PIXART ADNS-9500

ADNS-9500
Laser Gaming Sensor
DataSheet
Description
Features
The ADNS-9500 Laser gaming sensor comprises
of sensor and VCSEL in a single chip-on-board (COB)
package. ADNS-9500 provides enhanced features like programmable frame rate, programmable resolution, configurable sleep and wake up time to suit various PC gamers’
preferences.
 Small form factor chip-on-board package
The advanced class of VCSEL was engineered by PixArt
Imaging to provide a laser diode with a single longitudinal and a single transverse mode.
This Laser gaming sensor is in 16-pin integrated
chip-on-board (COB) package. It is designed to be used
with ADNS-6190-002 small form factor (SFF) gaming laser
lens to achieve the optimum performance featured in this
document. These parts provide a complete and compact
navigation system without moving part and laser calibration process is NOT required in the complete mouse form,
thus facilitating high volume assembly.
Theory of Operation
The sensor is based on Laser technology, which
measures changes in position by optically acquiring
sequential surface images (frames) and mathematically
determining the direction and magnitude of movement.
It contains an Image Acquisition System (IAS), a Digital
Signal Processor (DSP), and a four wire serial port. The
IAS acquires microscopic surface images via the lens and
illumination system. These images are processed by the
DSP to determine the direction and distance of motion.
The DSP calculates the x and y relative displacement
values. An external microcontroller reads the x and y
information from the sensor serial port. The microcontroller then translates the data into PS2, USB, or RF signals
before sending them to the host PC or game console.
 Dual power supply selections, 3V or 5V
 VDDIO range: 1.65 – 3.3V
 16-bits motion data registers
 High speed motion detection at 150ips and acceleration
up to 30g
 Advanced technology 832-865nm wavelength VCSEL
 Single mode lasing
 No laser power calibration needed
 Compliance to IEC/EN 60825-1 Eye Safety
– Class 1 laser power output level
– On-chip laser fault detect circuitry
 Self-adjusting frame rate for optimum performance
 Motion detect pin output
 Internal oscillator – no external clock input needed
 Enhanced Programmability
– Frame rate up to 11,750 fps
– 1 to 5 mm lift detection
– Resolution up to 5737.5cpi with ~22.5cpi step
– X and Y axes independent resolution setting
– Register enabled Rest Modes
– Sleep and wake up times
Applications
 Corded and cordless gaming laser mice
 Optical trackballs
 Motion input devices
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
1
PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Pinout of ADNS-9500 Optical Mouse Sensor
Pin No
Pin Name for 5V mode
Pin Name for 3V mode
Description
1
+VCSEL
+VCSEL
Positive Terminal Of VCSEL
2
LASER_NEN
LASER_NEN
LASER Enable (Active Low Output)
3
NCS
NCS
Chip Select (Active Low Input)
4
MISO
MISO
Serial Data Output (Master In/Slave Out)
5
SCLK
SCLK
Serial Clock Input
6
MOSI
MOSI
Serial Data Input (Master Out/Slave In)
7
MOTION
MOTION
Motion Detect (Active Low Output)
8
XYLASER
XYLASER
Laser Current Output Control
9
VDD5
VDD3
5V input for 5V mode
3V Input for 3V mode
10
PWR_OPT (GND)
PWR_OPT (VDD3)
Power Option:
Connect to GND for 5V Mode
Connect to VDD3 for 3V Mode
11
GND
GND
Analog Ground
12
REFB
VDD3
3V Regulator Output for 5V Mode
3V Input for 3V Mode
13
REFA
REFA
1.8V Regulator Output
14
DGND
DGND
Digital Ground
15
VDDIO
VDDIO
IO Voltage Input (1.65 - 3.3V)
16
-VCSEL
-VCSEL
Negative Terminal Of VCSEL
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
Product Code
Date Code
Lot Code
Item
Marking
Remarks
Product Number
A9500
Date Code
XYYWWZV
X = Subcon Code
YYWW = Date Code
Z = Sensor Die Source
V = VCSEL Die Source
Lot Code
VVV
Numeric
Figure 1. Package Pinout
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
2
PixArt Imaging Inc.
E-mail: [email protected]
PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Figure 2. Package outline drawing
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
3
PixArt Imaging Inc.
E-mail: [email protected]
PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Overview of Laser Mouse Sensor Assembly
B
B
Section B-B
2.40
0.094 Top of PCB to Surface
7.40
0.291 Bottom of lens flange to Surface
10.75 Top of Sensor to Surface
0.423
Note: Dimensions in millimeters/inches and for reference only.
Figure 3. 2D Assembly drawing of ADNS-9500 sensor and ADNS-6190-002 lens coupled with PCB and base plate
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
4
PixArt Imaging Inc.
E-mail: [email protected]
PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Figure 4. Isometric drawing of ADNS-9500 sensor and ADNS-6190-002 lens
12.96
5.02
Pin #1
Optical Center
14 X 1.78
12.60
10.90
6.30
1.70
0.50
16 X ∅ 0.80
Figure 5. Recommended PCB mechanical cutouts and spacing
Assembly Recommendation
1. Insert the COB sensor and all other electrical components into the application PCB.
2. This sensor package is only qualified for wave-solder
process.
3. Wave-solder the entire assembly in a no-wash soldering
process utilizing a solder fixture. The solder fixture is
needed to protect the sensor during the solder process.
The fixture should be designed to expose the sensor
leads to solder while shielding the optical aperture
from direct solder contact.
4. Place the lens onto the base plate. Care must be taken
to avoid contamination on the optical surfaces.
5. Remove the protective kapton tapes from the optical
aperture of the sensor and VCSEL respectively. Care
must be taken to keep contaminants from entering the
aperture.
6. Insert the PCB assembly over the lens onto the base
plate. The sensor package should self-align to the lens.
The optical position reference for the PCB is set by the
base plate and lens. The alignment guide post of the
lens locks the lens and integrated molded lead-frame
DIP sensor together. Note that the PCB motion due to
button presses must be minimized to maintain optical
alignment.
7. Optional: The lens can be permanently locked to the
sensor package by melting the lens’ guide posts over
the sensor with heat staking process.
8. Install the mouse top case. There must be a feature in
the top case (or other area) to press down onto the
sensor to ensure the sensor and lenses are interlocked
to the correct vertical height.
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5
PixArt Imaging Inc.
E-mail: [email protected]
VSS
-CPI
+CPI
VBUS
DD+
GND
SHIELD
1
2
3
4
5
P6
P5
P4
1
1
1
R1
1k
HEADER 5
H1
-CPI
+CPI
-CPI
1
1
3
5
7
9
CON1
2
4
6
8
10
SW4
SW5
JTAG
2
3
2
3
C5
100nF
R7
1k
VDD
C4
1uF/10V
+CPI
1
1
R6
0R
20R
20R
0R
R2
2
PIN HEADER 2.54MM10P/D
VDD
R5
0R
R3
R4
C2
10nF
J1
C3
20pF
6
VCC
1
CON2
2
4
6
8
8
RIGHT
ZA
MCU
P0.0
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P0.1/SCLK
P0.2/MISO
P0.3/MOSI
P0.4/NCS
P0.5
P0.6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
PCB SOCKET 2MM8P/D
7
VDD
C8
100nF
C2CK/RST
P3.0/C2D
P2.7
P2.6
VREGIN
VBUS
DD+
U1
LEFT
1
MIDDLE 3
ZB
5
9
10
11
12
7
8
5
4
C10
C7
1uF/10V 4.7uF/10V
R10
1k
C11
20pF
C9
100nF
VCC1
Figure 6a. Schematic Diagram for 5V Corded Mouse
R
W
G
B
VCC
1
VDD
2
27
18
17
16
15
14
13
1
32
31
30
29
28
26
25
24
23
22
21
20
19
+CPI
LED1
LED1
LED2
LED3
1
-CPI 1
+CPI 1
P3
P2
LEFT
VSS
-CPI
YELLOW
YELLOW
D3
YELLOW
D2
470R
R14
470R
R13
C1
100nF
SW1
Left Click
1
R8
10k
VDD
2
3
R IG H T
CPI Indication LED
LED3
LED2
470R
VCC
R12
C12
100nF
ZB
ZA
LEFT
RIGHT
MIDDLE
+CPI
-CPI
D1
8
3
7
4
SCLK
MISO
MOSI
NCS
MOTION
P1
VCC
WP
HOLD
VSS
EEPROM
25LC040P
CS
SCK
SI
SO
U2
SCLK
MISO
MOSI
NCS
MOTION
1
6
5
2
100k
VDD
C6
100nF
SW2
Right Click
1
1
0R
R15
2
VCSEL+VE
VCSEL-VE
XYLASER
VDDIO
VDD3 / VDD5
1
VDD1
2
3
C17
VDD2
10
SW3
Middle Click
C24 1
100nF
M ID D L E
R16
10k
VDD
100nF
C18
470pF
C15
VCC1
2
3
3
2
4
6
8
8
RIGHT
ZA
ZB
ZA
3
2
1
COM
B
A
Q1
VDD
3.3uF/16V
C20
PIN HEADER 2MM8P/D
CON3
10uF/10V
C23
Z-Encoder
7
LEFT
1
MIDDLE 3
ZB
5
1
100nF
C19
4.7uF/10V
100nF
C21
C22
1
VDD1
VDD1
1
VDD2
100nF
J4
J3
VDD2
C14
1uF/10V
C16
3
VDD1
VDD1
C13
10nF
VCC1
Sensor Block
10uF/10V
PWR_OPT
13
12
1
16
8
15
9
NTA4151P
Q2
VDD2
2
3
J2
LASER_NEN
SCLK
MISO
MOSI
ADNS-9500
NCS
REF A
MOTION
VDD3 / REF B
U3
R9
10k
VDD
2
5
4
6
3
7
VDD
DGND
14
6
VDD
C8051F347
GND
3
GND
11
2
6
2
R11
Application Circuits
10uF/16V
C4
J1
VDD3
B TI
B AT TE R Y
S E NS OR P A R T
C5
100nF
VDD3
100nF
C2
-
+
2
C8
100nF 1 6
9
10
12
13
15
14
11
C3
6
3
C9
2
U3 ADNS -9500
8
1
2
3
4
5
6
7
NTA4151P
Q1
1
X Y _L AS E R
3
2
VDD3
+VC S E L
VDD5/VDD3
P WR _OP T LAS E R _NE N
NCS
V DD3/R E FB
MIS O
R E FA
S CLK
VDDIO
MOSI
DG ND
MOTION
G ND
-V C S E L
S W2
MOUS E _B UT TON
C 10
470pF
1
VBAT
EN
U1
T P S 6 1070
L E FT C LIC K
C7
4.7uF/16V
100nF
VB AT
C6
4.7uF/16V
1uF/10V
S W S LI DE-S P S T
S W1
VOUT
FB
SW
7
Figure 6b. Schematic Diagram for 3V Cordless Mouse
3.3uF/16V
C 11
10uF/16V
C1
Note:
2 A A B attery 1.5v
C onnec ted in s eries
1
2
L1
4.7uH
GND
2
5
4
1
S W3
2
Q3
A
B
C OM
MOUS E _B UTT ON
1
R IG HT C L IC K
R3
180K
R2
820K
1
2
3
1
C 12
4.7uF/16V
VDD3
C 14
10uF/16V
J4
2
3
VDD3
R7
27K
MOUS E _B UT TON
J 12
J UMP E R _3
1
S W4
C E NTE R C LIC K
C 13
4.7uF/16V
R 2 = 8 20kohm V dd = 2. 8V
R 2 = 910kohm Vdd = 3. 0V
R 2 = 1 Mohm = 3. 3V
1
2
NO T E :
2
R8
27K
MMB T 2222A
R4
0R
VDD3
1
2
3
2
2
R 12
OR
VDD3
Q2 1
J10
R9
1
R 13
47K
VDD3
J 13
499R
R5
Open
R6
60R4
VB AT
BLUE
D3
R 11
1K
1
3
5
7
9
2
P US H B UTT ON
S W5
1
1
2
2
VDD3
R es olution C hange
Notes:
Us e jumper wir e
J6
J5
S OC Debug/flas h
P INR OW_2X5
J 11
2
4
6
8
10
1
31
13
5
6
7
8
9
11
12
14
15
16
4
3
1
36
35
34
33
32
2
10
28
29
30
C 17
100nF
R 15
0R
VDD3
R 14
0R
V AB T
R E S E T _N
P 0_7
P 0_0/AT E S T
P 0_1
P 0_2
P 0_3
P 0_4
P 0_5
P 0_6
P 1_0/L E D
P 1_1/L E D
P 1_2
P 1_3
P 1_4
P 1_5
P 1_6
P 1_7
P 2_0
P 2_1
P 2_2
DVV D
DVV D
DG UAR D
DVV D
DC OUP L
U4
T I C C 2510
AVDD
AVDD
AVDD
AVDD
37
27
21
20
17
19
24
23
19
22
25
26
100pF
C25
C23
100pF
C 18
22nF
O N 3 s ec
OFF
OFF
B atter y Low Level Detec tion
R 14 on, R 15 off = = E nabl e
R 14 off, R 15 on = = Dis able
G ND E xpos ed
R BI AS
XOS C _Q1
XOS C _Q2
P 2_3/XOS 32_Q2
P 2_3/XOS C32_Q1
R F_N
R F _P
B li nkin g O n 1 s e c , O F F 1 s e c
L o w batter y ( <2 . 2 0 V )
C 16
B li nkin g O n 1 s e c , Off 4 s e c
L o w batter y ( 2 . 2 5 – 2. 3 5 V )
100nF
O N 3 s ec
6 0 0 0 c pi
C 15
100nF
OFF
O N 3 s ec
3 2 0 0 c pi
VDD3
YE LL OW
D2
R 10
1K
VDD3
OFF
OFF
1 6 0 0 c pi( d efa ult)
O N 3 s ec
OFF
R 16
56K
C 19
100nF
L E D 2 (P 1_1)
L E D1 ( Pl _0)
1 0 0 0 c pi
L E D I n d i c a ti o n T a b l e :
I n di c a ti o n
C 27
22pF
1
L5
12nH
C 22
1pF
C 20
100nF
X1
26MHz
3
C26
1pF
1.2nH
L4
C 21
22onF
J7
VDD3
2
1
1
1
2
C28
22pF
J9
1
1
C 29
1.5pF
OR
R 18
R 17
OR
2.4G hz S ingle E nded A ntenna
2
Hor izontal S croll (S witc h)
2
J8
2
C 24
1.8pF
1.2nH
L6
EI
ANT E NNA
1
7
PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Eye Safety
The ADNS-9500 sensor and the associated components
in the schematic of Figure 6 are intended to comply with
Class 1 Eye Safety Requirements of IEC 60825-1. PixArt
Imaging calibrates the sensor’s laser output power
(LOP) to Class 1 eye safety level and store the registers
values that control the LOP prior shipping out, thus no
LOP calibration is required in complete mouse system at
manufacturer site.
Figure 7. Block diagram of ADNS-9500
Regulatory Requirements
 Passes FCC B and worldwide analogous emission limits
when assembled into a mouse with shielded cable and
following PixArt recommendations.
 Passes IEC-1000-4-3 radiated susceptibility level when
assembled into a mouse with shielded cable and
following PixArt recommendations.
 Passes EN61000-4-4/IEC801-4 EFT tests when
assembled into a mouse with shielded cable and
following PixArt recommendations.
 Passes IEC-61000-4-2 Electrostatic Discharge Immunity
Test (ESD) and provides sufficient ESD creepage/
clearance distance to withstand discharge up to 15KV
when assembled into a mouse according to usage
instructions above.
 Passes IEC/EN 60825-1 Eye Safety Class 1 when
operating with the laser output power pre-calibrated
by PixArt Imaging without external hardware and
software control of laser current.
Design Considerations for Improving ESD Performance
For improved electrostatic discharge performance, typical
creepage and clearance distance are shown in the table
below. Assumption: base plate construction as per the
PixArt supplied 3D model file when use with ADNS6190-002 lens. The lens flange can be sealed (i.e. glued)
to the base plate. Note that the lens material is polycarbonate and therefore, cyanoacrylate based adhesives or
other adhesives that may damage the lens should NOT be
used.
ADNS-9500 sensor is designed to maintain the laser
output power using ADNS-6190-002 lens within Class 1
Eye Safety requirements over components manufacturing tolerances under the recommended operating conditions and application circuits of Figure 6 as specified in
this document. Under normal operating conditions, the
sensor generates the drive current for the VCSEL. Increasing the LOP by other means on hardware and software
can result in a violation of the Class 1 eye safety limit of
716W. For more information, please refer to Eye Safety
Application Note.
LASER Drive Mode
The laser is driven in pulsed mode during normal operation.
A calibration mode is provided which drives the laser in
continuous (CW) operation for testing purpose.
The default setting of laser is in Forced_Disable mode,
which the laser is turned OFF. The laser have to be turned
ON during power up sequence by setting Forced_ Disabled
bit (Bit-0) of LASER_CTRL0 register to 0.
Disabling the LASER
LASER_NEN is connected to the gate of an external Pchannel MOSFET transistor which, when ON connects
REFB to the laser. In normal operation, LASER_NEN is low.
In the case of a fault condition, LASER_NEN goes high to
turn the transistor off and disconnect REFB from the laser.
Typical Distance (mm)
ADNS-6190-002
Creepage
17.3
Clearance
1.8
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8
PixArt Imaging Inc.
E-mail: [email protected]
PixArt Imaging Inc.
ADNS-9500 LaserStream™Gaming Sensor
LASER Output Power (LOP)
Single Fault Detection
The LOP can be measured for testing purpose as per steps
below.
ADNS-9500 sensor is able to detect a short circuit or fault
condition at –VCSEL pin, which could lead to excessive
laser output power. A leakage path to ground on this
node will trigger the fault detection circuit, which will turn
off the laser drive current source and set the LASER_NEN
output high. When used in combination with external
component as shown in the block diagram below, the
system will prevent excessive laser power for a resistive
path at XY_LASER by shutting off the laser. In addition
to the ground path fault detection described above, the
fault detection circuit is periodically checking for proper
operation by internally generating a path to ground with
the laser turned off via LASER_NEN. If the –VCSEL pin is
shorted to VDD5, VDD3, REFA or REFB pin, this test will fail
and will be reported as a fault.
1. Power up reset the mouse system.
2. Enable the laser by setting Forced_Disabled bit of
LASER_CTRL0 register (address 0x20) to 0.
3. Enable the Calibration mode by writing 010b to bits
[3,2,1] of LASER_CTRL0 register (address 0x20) to set
the laser to continuous (CW) mode.
4. Measure the LOP at the navigation surface plane.
The pre-calibrated LOP value at typical operating supply
voltage and temperature of 25 ± 5°C should not exceeding
506μW, otherwise the LOPmax limit in the Absolute
Maximum Rating is applicable. The following conditions
apply:
 The system is operated within the recommended
operating supply voltage and temperature range.
 In 3V mode, the VDD3 value is no greater than 300mV
above the pre-calibration voltage of 3.0V. In 5V mode,
REFB should be used to drive the PMOSFET connecting
to VCSEL.
 No allowance for optical power meter accuracy is
assumed.
VDD3/REFB
(Pin 12)
ADNS-9500
Microcontroller
S
LASER DRIVER
LASER_NEN
G
P_MOSFET
VDD3
D
fault control
block
VCSEL
Serial port
+VCSEL
voltage sense
470 pF
current set
–VCSEL
GND
Figure 8. Single Fault Detection and Eye-safety Feature Block Diagram
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9
PixArt Imaging Inc.
E-mail: [email protected]
PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Storage Temperature
TS
-40
85
°C
260
°C
Lead-Free Solder Temp
Supply Voltage
Notes
For 7 seconds, 1.8mm below seating plane. Refer to soldering reflow profile in PCB Assembly
& Soldering Considerations Application Note
AN 5023.
VDD5
-0.5
5.5
V
VDD3
-0.5
3.4
V
VDDIO
-0.5
3.4
V
2
kV
All Pins
3.4
V
All I/O Pins
ESD (Human body model)
-0.5
Input Voltage
VIN
Laser Output Power
LOPmax
716
W
Class 1 Eye Safety Limit
VCSEL DC Forward Current
IF
7
mA
For maximum duration of 240 hrs Applicable
when driving VCSEL externally and internally
using sensor's laser registers setting Refer to
reliability datasheet.
VCSEL Reverse Voltage
VR
5
V
I = 10 μA
Comments:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are the stress ratings only and functional operation of the device at these or any other condition beyond those indicated for
extended period of time may affect device reliability.
2. The inherent design of this component causes it to be sensitive to electrostatic discharge. The ESD threshold is listed above.
To prevent ESD-induced damage, take adequate ESD precautions when handling this product.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
10
PixArt Imaging Inc.
E-mail: [email protected]
PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Recommended Operating Conditions
Parameter
Symbol
Minimum
Operating Temperature
TA
0
Supply voltage
VDD5
Power supply rise time
Typical
Maximum
Units
Notes
40
°C
4.0
5.0
5.25
Volts
Including Supply Noise for 5V
mode
VDD3
2.7
2.8
3.3
Volts
Including Supply Noise for 3V
mode
VDDIO
1.65
3.3
Volts
Including noise.
VRT5
1
100
ms
0 to 5.0V for 5V mode
VRT3
1
100
ms
0 to 2.8V for 3V mode
Supply noise (Sinusoidal)
VNA
100
mVp-p
50kHz - 50MHz
Serial Port Clock Frequency
fSCLK
2
MHz
Active drive, 50% duty cycle
Distance from lens reference
plane to surface
Z
2.40
2.62
mm
Results in +/- 0.22mm minimum
DOF. Refer to Figure 9.
Speed
S
150
200
ips
inch/sec
Maximum speed performance on
select gaming surfaces.
2.18
Acceleration
A
30
g
In Run mode only
Load Capacitance
Cout
100
pF
MOTION, MISO
Frame Rate
FR
11,750
fps
Frame per second
VCSEL Peak Wavelength

865
nm
832
Z
Figure 9. Distance from lens reference plane to surface, Z
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11
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ADNS-9500 Laser Gaming Sensor
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. (Typical values at 25 °C, VDD3 = 2.8V, VDDIO = 1.8V)
Parameter
Symbol
Minimum
Motion delay after reset
tMOT-RST
30
Typical
Maximum
Shutdown
tSTDWN
Wake from shutdown
tWAKEUP
Forced Rest enable
tREST-EN
1
s
Wake from Forced Rest
tREST-DIS
1
s
MISO rise time
tr-MISO
50
200
ns
From RESTEN bits cleared to valid
motion
CL = 100pF
MISO fall time
tf-MISO
50
200
ns
CL = 100pF
MISO delay after SCLK
tDLY-MISO
120
ns
MISO hold time
thold-MISO
200
ns
MOSI hold time
thold-MOSI
200
ns
MOSI setup time
tsetup-MOSI
120
ns
From SCLK falling edge to MISO data
valid, no load conditions
Data held until next falling SCLK
edge
Amount of time data is valid after
SCLK rising edge
From data valid to SCLK rising edge
SPI time between
write commands
tSWW
120
s
SPI time between write and
read commands
tSWR
120
s
SPI time between read and
subsequent commands
tSRW
tSRR
20
s
SPI read address-data delay
tSRAD
100
s
NCS inactive after motion
burst
NCS to SCLK active
tBEXIT
500
ns
tNCS-SCLK
120
ns
SCLK to NCS inactive
(for read operation)
SCLK to NCS inactive
(for write operation)
NCS to MISO high-Z
tSCLK-NCS
120
ns
tSCLK-NCS
20
us
MOTION rise time
tr-MOTION
MOTION fall time
tf-MOTION
Transient Supply Current
500
30
Units
Notes
ms
From SW_RESET register write to
valid motion, assuming motion is
present
From Shutdown mode active to low
current
From Shutdown mode inactive to
valid motion. Notes: A RESET must
be asserted after a shutdown. Refer
to Shutdown
section, also note tMOT-RST
From RESTEN bits set to low current
ms
ms
500
ns
50
200
ns
From rising SCLK for last bit of the
first data byte, to rising SCLK for last
bit of the second data byte.
From rising SCLK for last bit of the
first data byte, to rising SCLK for last
bit of the second address byte.
From rising SCLK for last bit of the
first data byte, to falling SCLK for the
first bit of the address byte of the
next command.
From rising SCLK for last bit of the
address byte, to falling SCLK for first
bit of data being read.
Minimum NCS inactive time after
motion burst before next SPI usage
From last NCS falling edge to first
SCLK rising edge
From last SCLK rising edge to NCS rising edge, for valid MISO data transfer
From last SCLK rising edge to NCS rising edge, for valid MOSI data transfer
From NCS rising edge to MISO high-Z
state
CL = 100pF
50
200
ns
CL = 100pF
IDDT5
90
mA
IDDT3
65
mA
Max supply current during a VDD5
ramps from 0 to 5.0V
Max supply current during a VDD3
ramps from 0 to 2.8V
tNCS-MISO
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12 E-mail: [email protected]
PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
DC Electrical Specifications
Electrical Characteristics over recommended operating conditions.
For 3V mode, Typical values at 25°C, VDD = 2.8 V, VDDIO = 2.8V. For 5V mode, Typical values at 25°C, VDD = 5.0 V, VDDIO = REFB
Parameter
Symbol
DC Supply Current in
3V mode
Minimum
Typical
Maximum
Units
Notes
IDD_RUN3
33
45
mA
IDD_REST1
0.26
0.4
mA
Average current, including LASER
current. No load on MISO, MOTION.
IDD_REST2
0.12
0.2
mA
IDD_REST3
0.08
0.15
mA
DC Supply Current in
5V mode
IDD_RUN5
36
50
mA
Peak Supply Current
IDDP3
60
mA
For 3V mode
IDDP5
65
mA
For 5V mode
65
140
A
NCS, SCLK, MOSI = VDDIO
MISO = GND
3.05
3.25
V
Do not connect this pin as a
supply to other chips other than
the integrated VCSEL and VDDIO
0.3*VDDIO
V
SCLK, MOSI, NCS
V
SCLK, MOSI, NCS
mV
SCLK, MOSI, NCS
±10
A
Vin = 0.7*VDDIO , SCLK, MOSI, NCS
0.3*VDDIO
V
Iout = 1mA, MISO, MOTION
V
Iout = -1mA, MISO, MOTION
V
Iout = 1mA, LASER_NEN
V
Iout = -0.5mA, LASER_NEN
pF
MOSI, NCS, SCLK
Shutdown Supply Current
IDDSTDWN
REFB Output Voltage
VREFB
Input Low Voltage
VIL
Input High Voltage
VIH
Input Hysteresis
VI_HYS
100
Input Leakage Current
Ileak
±1
Output Low Voltage,
MISO, MOTION
VOL
Output High Voltage,
MISO, MOTION
VOH
Output Low Voltage,
LASER_NEN
VOL
Output High Voltage,
LASER_NEN
VOH
Input Capacitance
Cin
2.85
0.7*VDDIO
0.7*VDDIO
0.3*VREFB
0.7*VREFB
10
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ADNS-9500 Laser Gaming Sensor
Sensor’s Typical Performance Characteristics
1800
1600
1400
1200
1000
800
600
400
200
0
White Paper
Photo Paper
Manila
Spruce Wood
Black Formica
White Formica
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
White Delrin
1.6
Resolution (cpi)
Resolution Vs. Z
Straight Line At 45 Degrees, Path Length = 4 inches; Speed = 6 ips ; Resolution = 1600cpi
Distance from Lens Reference Plane to Navigation Surface, Z (mm)
Figure 10. Mean Resolution vs. Z at default resolution at 1600cpi
Typical Path Deviation
Largest Single Perpendicular Deviation From A Straight Line At 45 Degrees
Path Length = 4 inches; Speed = 6 ips ; Resolution = 1600cpi
Maximum Distance (Mouse Counts)
30
White Paper
25
Photo Paper
20
Manila
15
Spruce Wood
10
Black Formica
White Formica
5
White Delrin
0
1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4
Distance from Lens Reference Plane to Navigation Surface, Z (mm)
Relative Responsivity
Figure 11. Average Error vs. Distance at default resolution at 1600cpi (mm)
Relative Responsivity Vs. Wavelength
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
400
450
500
550
600
650 700 750
Wavelength (nm)
800
850
900
950
1000
Figure 12. Wavelength Responsivity
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ADNS-9500 Laser Gaming Sensor
Synchronous Serial Port
Chip Select Operation
The synchronous serial port is used to set and read parameters in the ADNS-9500 Sensor, and to read out the motion
information. The serial port is also used to load PROM data
into the ADNS-9500 Sensor.
The serial port is activated after NCS goes low. If NCS is
raised during a transaction, the entire transaction is
aborted and the serial port will be reset. This is true for all
transactions including PROM download. After a transaction is aborted, the normal address-to-data or transactionto-transaction delay is still required before beginning the
next transaction. To improve communication reliability,
all serial transactions should be framed by NCS. In other
words, the port should not remain enabled during periods
of non-use because ESD and EFT/B events could be interpreted as serial communication and put the chip into an
unknown state. In addition, NCS must be raised after each
burst-mode transaction is complete to terminate burstmode. The port is not available for further use until burstmode is terminated.
The port is a four wire port. The host micro-controller
always initiates communication; the ADNS-9500 Sensor
never initiates data transfers. SCLK, MOSI, and NCS may be
driven directly by a micro-controller. The port pins may be
shared with other SPI slave devices. When the NCS pin is
high, the inputs are ignored and the output is tri-stated.
The lines that comprise the SPI port are:
SCLK: Clock input. It is always generated by the master
(the micro-controller).
MOSI: Input data. (Master Out/Slave In)
Write Operation
MISO: Output data. (Master In/Slave Out)
Write operation, defined as data going from the microcontroller to the ADNS-9500 Sensor, is always initiated by
the micro-controller and consists of two bytes. The first
byte contains the address (seven bits) and has a “1” as its
MSB to indicate data direction. The second byte contains
the data. The ADNS-9500 Sensor reads MOSI on rising
edges of SCLK.
NCS: Chip select input (active low). NCS needs to be low
to activate the serial port; otherwise, MISO will be high
Z, and MOSI & SCLK will be ignored. NCS can also be used
to reset the serial port in case of an error.
Motion Pin
The motion pin is an active low output that signals the
micro-controller when motion has occurred. The motion
pin is lowered whenever the motion bit is set; in other
words, whenever there is data in the Delta_X_L, Delta_XH,
Delta_Y_L or Delta_Y_H registers. Clearing the motion
bit (by reading Delta_X_L, Delta_XH, Delta_Y_L and
Delta_Y_H, or writing to the Motion register) will put the
motion pin high.
NCS
SCLK
MOSI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
1
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
A6
MISO
MOSI Driven by Micro-Controller
Figure 13. Write Operation
SCLK
MOSI
tHold,MOSI
tsetup , MOSI
Figure 14. MOSI Setup and Hold Time
15
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ADNS-9500 Laser Gaming Sensor
Read Operation
A read operation, defined as data going from the ADNS-9500 Sensor to the micro-controller, is always initiated by the
micro-controller and consists of two bytes. The first byte contains the address, is sent by the micro-controller over MOSI,
and has a “0” as its MSB to indicate data direction. The second byte contains the data and is driven by the ADNS-9500
Sensor over MISO. The sensor outputs MISO bits on falling edges of SCLK and samples MOSI bits on every rising edge of
SCLK.
NCS
SCLK
Cycle #
1
2
3
4
5
6
7
A6
A5
A4
A3
A2
A1
8
9
10
11
12
13
14
15
16
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
MOSI
0
MISO
A0
tSRAD delay
Figure 15. Read Operation
SCLK
MISO
NOTE:
The minimum high state of SCLK is also the minimum MISO data hold
time of the ADNS-9500 Sensor. Since the falling edge of SCLK is actually
the start of the next read or write command, the ADNS-9500 Sensor will
hold the state of data on MISO until the falling edge of SCLK.
tHOLD-MISO
tDLY-MISO
D0
Figure 16. MISO Delay and Hold Time
Required timing between Read and Write Commands (tsxx)
There are minimum timing requirements between read and write commands on the serial port.
tSWW
SCLK
Address
Data
Write Operation
Address
Data
Write Operation
Figure 17. Timing between two write commands
If the rising edge of the SCLK for the last data bit of the second write command occurs before the tsww delay, then the
first write command may not complete correctly.
tSWR
SCLK
Address
Data
Write Operation
Address
Next Read
Operation
Figure 18. Timing between write and read commands
If the rising edge of SCLK for the last address bit of the read command occurs before the tswr required delay, the write
command may not complete correctly.
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ADNS-9500 Laser Gaming Sensor
tSRW & tSRR
tSRAD for read
SCLK
Address
Data
Read Operation
Address
Next Read or
Write Operation
Figure 19. Timing between read and either write or subsequent read commands
During a read operation SCLK should be delayed at least
tSRAD after the last address data bit to ensure that the
Sensor has time to prepare the requested data.
The falling edge of SCLK for the first address bit of either
the read or write command must be at least TSRR or
TSRW after the last SCLK rising edge of the last data bit
of the previous read operation. In addition, during a read
operation SCLK should be delayed after the last address
data bit to ensure that the ADNS-9500 Sensor has time to
prepare the requested data.
Burst Mode Operation
Burst mode is a special serial port operation mode which
may be used to reduce the serial transaction time for three
predefined operations: motion read, PROM download
and frame capture. The speed improvement is achieved
by continuous data clocking to or from multiple registers
without the need to specify the register address, and
by not requiring the normal delay period between data
bytes.
Motion Burst Read
Reading the Motion_Burst register activates this mode.
The ADNS-9500 sensor will respond with the contents
of the Motion, Observation, Delta_X_L, Delta_X_H,
Delta_Y_L, Delta_Y_H, Pixel Statistic, Shutter and Frame
period registers in that order. After sending the register
address, the micro-controller must wait one frame, and
then begin reading data. All data bits can be read with
no delay between bytes by driving SCLK at the normal
rate. The data are latched into the output buffer after the
last address bit is received. After the burst transmission is
complete, the micro-controller must raise the NCS line for
at least tBEXIT to terminate burst mode. The serial port is
not available for use until it is reset with NCS, even for a
second burst transmission.
tSRAD
SCLK
Motion_Burst Register Address
Read First Byte
First Read Operation
Read Second Byte
Read Third Byte
Figure 20. Motion Burst Timing
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ADNS-9500 Laser Gaming Sensor
Procedure to start motion burst:
SROM Download
1. Lower NCS
This function is used to load the PixArt supplied firmware
file contents into the ADNS-9500 after sensor power up
sequence. The firmware file is an ASCII text file. There are
2 methods of SROM downloading in ADNS-9500:1.5K and
3K bytes. 1.5K SROM download will only download 1.5K
bytes data into the first half of SROM and leave the rest
empty, while 3K SROM download will download the full
3K bytes data into SROM. They can be selected through
Configuration_IV register, where default setting is 1.5K
SROM download. In the current version of ADNS-9500
sensor, 3K bytes of SROM will be used.
2. Send 0x50 to Motion_Burst register.
3. Wait for one frame. (This only applicable in Run mode
for wakeup but not require for rest mode)
4. Start reading SPI Data continuously up to 14bytes.
Motion burst may be terminated by pulling NCS high
for at least tBEXIT.
5. To read new motion burst data, repeating from step 1.
6. Write any value to Motion register (address 0x02) to
clear any residual motion.
SROM download procedure:
Motion burst reporting:
1. Select the 3K bytes SROM size at Configuration_IV
register, address 0x39
BYTE [00] = Motion
BYTE [01] = Observation
BYTE [02] = Delta_X_L
BYTE [03] = Delta_X_H
BYTE [04] = Delta_Y_L
BYTE [05] = Delta_Y_H
BYTE [06] = SQUAL
BYTE [07] = Pixel_Sum
BYTE [08] = Maximum_Pixel
BYTE [09] = Minimum_Pixel
BYTE [10] = Shutter_Upper
BYTE [11] = Shutter_Lower
BYTE [12] = Frame_Period_Upper
BYTE [13] = Frame_Period_Lower
2. Write 0x1d to SROM_Enable register for initializing
3. Wait for one frame
4. Write 0x18 to SROM_Enable register again to start
SROM downloading
5. Write SROM file into SROM_Load_Burst register, 1st data
must start with SROM_Load_Burst register address. All
the SROM data must be downloaded before SROM
start running.
Note: In rest mode, motion burst data is always available or in other
words, motion burst data can be read from Motion_Burst register even
in rest modes.
exit burst mode
tBEXIT ≥1 s
NCS
2 reg writes, see text
SROM_Enable reg write
MOSI
address key data
SROM_Load reg write
byte 1
address
byte 2
byte 3070
address
enter burst
mode
≥ 1 frame
period
SCLK
tNCS-SCLK
>120ns
≥10 s
≥120 s
≥15 s
≥15 s
≥160 s
Soonest to read SROM_ID
Figure 21. SROM Download Burst Mode
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ADNS-9500 Laser Gaming Sensor
Frame Capture
This is a fast way to download a full array of pixel values
from a single frame. This mode disables navigation and
overwrites any downloaded firmware. A hardware reset
is required to restore navigation, and the SROM firmware
must be reloaded.
To trigger the capture, write to the Frame_Capture register.
The next available complete 1 frame image will be stored
to memory. The data are retrieved by reading the Pixel_
Burst register once using the normal read method, after
which the remaining bytes are clocked out by driving
SCLK at the normal rate. If the Pixel_Burst register is read
before the data is ready, it will return all zeros.
Procedure of Frame Capture:
1. Reset the chip by writing 0x5a to Power_Up_Reset
register (address 0x3a).
2. Enable laser by setting Forced_Disable bit (bit-0) of
LASER_CTRL0 register to 0.
3. Write 0x93 to Frame_Capture register.
4. Write 0xc5 to Frame_Capture register.
5. Wait for two frames.
6. Check for first pixel by reading bit zero of Motion
register. If =1, first pixel is available.
7. Continue read from Pixel_Burst register until all 900
pixels are transferred.
8. Continue step 3-7 to capture another frame.
Note: Manual reset and SROM download are needed after frame capture
to restore navigation for motion reading.
exit burst mode
tBEXIT ≥4 s
NCS
2 reg write to enter
frame capture mode
address
data
MOSI
pixel dump reg read
address
frame capture reg
address
enter burst
mode
SCLK
tNCS-SCLK
>120ns
MISO
soonest to begin again
Wait for
2 frames
tSRAD
P1
tLOAD
≥15 s
P2
P900
Figure 22. Frame Capture Burst Mode
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19
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≥100 s
PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Cable
Top Xray View of Mouse
Positive Y
LB
RB
Positive X
1
8
A9500
16
9
expanded view of the
surface as viewed
through the lens
last output
29 59 89 119 149 179 209 239 269 299 329 359 389 419 449 479 509 539 569 599 629 659 689 719 749 779 809 839 869 899
28 58 88 118 148 178 208 238 268 298 328 358 388 418 448 478 508 538 568 598 628 658 688 718 748 778 808 838 868 898
27 57
t
t
t
etc. t
t
t 842 872
1
31 61 91 121 151 181 211 241 271 301 331 361 391 421 451 481 511 541 571 601 631 661 691 721 751 781 811 841 871
0
30 60 90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720 750 780 810 840 870
first output
Figure 23. Pixel Map (Surface referenced)
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20
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ADNS-9500 Laser Gaming Sensor
Power Up
The ADNS-9500 Sensor does not perform an internal
power up self-reset; the Power_Up_Reset register must
be written every time power is applied. The appropriate
sequence is as follows:
5. Read from registers 0x02, 0x03, 0x04, 0x05 and 0x06
(or read these same 5 bytes from burst motion register)
one time regardless of the motion pin state.
1. Apply power to VDD5/VDD3 and VDDIO in any order
7. Enable laser by setting Forced_Disable bit (bit-0) of
LASER_CTRL0 register (address 0x20) to 0.
2. Drive NCS high, and then low to reset the SPI port.
3. Write 0x5a to Power_Up_Reset register (address 0x3a).
4. Wait for at least 50ms time.
6. SROM download.
During power-up there will be a period of time after the
power supply is high but before any clocks are available.
The table below shows the state of the various pins during
power-up and reset.
State of Signal Pins After VDD is Valid
Pin
On Power-Up
NCS High before Reset
NCS Low before Reset
After Reset
NCS
Functional
Hi
Low
Functional
MISO
Undefined
Undefined
Functional
Depends on NCS
SCLK
Ignored
Ignored
Functional
Depends on NCS
MOSI
Ignored
Ignored
Functional
Depends on NCS
MOTION
Undefined
Undefined
Undefined
Functional
LASER_NEN
Undefined
Undefined
Undefined
Functional
Shutdown
The ADNS-9500 can be set in Shutdown mode by writing
0xb6 to register 0x3b. The SPI port should not be accessed
when Shutdown mode is asserted, except the power-up
command (writing 0x5a to register 0x3a). (Other ICs on
the same SPI bus can be accessed, as long as the sensor’s
NCS pin is not asserted.) The table below shows the state
of various pins during shutdown. To deassert Shutdown
mode:
1. Drive NCS high, then low to reset the SPI port.
2. Write 0x5a to Power_Up_Reset register (address 0x3a).
3. Wait for at least 50ms time.
4. Clear observation register.
5. Wait at least one frame and check observation register,
Bit[5:0] must be set.
6. Read from registers 0x02, 0x03, 0x04, 0x05 and 0x06
(or read these same 5 bytes from burst motion register)
one time regardless of the motion pin state.
7. SROM download.
8. Enable laser by setting Forced_Disable bit (bit-0) of
LASER_CTRL0 register to 0.
9. Any register setting must then be reloaded.
Pin
Status when Shutdown Mode
NCS
Functional *1
MISO
Undefined *2
SCLK
Ignore if NCS = 1 *3
MOSI
Ignore if NCS = 1 *4
LASER_NEN
High (off )
MOTION
Undefined *2
*1 NCS pin must be held to 1 (high) if SPI bus is shared with other
devices. It is recommended to hold to 1 (high) during Power Down
unless powering up the Sensor. It must be held to 0 (low) if the sensor
is to be re-powered up from shutdown (writing 0x5a to register
0x3a).
*2 Depends on last state. MISO should be configured to drive LOW
during shutdown to meet the low current consumption as specified
in the datasheet. This can be achieved by reading Inverse_Product_
ID register (address 0x3f ) since the return value (0xcc) on MISO line
ends in a 0 (low state).
*3 SCLK is ignored, if NCS is 1 (high). It is functional if NCS is 0 (low).
*4 MOSI is ignored, if NCS is 1 (high). If NCS is 0 (low), any command
present on the MOSI pin will be ignored except power-up command
(writing 0x5a to register 0x3a).
Note:
There are long wakeup times from shutdown and forced Rest. These
features should not be used for power management during normal
mouse motion.
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ADNS-9500 Laser Gaming Sensor
Registers
The ADNS-9500 registers are accessible via the serial port. The registers are used to read motion data and status as well
as to set the device configuration.
Address
Register
Read/Write
Default Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
0x10
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
0x20
0x21- 0x23
0x24
0x25
0x26
0x27 - 0x29
0x2a
0x2e
0x2f
0x30 - 0x38
0x39
0x3a
0x3b
0x3c - 0x3e
0x3f
0x40 – 0x4f
0x50
0x62
0x64
Product_ID
Revision_ID
Motion
Delta_X_L
Delta_X_H
Delta_Y_L
Delta_Y_H
SQUAL
Pixel_Sum
Maximum_Pixel
Minimum_Pixel
Shutter_Lower
Shutter_Upper
Frame_Period_Lower
Frame_Period_Upper
Configuration_I
Configuration_II
Frame_Capture
SROM_Enable
Run_Downshift
Rest1_Rate
Rest1_Downshift
Rest2_Rate
Rest2_Downshift
Rest3_Rate
Frame_Period_Max_Bound_Lower
Frame_Period_Max_Bound_Upper
Frame_Period_Min_Bound_Lower
Frame_Period_Min_Bound_Upper
Shutter_Max_Bound_Lower
Shutter_Max_Bound_Upper
LASER_CTRL0
Reserved
Observation
Data_Out_Lower
Data_Out_Upper
Reserved
SROM_ID
Lift_Detection_Thr
Configuration_V
Reserved
Configuration_IV
Power_Up_Reset
Shutdown
Reserved
Inverse_Product_ID
Reserved
Motion_Burst
SROM_Load_Burst
Pixel_Burst
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x33
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x20
0x4e
0xc0
0x5d
0x12
0x00
0x00
0x00
0x32
0x01
0x1f
0x09
0xbc
0x31
0xc0
0x5d
0xa0
0x0f
0x20
0x4e
0x81
R/W
R
R
0x00
Undefined
Undefined
R
R/W
R/W
0x00
0x10
0x12
R/W
W
W
0x00
NA
Undefined
R
0xcc
R
W
R
0x00
Undefined
0x00
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22
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ADNS-9500 Laser Gaming Sensor
Product_ID
Access: Read Only
Address: 0x00
Reset Value: 0x33
Bit
7
6
5
4
3
2
1
0
Field
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0
Data Type: 8-bit unsigned integer.
USAGE: This value is a unique identification assigned to this model only. The value in this register does not change; it can
be used to verify that the serial communications link is functional.
Revision_ID
Access: Read Only
Address: 0x01
Reset Value: 0x03
Bit
7
6
5
4
3
2
1
0
Field
RID7
RID6
RID5
RID4
RID3
RID2
RID1
RID0
Data Type: 8-bit unsigned integer.
USAGE: This register contains the current IC revision, the revision of the permanent internal firmware. It is subject to
change when new IC versions are released.
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ADNS-9500 Laser Gaming Sensor
Motion
Access: Read Only
Address: 0x02
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
MOT
FAULT
LP_Valid
Reserved
Reserved
OP_Mode1
OP_Mode2
FRAME_
Pix_First
Data Type: Bit field
USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If the MOT
bit is set, Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H register should be read in sequence to get the accumulated motion. Read this register before reading the Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H
registers as reading this register freezes the Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H register values. If
Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H registers are not read before the Motion register is read for the
second time, the data in Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H will be lost. Writing anything to this
register clears the MOT bit, Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H registers. The written data byte is
not saved.
It also tells if laser fault, laser power setting status and operating mode in current frame.
Field Name
Description
MOT
Motion since last report or Shutdown
0 = No motion
1 = Motion occurred, data ready for reading in Delta_X_L, Delta_X_H, Delta_Y_L and
Delta_Y_H registers
FAULT
Indicates that the XY_LASER is shorted to GND.
0 = no fault detected
1 = fault detected
LP_Valid
Laser Power Settings
0 = Laser power register values do not have complementary values
1 = laser power is valid
OP_Mode[1:0]
Operating mode of the sensor
00 = Run
01 = Rest 1
10 = Rest 2
11 = Rest 3
FRAME_Pix_First
This bit is set to indicate first pixel in frame capture.
0 = Frame capture data not from pixel 0,0
1 = Frame capture data is from pixel 0,0
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ADNS-9500 Laser Gaming Sensor
Delta_X_L
Access: Read Only
Address: 0x03
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
X7
X6
X5
X4
X3
X2
X1
X0
Data Type: 16 bits 2’s complement number. Lower 8 bits of Delta_X.
USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading it clears the
register.
Motion
-32768
-32767
-2
-1
0
+1
+2
Delta_X
8000
8001
FE
FF
00
01
02
Delta_X_H
Access: Read Only
+32766 +32767
7FFE
7FFF
Address: 0x04
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
X15
X14
X13
X12
X11
X10
X9
X8
Data Type: 16 bits 2’s complement number. Upper 8 bits of Delta_X.
USAGE: Delta_X_H must be read after Delta_X_L to have the full motion data. Reading it clears the register.
Delta_Y_L
Access: Read Only
Address: 0x05
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data Type: 16 bits 2’s complement number. Lower 8 bits of Delta_Y.
USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading it clears the
register.
Motion
-32768
-32767
-2
-1
0
+1
+2
Delta_Y
8000
8001
FE
FF
00
01
02
Delta_Y_H
Access: Read Only
+32766 +32767
7FFE
7FFF
Address: 0x06
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Data Type: 16 bits 2’s complement number. Upper 8 bits of Delta_Y.
USAGE: Delta_Y_H must be read after Delta_Y_L to have the full motion data. Reading it clears the register.
NOTES: PixArt RECOMMENDS that registers 0x02, 0x03, 0x04,0x05 and 0x06 to be sequentially
25
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PixArt Imaging Inc.
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PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
SQUAL
Access: Read Only
Address: 0x07
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SQ7
SQ6
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Data Type: Upper 8-bits of a 10-bit unsigned integer.
USAGE: The SQUAL (Surface quality) register is a measure of the number of valid features visible by the sensor in the
current frame. Use the following formula to find the total number of valid features.
Number of Features = SQUAL Register Value * 4
The maximum SQUAL register value is 169. Since small changes in the current frame can result in changes in
SQUAL, variations in SQUAL when looking at a surface are expected. The graph below shows 800 sequentially
acquired SQUAL values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero if there
is no surface below the sensor. SQUAL remains fairly high throughout the Z-height range which allows illumination of most pixels in the sensor.
SQUAL Values (White Paper)
At Z = 2.4mm, [email protected]" diameter, Speed = 6ips
200
SQUAL (Count)
150
100
50
0
1
51 101 151 201 251 301 351 401 451 501 551 601 651 701 751
Count
Figure 24. SQUAL Values at 1600cpi (White Paper)
Mean SQUAL Vs. Z (White Paper)
1600cpi, [email protected]" diameter, Speed = 6ips
140
Avg-3sigma
Avg
Avg+3sigma
SQUAL (Count)
120
100
80
60
40
20
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
Distance from Lens Reference Plane to Navigation Surface (mm)
3.4
Figure 25. Mean SQUAL vs. Z (White Paper)
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ADNS-9500 Laser Gaming Sensor
Pixel_Sum
Access: Read Only
Address: 0x08
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
AP7
AP6
AP5
AP4
AP3
AP2
AP1
AP0
Data Type: High 8-bits of an unsigned 17-bit integer.
USAGE: This register is used to find the average pixel value. It reports the upper byte of a 17-bit counter which sums
all 900 pixels in the current frame. It may be described as the full sum divided by 512. To find the average pixel
value, follows the formula below.
Average Pixel = Register Value * 512/900  Register Value/1.76
The maximum register value is 223 (127 * 900/512 truncated to an integer). The minimum register value is 0. The
pixel sum value can change every frame.
Maximum_Pixel
Access: Read Only
Address: 0x09
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
Data Type: Seven bit number.
USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value
can be adjusted every frame.
Minimum_Pixel
Access: Read Only
Address: 0x0A
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
MinP7
MinP6
MinP5
MinP4
MinP3
MinP2
MinP1
MinP0
Data Type: Seven bit number.
USAGE: Minimum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value can
be adjusted every frame.
Shutter_Lower
Access: Read Only
Address: 0x0B
Reset Value: 0x20
Bit
7
6
5
4
3
2
1
0
Field
S7
S6
S5
S4
S3
S2
S1
S0
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ADNS-9500 Laser Gaming Sensor
Shutter_Upper
Access: Read Only
Address: 0x0C
Reset Value: 0x4e
Bit
7
6
5
4
3
2
1
0
Field
S15
S14
S13
S12
S11
S10
S9
S8
Data Type: 16-bit unsigned number.
USAGE: Units are clock cycles of internal oscillator (nominally 47MHz). Read Shutter_Upper first, then Shutter_Lower.
They should be read consecutively. The shutter is adjusted to keep the average pixel values within normal
operating ranges. The shutter value is checked and automatically adjusted to a new value if needed on every
frame when operating in default mode. The shutter value can be set manually by disabling the AGC using the
Configuration_II register and writing to the Shutter_Maximum_Bound registers. Because the automatic frame
rate feature is related to shutter value it may also be appropriate to enable the fixed frame rate mode using
the Configuration_II register. The maximum value of the shutter is dependent upon the setting in the Shutter_
Maximum_Bound registers.
Shown below is a graph of 800 sequentially acquired shutter values, while the sensor was moved slowly over
white paper.
Shutter Values (White Paper
At Z = 2.4mm, [email protected]" diameter, Speed = 6ips)
120
Shutter Value
100
80
60
40
20
0
1
51 101 151 201 251 301 351 401 451 501 551 601 651 701 751
Count
Figure 26. Shutter Values at 5670cpi (White Paper)
Mean Shutter vs Z (White Paper)
1600cpi, [email protected]" diameter, Speed = 6ips
300
Avg-3sigma
Avg
Avg+3sigma
Shutter Value
250
200
150
100
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
Distance from Lens Reference Plane to Navigation Surface, Z (mm)
3.4
Figure 27. Mean Shutter vs. Z (White Paper)
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ADNS-9500 Laser Gaming Sensor
Frame_Period_Lower
Access: Read Only
Address: 0x0D
Reset Value: 0xc0
Bit
7
6
5
4
3
2
1
0
Field
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
Frame_Period_Upper
Access: Read Only
Address: 0x0E
Reset Value: 0x5d
Bit
7
6
5
4
3
2
1
0
Field
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
Data Type: 16-bit unsigned integer.
USAGE: To read from the registers, read Frame_Period_Upper first followed by Frame_Period_Lower. If the Frame_Period_
Upper register greater the zero, these registers provide the Run mode frame rate period. Read these registers to
determine the run mode frame period, or indirectly the run mode frame rate. Units are clock cycles of the internal
oscillator (nominally 47MHz). The formula is:
Run Mode's Frame Rate = Clock Frequency/Register Value
If the Frame_Period_Upper register is zero, these register provide the Rest mode frame rate period. Read these
register to determine the rest mode frame period, or indirectly the rest mode frame rate. Units are clock cycles of
the internal oscillator (nominally 100Hz). The formula is:
Rest Mode Frame Rate = 1 / [Register Value +1]
To set the frame rate manually, disable automatic frame rate mode via the Configuration_II register and write the
desired count value to the Frame_Period_Maximum_Bound registers.
Configuration_I
Access: R/W
Address: 0x0F
Reset Value: 0x12
Bit
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
RES5
RES4
RES3
RES2
RES1
RES0
Data Type: Bit Field.
USAGE: This register sets the resolution on XY axes or X axis only. The approximate resolution value for each register
setting can be calculated using the following formula. Each bit change is ~90cpi. The maximum write value is
0x38, which the resolution setting is approximately 5670cpi.
Resolution value (counts per inch, cpi) ≈ RES [5:0] x 90
For example:
Configuration_I
Register Value
Approximate
Resolution (cpi)
Description
0x01
90
Minimum
0x12
1620
Default
0x24
3240
0x38
5040
Maximum
Note: Rpt_Mod bit in Configuration_II register is used to select CPI reporting mode either XY axes resolution setting in sync or independent setting
for X-axis and Y-axis respectively. Refer to Configuration_V register for Y-axis resolution setting.
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Configuration_II
Access: R/W
Address: 0x10
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
F_Rest1
F_Rest0
Rest_En
NAGC
Fixed_FR
Rpt_Mod
0
0
Data Type: Bit Field.
USAGE: This register is used to change configuration of sensor.
When the sensor is put into Force Rest function via F_Rest[1:0], the operation mode of sensor will change from
current mode to the next desired Rest mode and stay at the desired Rest mode until the Force Rest mode is
released. Once Force Rest mode is released, the sensor will resume to normal operation from the desired Rest
mode and auto downshift to the next level of Rest modes if no motion or recover to Run mode if motion is
detected.
For example:
Current mode
Next desired
mode
Force Rest mode
action
Run
Rest1
Force Rest1
F_Rest[1:0] = 01
Resume to normal operation from REST1, auto downshift to Rest2,
then Rest3 in sequence if no motion or back to Run mode if motion
detected.
Run
Rest2
Force Rest2
F_Rest[1:0] = 10
Resume to normal operation from REST2, auto downshift to Rest3 if
no motion or back to Run mode if motion detected.
Run
Rest3
Force Rest3
F_Rest[1:0] = 11
Resume to normal operation from REST3, stay in Rest3 if no motion
or back to Run mode if motion detected.
After Force Rest mode is released (F_Rest[1:0] = 00)
Field Name
Description
F_Rest[1:0]
Puts chip into Rest mode
00 = Normal operation
01 = Force Rest1
10 = Force Rest2
11 = Force Rest3
Rest_En
Enable Rest mode
0 = Normal operation without REST modes
1 = REST modes enabled
NAGC
Disable AGC. Shutter value will be set to the value in the Shutter_Maximum_Bound registers.
0 = no, AGC is active
1 = yes, AGC is disabled
Fixed_FR
Fixed frame rate (disable automatic frame rate control). When this bit is set the frame rate will be
set by the value in the Frame_Period_Maximum_Bound registers.
0 = automatic frame rate
1 = fixed frame rate
Rpt_Mod
Select CPI reporting mode.
0 = XY axes CPI setting in sync
1 = CPI setting independently for X-axis and Y-axis. Configuration_I register sets X-axis resolution,
while Configuration_V register sets Y-axis resolution.
Bit[1:0]
Must be set to 00
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ADNS-9500 Laser Gaming Sensor
Frame_Capture
Access: R/W
Address: 0x12
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
Data Type: Bit Field.
USAGE: Used to capture the next available complete 1 frame of pixel values to be stored to SROM RAM. Writing to
this register will cause any firmware loaded in the SROM to be overwritten and stops navigation. A hardware
reset and SROM download are required to restore normal operation for motion reading. Refer to Frame Capture
section for use details.
SROM_Enable
Access: Write Only
Address: 0x13
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
Data Type: 8 Bit number.
USAGE: Write to this register to start either SROM download or SROM CRC test. See SROM Download section for details
SROM download procedure.
SROM CRC test can be performed to check for the successful of SROM downloading procedure. SROM CRC test
is only valid after SROM downloaded. Navigation is halted and the SPI port should not be used during this SROM
CRC test. PixArt recommends reading the Motion register to determine the laser fault condition before performing the SROM CRC test.
SROM CRC test procedure is as below:
1. Write 0x15 to SROM_Enable register to start SROM CRC test.
2. Wait for at least 10ms.
3. Read the CRC value from Data_Lower and Data_Upper registers.
Run_Downshift
Access: R/W
Address: 0x14
Reset Value: 0x32
Bit
7
6
5
4
3
2
1
0
Field
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
Data Type: 8 Bit number.
USAGE: This register set the Run to Rest 1 downshift time. Default value is 500ms. Use the formula below for calculation.
Run Downshift time (ms) = RD[7:0] x 10
Default = 50 x 10 = 500ms
All the above values are calculated base on system clock, which expected to have 20% tolerance.
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31
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ADNS-9500 Laser Gaming Sensor
Rest1_Rate
Access: R/W
Address: 0x15
Reset Value: 0x01
Bit
7
6
5
4
3
2
1
0
Field
R1R7
R1R6
R1R5
R1R4
R1R3
R1R2
R1R1
R1R0
Data Type: 8 Bit number.
USAGE: This register set the Rest 1 frame rate. Default value is 20ms. Use the formula below for calculation.
Rest1 frame rate = (R1R[7:0] + 1) x 10ms.
Default = (1 + 1) x 10 = 20ms
All the above values are calculated base on 100Hz Hibernate clock, which expected to have 40% tolerance.
Rest1_Downshift
Access: R/W
Address: 0x16
Reset Value: 0x1f
Bit
7
6
5
4
3
2
1
0
Field
R1D7
R1D6
R1D5
R1D4
R1D3
R1D2
R1D1
R1D0
Data Type: 8 Bit number.
USAGE: This register set the Rest 1 to Rest 2 downshift time. Default value is 9920ms. Use the formula below for calculation.
Rest1 Downshift time = R1D[7:0] x 16 x Rest1_Rate.
Default = 31 x 16 x 20 = 9920ms
All the above values are calculated base on 100Hz Hibernate clock, which expected to have 40% tolerance.
Rest2_Rate
Access: R/W
Address: 0x17
Reset Value: 0x09
Bit
7
6
5
4
3
2
1
0
Field
R2R7
R2R6
R2R5
R2R4
R2R3
R2R2
R2R1
R2R0
Data Type: 8 Bit number.
USAGE: This register set the Rest 2 frame rate. Default value is 100ms. Use the formula below for calculation.
Rest2 frame rate = (R2R[7:0] + 1) x 10ms.
Default = (9 + 1) x 10 = 100ms
All the above values are calculated base on 100Hz Hibernate clock, which expected to have 40% tolerance.
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Rest2_Downshift
Access: R/W
Address: 0x18
Reset Value: 0xbc
Bit
7
6
5
4
3
2
1
0
Field
R2D7
R2D6
R2D5
R2D4
R2D3
R2D2
R2D1
R2D0
Data Type: 8 Bit number.
USAGE: This register set the Rest 2 to Rest 3 downshift time. Default value is 10mins. Use the formula below for calculation.
Rest2 Downshift time = R2D[7:0] x 32 x Rest2_Rate.
Default = 188 x 32 x 100 = 601600ms = 10mins
All the above values are calculated base on 100Hz Hibernate clock, which expected to have 40% tolerance.
Rest3_Rate
Access: R/W
Address: 0x19
Reset Value: 0x31
Bit
7
6
5
4
3
2
1
0
Field
R3R7
R3R6
R3R5
R3R4
R3R3
R3R2
R3R1
R3R0
Data Type: 8 Bit number.
USAGE: This register set the Rest 3 frame rate. Default value is 500ms. Use the formula below for calculation.
Rest3 frame rate = (R3R[7:0] + 1) x 10ms.
Default = (49 + 1) x 10 = 500ms
All the above values are calculated base on 100Hz Hibernate clock, which expected to have 40% tolerance.
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33
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PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Frame_Period_Max_Bound_Lower
Access: R/W
Address: 0x1A
Reset Value: 0xc0
Bit
7
6
5
4
3
2
1
0
Field
FBM7
FBM6
FBM5
FBM4
FBM3
FBM2
FBM1
FBM0
Frame_Period_Max_Bound_Upper
Access: R/W
Address: 0x1B
Reset Value: 0x5d
Bit
7
6
5
4
3
2
1
0
Field
FBM15
FBM14
FBM13
FBM12
FBM11
FBM10
FBM9
FBM8
Data Type: 16-bit unsigned integer.
USAGE: This value sets the maximum frame period (the MINIMUM frame rate) which may be selected by the automatic
frame rate control, or sets the actual frame period when operating in manual mode. To read from the registers,
read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper. Units are clock
cycles of the internal oscillator (nominally 47MHz). The formula is:
Frame Rate (Frames/second, fps) = Clock Frequency / Register Value
To set the frame rate manually, disable automatic frame rate mode via the Configuration_II register and write
the desired count value to these registers. Writing to the Frame_Period_Max_Bound_Upper and Lower registers
also activates any new values in the following registers:
 Frame_Period_Max_Bound_Upper and Lower
 Frame_Period_Min_Bound_Upper and Lower
 Shutter_Max_Bound_Upper and Lower
Any data written to these registers will be saved but will not take effect until the write to the Frame_Period_
Max_Bound_Upper and Lower is complete. After writing to this register, two complete frame times are required
to implement the new settings. Writing to any of the above registers before the implementation is complete
may put the chip into an undefined state requiring a reset.
The three bound registers must also follow this rule when set to non-default values. There is no protection
against illegal register settings, which can impact the navigation.
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
The following table lists some Frame Period example values with a 47MHz clock.
Frame Period
Frame_Period Register Value
Frame Rate
Decimal
Hex
Upper
Lower
1,880
25,000
61a8
61
a8
1,958
24,000
5dc0
5d
c0
7,200
6,528
1980
19
80
11,750
4,000
0fa0
0f
a0
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PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Frame_Period_Min_Bound_Lower
Access: R/W
Address: 0x1C
Reset Value: 0xa0
Bit
7
6
5
4
3
2
1
0
Field
FBm7
FBm6
FBm5
FBm4
FBm3
FBm2
FBm1
FBm0
Frame_Period_Min_Bound_Upper
Access: R/W
Address: 0x1D
Reset Value: 0x0f
Bit
7
6
5
4
3
2
1
0
Field
FBm15
FBm14
FBm13
FBm12
FBm11
FBm10
FBm9
FBm8
Data Type: 16-bit unsigned integer.
USAGE: This value sets the minimum frame period (the MAXIMUM frame rate) which may be selected by the automatic
frame rate control. Units are clock cycles of the internal oscillator (nominally 47MHz). The minimum allowed
write value is 0fa0, the maximum is 61a8. The Frame Rate formula is
Frame Rate (Frames/second, fps) = Clock Rate / Register Value
To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed
by Upper, then write anything to the Frame_Period_Max_Bound Lower and Upper registers to activate the new
setting. A good practice is to read the content of the Frame_Period_Max_Bound registers and write it back.
Reading this register will return the most recent value that was written to it. However, the value will take effect
only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_
Max_Bound_Upper, wait at least two frame times before writing to Frame_Period_Min_Bound_Upper or Lower
again. Refer to Frame_Period_Max_Bound register USAGE for details.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
35
PixArt Imaging Inc.
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PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Shutter_Max_Bound_Lower
Access: R/W
Address: 0x1E
Reset Value: 0x20
Bit
7
6
5
4
3
2
1
0
Field
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
Shutter_Max_Bound_Upper
Access: R/W
Address: 0x1F
Reset Value: 0x4e
Bit
7
6
5
4
3
2
1
0
Field
SB15
SB14
SB13
SB12
SB11
SB10
SB9
SB8
Data Type: 16-bit unsigned integer.
USAGE: This value sets the maximum allowable shutter value when operating in automatic mode. Units are clock cycles
of the internal oscillator (nominally 47MHz). Since the automatic frame rate function is based on shutter value,
the value in these registers can limit the range of the frame rate control.
To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed
by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers to activate the new
setting. A good practice is to read the content of the Frame_Period_Max_Bound registers and write it back. To
set the shutter manually, disable the AGC via the Configuration_I register and write the desired value to these
registers.
Reading this register will return the most recent value that was written to it. However, the value will take effect
only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_
Max_Bound_Upper, wait at least two frame times before writing to Shutter_Max_Bound_Upper or Lower
again.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
36
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PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
LASER_CTRL0
Access: R/W
Address: 0x20
Reset Value: 0x81
Bit
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
Reserved
Reserved
CW2
CW1
CW0
Force_
Disabled
Data Type: Bit field
USAGE: This register is used to control the laser drive mode.
Field Name
Description
CW[2:0]
Laser drive mode
- Write 010b to bits [3,2,1] to set the laser to continuous ON (CW) mode.
- Write 000b to exit laser continuous ON mode, all other values are not recommended.
Reading the Motion register (0x02) will reset the value to 000b and exit laser continuous ON mode.
Force_Disabled
LASER force disabled
0 = LASER_NEN normal
1 = LASER_NEN force disabled
Observation
Access: R/W
Address: 0x24
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
OB7
OB6
OB5
OB4
OB3
OB2
OB1
OB0
Data Type: Bit field
USAGE: The user must clear the register by writing 0x00, wait for one frame, and read the register. The active processes
will have set their corresponding bit. This register may be used as part of a recovery scheme to detect a problem
caused by EFT/B or ESD.
Field Name
Description
OB6
0 = chip is not running SROM code
1 = chip is running SROM code
OB[5:0]
Set once per frame
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PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Data_Out_Lower
Access: Read Only
Address: 0x25
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Data_Out_Upper
Access: Read Only
Address: 0x26
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
DO15
DO14
DO13
DO12
DO11
DO10
DO9
DO8
Data Type: 16-bit word.
USAGE: Data in these registers come from the SROM CRC test. The data can be read out in either order. The SROM CRC
test is initiated by writing 0x15 to SROM_Enable register.
CRC Result
Data_Out_Upper
Data_Out_Lower
SROM CRC test
BE
EF
SROM_ID
Access: Read Only
Address: 0x2A
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
Data Type: 8-bit unsigned integer.
USAGE: Contains the revision of the downloaded Shadow ROM (SROM) firmware. If the firmware has been successfully downloaded and the chip is operating out of SROM, this register will contain the SROM firmware revision;
otherwise it will contain 0x00.
Lift_Detection_Thr
Access: R/W
Address: 0x2E
Reset Value: 0x10
Bit
7
6
5
4
3
2
1
0
Field
Reserve
Reserve
Reserve
LD_Thr4
LD_Thr3
LD_Thr2
LD_Thr1
LD_Thr0
Data Type: 8-bit unsigned integer.
USAGE: To configure the lift detection from the nominal Z-height of 2.4mm of navigation system when ADNS-9500
sensor is coupled with ADNS-6190-002 lens. Higher value will result in higher lift detection. Different surfaces
will have different lift detection values with same setting due to different surface characteristic.
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38
PixArt Imaging Inc.
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PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Configuration_V
Access: R/W
Address: 0x2F
Reset Value: 0x12
Bit
7
6
5
4
3
2
1
0
Field
ResY7
ResY6
ResY5
ResY4
ResY3
ResY2
ResY1
ResY0
Data Type: Bit field.
USAGE: This register allows the user to change the Y-axis resolution when the sensor is configured to have indepedent
X-axis and Y-axis resolution reporting mode via Rpt_Mod bit = 1 in Configuration_II register. The setting in this
register will be inactive if Rpt_Mod bit = 0. The approximate resolution value for each register setting can be calculated using the following formula. Each bit change is~90cpi. The minimum write value is 0x01 and maximum
is 0x37.
Resolution value (counts per inch, cpi) = RES [7:0] x 90
Configuration_IV
Access: R/W
Address: 0x39
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SROM_Size
Reserved
Data Type: Bit field.
USAGE: The correct SROM file size must be selected before loading the SROM to sensor. The current SROM is 3K Bytes
size.
Field Name
Description
SROM_Size
= 0: 1.5K SROM download
= 1: 3K SROM download
Power_Up_Reset
Access: Write Only
Address: 0x3A
Reset Value: 0xNA
Bit
7
6
5
4
3
2
1
0
Field
PUR7
PUR6
PUR5
PUR4
PUR3
PUR2
PUR1
PUR0
Data Type: 8-Bit integer.
USAGE: Write 0x5a to this register to reset the chip. All settings will revert to default values. Reset is required after
recovering from shutdown mode and restore normal operation after Frame Capture.
Shutdown
Access: Write Only
Address: 0x3B
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
OB7
OB6
OB5
OB4
OB3
OB2
OB1
OB0
Data Type: 8-Bit integer.
USAGE: Write 0xb6 to set the chip to shutdown mode, use POWER_UP_RESET register to power up the chip. Refer to
Shutdown section for more details.
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39
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PixArt Imaging Inc.
ADNS-9500 Laser Gaming Sensor
Inverse_Product_ID
Access: Read Only
Address: 0x3F
Reset Value: 0xcc
Bit
7
6
5
4
3
2
1
0
Field
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0
Data Type: 8-Bit unsigned integer.
USAGE: This value is the inverse of the Product_ID, located at the inverse address. It is used to test the SPI port
hardware.
Motion_Burst
Access: Read Only
Address: 0x50
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
Data Type: 8-Bit unsigned integer.
USAGE: The Motion_Burst register is used for high-speed access to the Motion, Observation, Delta_X_L, Delta_X_H,
Delta_Y_L, Delta_Y_H, SQUAL, Pixel_Sum, Maximum_Pixel, Minimum_Pixel, Shutter_Upper, Shutter_Lower,
Frame_Period_Upper and Frame_Period_Lower registers. See Burst Mode-Motion Read section for use details.
Write any value to this register will clear all motion burst data.
SROM_Load_Burst
Access: Write Only
Address: 0x62
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
SL7
SL6
SL5
SL4
SL3
SL2
SL1
SL0
USAGE: The SROM_Load_Burst register is used for high-speed programming SROM from an external PROM or microcontroller. See SROM Download section for use details.
Pixel_Burst
Access: Read Only
Address: 0x64
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Data Type: 8-Bit unsigned integer.
USAGE: The Pixel_Burst register is used for high-speed access to all the pixel values for one complete frame capture,
without writing to the register address to obtain each pixel data. The data pointer is automatically incremented
after each read so all 900 pixel values may be obtained by reading this register 900 times. See Frame Capture
section for use details.
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PixArt Imaging Inc.
E-mail: [email protected]