TI SMJ320C25-50

 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
– 68-Pin Leaded Ceramic Chip Carrier (FJ
Suffix)
– 68-Pin Ceramic Grid Array (GB Suffix)
– 68-Pin Leadless Ceramic Chip Carrier
(FD Suffix)
VSS
D7
D6
D5
D4
D3
D2
D1
D0
SYNC
INT0
INT1
INT2
VCC
DR
FSR
A0
CLKR
CLKX
V CC
V CC
68-Pin FJ and FD Packages
(Top View)
READY
D
D
D
D
D
D Single 5-V Supply
D On-Chip Clock Generator
D Packaging:
D8
D9
D10
D11
D12
D13
D14
D15
D
D
– –55°C to 125°C
100-ns or 80-ns Instruction Cycle Times
544 Words of Programmable On-Chip Data
RAM
4K Words of On-Chip Program ROM
128K Words of Data/Program Space
16 Input and 16 Output Channels
16-Bit Parallel Interface
Directly Accessible External Data Memory
Space
– Global Data Memory Interface
16-Bit Instruction and Data Words
16 × 16-Bit Multiplier With a 32-Bit Product
32-Bit ALU and Accumulator
Single-Cycle Multiply/Accumulate
Instructions
0 to 16-Bit Scaling Shifter
Bit Manipulation and Logical Instructions
Instruction Set Support for Floating-Point
Operations, Adaptive Filtering, and
Extended-Precision Arithmetic
Block Moves for Data/Program
Management
Repeat Instructions for Efficient Use of
Program Space
Eight Auxiliary Registers and Dedicated
Arithmetic Unit for Indirect Addressing
Serial Port for Direct Code Interface
Synchronization Input for Synchronous
Multiprocessor Configurations
Wait States for Communication to
Slow-Off-Chip Memories/Peripherals
On-Chip Timer for Control Operations
Three External Maskable User Interrupts
Input Pin Polled by Software Branch
Instruction
1.6-µm CMOS Technology
Programmable Output Pin for Signaling
External Devices
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
10
59
11
58
12
57
13
56
14
55
15
54
16
53
17
52
18
51
19
50
20
49
21
48
22
47
23
46
24
45
25
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
IACK
MSC
CLKOUT1
CLKOUT2
XF
HOLDA
DX
FSX
X2 CLKIN
X1
BR
STRB
R/W
PS
IS
DS
VSS
V SS
A1
A2
A3
A4
A5
A6
A7
V CC
A8
A9
A10
A11
A12
A13
A14
A15
D Military Temperature Range
68-Pin GB Package
(Top View)
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
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POST OFFICE BOX 1443
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• HOUSTON, TEXAS 77251–1443
1
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
description
This data sheet provides design documentation for the SMJ320C25 and the SMJ320C25-50 digital signal
processor (DSP) devices in the SMJ320 family of VLSI digital signal processors and peripherals. The SMJ320
family supports a wide range of digital signal processing applications such as tactical communications,
guidance, military modems, speech processing, spectrum analysis, audio processing, digital filtering,
high-speed control, graphics, and other computation-intensive applications.
Differences between the SMJ320C25 and the SMJ320C25-50 are specifically identified, as in the following
paragraph and in the parameter tables on pages 18 through 24 of this data sheet. When not specifically
differentiated, the term SMJ320C25 is used to describe both devices.
The SMJ320C25 has a 100-ns instruction cycle time. The SMJ320C25-50 has an 80-ns instruction cycle time.
With these fast instruction cycle times and their innovative memory configurations, these devices perform
operations necessary for many real-time digital signal processing algorithms. Since most instructions require
only one cycle, the SMJ320C25 is capable of executing 12.5 million instructions per second. On-chip data RAM
of 544 16-bit words, on-chip program ROM of 4K words, direct addressing of up to 64K words of external data
memory space and 64K words of external program memory space, and multiprocessor interface features for
sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the
instruction set.
Table 1. PGA/CLCC/LCCC Pin Assignments
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
A0
K1/26
A12
K8/40
D2
E1/16
D14
A5/3
INT2
H1/22
VCC
H2/23
A1
K2/28
A13
L9/41
D3
D2/15
D15
B6/2
IS
J11/46
VCC
L6/35
A2
L3/29
A14
K9/42
D4
D1/14
DR
J1/24
MP/MC
A6/1
VSS
B1/10
A3
K3/30
A15
L10/43
D5
C2/13
DS
K10/45
MSC
C10/59
VSS
K11/44
A4
L4/31
BI0
B7/68
D6
C1/12
DX
E11/54
PS
J10/47
VSS
L2/27
A5
K4/32
BR
G11/50
D7
B2/11
FSR
J2/25
READY
B8/66
XF
D11/56
A6
L5/33
CLKOUT1
C11/58
D8
A2/9
FSX
F10/53
RS
A8/65
X1
G10/51
A7
K5/34
CLKOUT2
D10/57
D9
B3/8
HOLD
A7/67
R/W
H11/48
X2/CLKIN
F11/52
A8
K6/36
CLKR
B9/64
D10
A3/7
HOLDA
E10/55
STRB
H10/49
A9
L7/37
CLKX
A9/63
D11
B4/6
IACK
B11/60
SYNC
F2/19
A10
K7/38
D0
F1/18
D12
A4/5
INT0
G1/20
VCC
A10/61
A11
L8/39
D1
E2/17
D13
85/4
INT1
G2/21
VCC
B10/62
SMJ320 is a trademark of Texas Instruments Incorporated.
2
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Terminal Functions
SIGNALS
I/O/Z†
DEFINITION
VCC
VSS
I
5-V supply pins
I
Ground pins
X1
0
Output from internal oscillator for crystal
X2/CLKIN
I
Input to internal oscillator from crystal or external clock
CLKOUT1
0
Master clock output (crystal or CLKIN frequency/4)
CLKOUT2
0
A second clock output signal
D15–D0
I/O/Z
16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/0 spaces.
A15–A0
O/Z
16-bit address bus A15 (MSB) through A0 (LSB)
PS,DS,IS
O/Z
Program, data, and I/O space select signals
R/W
O/Z
Read / write signal
STRB
O/Z
Strobe signal
RS
I
Reset input
INT2–INT0
I
External user interrupt inputs
MP/MC
I
Microprocessor/microcomputer mode select pin
MSC
0
Microstate complete signal
IACK
0
Interrupt acknowledge signal
READY
I
Data ready input. Asserted by external logic when using slower devices to indicate that the current bus
transaction is complete.
BR
0
Bus request signal. Asserted when the SMJ320C25 requires access to an external global data memory
space.
XF
0
External flag output (latched software-programmable signal)
HOLD
1
Hold input. When asserted, SMJ320C25 goes into an idle mode and places the data, address, and
control lines in the high-impedance state.
HOLDA
0
Hold acknowledge signal
SYNC
I
Synchronization input
BIO
I
Branch control input. Polled by BIOZ instruction
DR
I
Serial data receive input
CLKR
I
Clock for receive input for serial port
I
Frame synchronization pulse for receive input
FSR
DX
CLKX
FSX
O/Z
I
Serial data transmit output
Clock for transmit output for serial port
I/O/Z
Frame synchronization pulse for transmit. Configurable as either an input or an output.
† I/O/Z denotes input/output/high-impedance state.
POST OFFICE BOX 1443
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3
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
block diagram
SYNC
IS
DS
PS
X1
X2/CLKIN
CLKOUT1
CLKOUT2
Program Bus
R/W
STRB
READY
BR
XF
HOLD
HOLDA
MSC
BIO
RS
IACK
16
16
16
16
PFC(16)
QIR(16)
IR(16)
16
STO(16)
Controller
MUX
ST1(16)
16
16
3
A15-A0
16
Stack
16
16
RSR(16)
XSR(16)
16
16
16
MUX
D15-D0
DRR(16)
16
Instruction
16
DR
CLKR
FSR
DX
CLKX
FSX
16
(8 x 16)
Program
ROM/
EPROM
(4096 × 16)
MUX
16
16
Address
16
MP/MC
IFR(6)
PC(16)
MCS(16)
16
INT(2-0)
RPTC(8)
16
16
DXR(16)
16
TIM(16)
16
PRD(16)
6
IMR(6)
8
GREG(8)
16
16
Program Bus
Data Bus
16
16
16
16
AR0(16)
AR2(16)
ARP(3)
MUX
DP(9)
Shifter(0-16)
9
AR4(16)
16
Multiplier
AR3(16)
3
16
16
TR(16)
7 LSB
From IR
AR1(16)
3
16
9
3
AR5(16)
PR(32)
AR6(16)
32
AR7(16)
32
16
ARB(3)
Shifter(-6, 0, 1, 4)
16
3
16
MUX
ARAU(16)
32
MUX
16
16
MUX
32
MUX
16
16
32
ALU(32)
32
DATA/PROG
RAM (256 × 16)
Block B0
Block B2
(32 × 16)
Data RAM
Block B1
(256 × 16)
C
32
16
MUX
16
Shifters (0-7)†
16
16
ACCL(16)
ACCH(16)
16
Data Bus
LEGEND:
ACCH =
ACCL =
ALU
=
ARAU =
ARB
=
ARP
=
DP
=
DRR
=
DXR
=
4
Accumulator high
Accumulator low
Arithmetic logic unit
Auxiliary register arithmetic unit
Auxiliary register pointer buffer
Auxiliary register pointer
Data memory page pointer
Serial port data receive register
Serial port data transmit register
IFR
IMR
IR
MCS
QIR
PR
PRD
TIM
TR
=
=
=
=
=
=
=
=
=
Interrupt flag register
Interrupt mask register
Instruction register
Microcall stack
Queue instruction register
Product register
Period register for timer
Timer
Temporary register
POST OFFICE BOX 1443
PC
PFC
RPTC
GREG
RSR
XSR
AR0-AR7
ST0, ST1
C
• HOUSTON, TEXAS 77251–1443
=
=
=
=
=
=
=
=
=
Program counter
Prefetch counter
Repeat instruction counter
Global memory allocation register
Serial port receive shift register
Serial port transmit shift register
Auxiliary registers
Status registers
Carry bit
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
architecture
The SMJ320C25 increases performance of DSP algorithms through innovative additions to the SMJ320
architecture. Increased throughput on the SMJ320C25 for many DSP applications is accomplished by means
of single-cycle multiply/accumulate instructions with a data move option, eight auxiliary registers with a
dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.
The architectural design of the SMJ320C25 emphasizes overall speed, communication, and flexibility in
processor configuration. Control signals and instructions provide floating-point support, block-memory
transfers, communication to slower off-chip devices, and multiprocessing implementations.
Two large on-chip RAM blocks, configurable either as separate program and data spaces or as two contiguous
data blocks, provide increased flexibility in system design. Programs of up to 4K words can be masked into the
internal program ROM. The remainder of the 64K-word program memory space is located externally. Large
programs can execute at full speed from this memory space. Programs can also be downloaded from slow
external memory to high-speed on-chip RAM. A total of 64K data memory address space is included to facilitate
implementation of DSP algorithms. The VLSI implementation of the SMJ320C25 incorporates all of these
features as well as many others, such as a hardware timer, serial port, and block data transfer capabilities.
32-bit ALU/accumulator
The SMJ320C25 32-bit arithmetic logic unit (ALU) and accumulator perform a wide range of arithmetic and
logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch
instructions dependent on the status of the ALU or a single bit in a word. These instruction provide the following
capabilities:
D Branch to an address specified by the accumulator
D Normalize fixed-point numbers contained in the accumulator
D Test a specified bit of a word in data memory.
One input to the ALU is always provided from the accumulator, and the other input can be provided from the
product register (PA) of the multiplier or the input scaling shifter which has fetched data from the RAM on the
data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the
accumulator.
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the
output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The
contents of the accumulator remain unchanged.
scaling shifter
The SMJ320C25 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to
the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the
instruction. The LSBs of the output are filled with zeroes, and the MSBs can be either filled with zeroes or
sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status
register ST1.
16 X 16-bit parallel multiplier
The SMJ320C25 has a 16 x 16-bit hardware multiplier, which is capable of computing a signed or unsigned
32-bit product in a single machine cycle. The multiplier has the following two associated registers:
D A 16-bit temporary register (TR) that holds one of the operands for the multiplier, and
D A 32-bit product register (PR) that holds the product.
Incorporated into the SMJ320C25 instruction set are single-cycle multiply/accumulate instruction that allow
both operands to be processed simultaneously. The data for these operations can reside anywhere in internal
or external memory and can be transferred to the multiplier each cycle via the program and data buses.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
16 X 16-bit parallel multiplier (continued)
Four product shift modes are available at the product register (PR) output that are useful when performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
timer
The SMJ320C25 provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM)
register is a down counter that is continuously clocked by CLKOUT1. A timer interrupt (TINT) is generated every
time the timer decrements to zero. The timer is reloaded with the value contained in the period (PRD) register
within the next cycle after it reaches zero so that interrupts can be programmed to occur at regular intervals of
PRD + 1 cycles of CLKOUT1.
memory control
The SMJ320C25 provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks
(B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words
(block B0) are programmable as either data or program memory. A data memory size of 544 words allows the
SMJ320C25 to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while
still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can
be downloaded from external program memory into on-chip RAM and then executed.
When using on-chip program RAM, ROM, or high-speed external program memory, the SMJ320C25 runs at
full speed without wait states. However, the READY line can be used to interface the SMJ320C25 to slower,
less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM
speeds processing while cutting system costs.
The SMJ320C25 provides three separate address states for program memory, data memory, and I/O. The
on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon
the memory configuration. The CNF0 (configure block B0 as data memory) and CNFP (configure block B0 as
program memory) instruction allow dynamic configuration of the memory maps through software. Regardless
of the configuration, the user can still execute from external program memory.
The SMJ320C25 has six registers which are mapped into the data memory space: a serial port data receive
register, serial port data transmit register, timer register, period register, interrupt mask register, and global
memory allocation register.
6
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
memory control (continued)
Program
0(0000h)
Program
0(0000h)
Interrupts
and Reserved
(External)
31(001Fh)
32(0020h )
31(001Fh)
32(0020h )
4015(0FAFh)
4016(0FB0h)
Data
0(0000h)
Interrupts
and Reserved
(On-Chip
ROM/EPROM)
On-Chip
Memory-Mapped
Registers
5(0005h)
6(0006h)
Reserved
On-Chip
ROM/EPROM
Page 0
95(005Fh)
96(0060h )
127(007Fh)
128(0080h)
Reserved
4095(0FFFh)
4096(1000h)
On-Chip
Block B2
Reserved
Pages 1-3
On-Chip
Block B0
Pages 4-5
On-Chip
Block B1
Pages 6 -7
511(01FFh)
512(0200h)
External
767(02FFh)
768(0300h)
External
1023(03FFh)
1024(0400h)
External
65,535(0FFFFh)
65,535(0FFFFh)
65,535(FFFFh)
Pages 8 -511
If MP/MC = 0
(Microcomputer Mode)
If MP/MC = 1
(Microprocessor Mode)
(a) Memory Maps After a CNFD Instruction
Program
0(0000h)
Interrupts
and Reserved
(External)
Program
0(0000h)
31(001Fh)
32(0020h )
31(001Fh)
32(0020h )
4015(0FAFh)
4016(0FB0h)
Data
0(0000h)
Interrupts
and Reserved
(On-Chip
ROM/EPROM)
On-Chip
Memory-Mapped
Registers
5(0005h)
6(0006h)
On-Chip
ROM/EPROM
Reserved
95(005Fh)
96(0060h )
Reserved
4095(0FFFh)
4096(1000h)
Page 0
On-Chip
Block B2
127(007Fh)
128(0080h)
Reserved
Pages 1-3
Does Not
Exist
Pages 4-5
On-Chip
Block B1
Pages 6 -7
511(01FFh)
512(0200h)
External
767(02FFh)
768(0300h)
External
1023(03FFh)
1024(0400h)
65,279(0FEFFh)
65,280(0FF00h)
65,279(0FEFFh)
65,280(0FF00h)
On-Chip
Block B0
65,535(0FFFFh)
External
65,535(0FFFFh)
If MP/MC = 1
(Microprocessor Mode)
Pages 8 -511
On-Chip
Block B0
65,535(0FFFFh)
If MP/MC = 0
(Microcomputer Mode)
(b) Memory Maps After a CNFP Instruction
Figure 1. Memory Maps
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
interrupts and subroutines
The SMJ320C25 has three external maskable user interrupts INT2–INT0, available for external devices that
interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT),
and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest
priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on
two-word boundaries so that branch instruction can be accommodated in those locations if desired.
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction is completed. This mechanism applies both to
instructions that are repeated or become multicycle due to the READY signal.
external interface
The SMJ320C25 supports a wide range of system interfacing requirements. Program, data, and I/O address
spaces provide interface to memory and I/O. thus maximizing system throughout. I/O design is simplified by
having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the
processor’s external address and data buses in the same manner as memory-mapped devices. Interface to
memory and I/O devices of varying speeds is accomplished by using the READY line. When transitions are
made with slower devices, the SMJ320C25 processor waits until the other device completes its function and
signals the processor via the READY line. Then, the SMJ320C25 continues execution.
A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and
other serial systems. The interface signals are compatible with codecs and many other serial devices with a
minimum of external hardware. The serial port can also be used for intercommunication between processors
in multiprocessing applications.
The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive register
(DRR). Both registers operate in either the byte mode or 16-bit word mode, any can be accessed in the same
manner as any other data memory location. Each register has an external clock, a framing synchronization
pulse, and associated shift registers. One method of multiprocessing can be implemented by programming one
device to transmit while the others are in the receive mode.
multiprocessing
The flexibility of the SMJ320C25 allows configurations to satisfy a wide range of system requirements. The
SMJ320C25 can be used as follows:
D
D
D
D
A standalone processor
A multiprocessor with devices in parallel
A slave/host multiprocessor with global memory space
A peripheral processor interfaced via processor-controlled signals to another device.
For multiprocessing applications, the SMJ320C25 has the capability of allocating global data memory space
and communicating with that space via the BR (bus request) and READY control signals. Global memory is data
memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit
memory-mapped GREG (global memory allocation register) specifies part of the SMJ320C25s data memory
as global external memory. The contents of the register determine the size of the global memory space. If the
current instruction addresses an operand within that space, BR is asserted to request control of the bus. The
length of the memory cycle is controlled by the READY line.
The SMJ320C25 supports DMA (direct memory access) to its external program/data memory using the HOLD
and HOLDA signals. Another processor can take complete control of the SMJ320C25s external memory by
asserting HOLD low. This causes the SMJ320C25 to place its address, data, and control lines in a
high-impedance state, and assert HOLDA. Program execution from on-chip memory can proceed concurrently
while the device is in the hold mode.
8
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• HOUSTON, TEXAS 77251–1443
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
instruction set
The SMJ320C25 microprocessor implements a comprehensive instruction set that supports both
numeric-intensive signal processing operations as well as general-purpose applications, such as
multiprocessing and high-speed control.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the
same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary
depending upon whether the next data operand fetch is from internal or external program memory. Highest
throughput is achieved by maintaining data memory on-chip and using either internal or fast external program
memory.
addressing modes
The SMJ320C25 instruction set provides three memory addressing modes: direct, indirect, and immediate
addressing.
Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the
instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data
memory address. Indirect addressing accesses data memory through the eight auxiliary registers. In immediate
addressing, the data is based on a portion of the instruction word(s).
In direct memory addressing, the instruction word contains the lower seven bits of the data memory address.
This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus,
memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words.
Eight auxiliary register (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific
auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 through 7 for AR0–AR7,
respectively.
There are seven types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding
or subtracting the contents of AR0, or single indirect addressing with no increment or decrement and bit-reversal
addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary
register in the same cycle as the original instruction, followed by anew ARP value being loaded.
repeat feature
A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table
read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded
with either a data memory value (RPT instruction) or an immediate value (RPTK instruction) .The value of this
operand is one less than the number of times that the next instruction is executed. Those instructions that are
normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle
instructions.
instruction set summary
Table 1 lists the symbols and abbreviations used in Table 1, the instruction set summary, Table 2 consists
primarily of single-cycle,single-word instructions. Infrequently used branch, I/O, and CALL instructions are
multicycle. The instruction set summary is arranged according to function and alphabetized within each
functional grouping.
POST OFFICE BOX 1443
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9
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
instruction set summary (continued)
Table 1. Instruction Symbols
SYMBOL
B
CM
10
MEANING
4-bit field specifying a bit code
2-bit field specifying compare mode
D
Data memory address field
F0
Format status bit
M
Addressing mode bit
K
Immediate operand field
PA
Port address (PA0–PA15 are predefined assembler symbols equal to 0 through 15, respectively)
PM
2-bit field specifying P register output shift code
R
3-bit operand field specifying auxiliary register
S
4-bit left-shift code
X
3-bit accumulator left-shift field
POST OFFICE BOX 1443
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
MNEMONIC
INSTRUCTION BIT CODE
NO.
WORDS
DESCRIPTION
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
0
0
1
1
1
0
0
0
0
1
1
0
1
1
Add to accumulator with shift
1
0
0
0
0
M
D
Add to accumulator with carry
1
0
1
0
0
0
0
1
1
M
D
ADDH
Add to high accumulator
1
0
1
0
0
1
0
0
0
M
D
ADDK‡
Add to accumulator short immediate
1
1
1
0
0
1
1
0
0
ADDS
Add to low accumulator with sign
extension suppressed
1
0
1
0
0
1
0
0
1
M
D
ADDT
Add to accumulator with shift specified by
T register
1
0
1
0
0
1
0
1
0
M
D
ADLK†
Add to accumulator long immediate with shift
2
1
1
0
1
0
1
0
AND
AND with accumulator
1
0
1
0
0
ANDK†
AND immediate with accumulator with shift
2
1
1
0
1
CMPL†
Complement accumulator
1
1
1
0
0
LAC
Load accumulator with shift
1
0
0
1
0
LACK
Load accumulator immediate short
1
1
1
0
0
1
0
1
0
LACT†
Load accumulator with shift specified by
T register
1
0
1
0
0
0
0
1
0
M
LALK†
Load accumulator long immediate with shift
2
1
1
0
1
0
0
0
0
NEG†
Negate accumulator
1
1
1
0
0
1
1
1
0
0
0
1
0
NORM†
Normalize contents of accumulator
1
1
1
0
0
1
1
1
0
1
OR
OR with accumulator
1
0
1
0
0
1
1
0
1
M
ORK†
OR immediate with accumulator with shift
2
1
1
0
1
ROL‡
Rotate accumulator left
1
1
1
0
0
1
1
1
0
ROR‡
Rotate accumulator right
1
1
1
0
0
1
1
1
0
SACH
Store high accumulator with shift
1
0
1
1
0
1
SACL
Store low-order accumulator with shift
1
0
1
1
0
0
SBLK†
Subtract from accumulator long immediate
with shift
2
1
1
0
1
SFL†
Shift accumulator left
1
1
1
0
0
1
1
1
SFR†
Shift accumulator right
1
1
1
0
0
1
1
1
SUB
Subtract from accumulator with shift
1
0
0
0
1
SUBB‡
Subtract from accumulator with borrow
1
0
1
0
0
1
1
1
SUBC
Conditional subtract
1
0
1
0
0
0
1
1
SUBH
Subtract from high accumulator
1
0
1
0
0
0
1
SUBK‡
Subtract from accumulator short immediate
1
1
1
0
0
1
SUBS
Subtract from low accumulator with sign
extension suppressed
1
0
1
0
0
0
ABS
Absolute value of accumulator
ADD
ADDC‡
S
S
1
1
1
1
K
0
0
0
0
0
1
0
M
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
1
0
0
0
1
0
0
1
1
S
D
M
S
S
S
D
K
D
D
D
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
0
0
1
1
0
1
0
1
X
M
D
X
M
D
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
S
M
D
1
M
D
1
M
D
0
0
M
D
1
0
1
1
0
1
S
K
M
D
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.
POST OFFICE BOX 1443
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11
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary (continued)
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
MNEMONIC
INSTRUCTION BIT CODE
NO.
WORDS
DESCRIPTION
15
14
13
12
11
10
9
8
7
6
5
4
3
SUBT†
Subtract from accumulator with shift specified by
T register
1
0
1
0
0
0
1
1
0
M
D
XOR
Exclusive-OR with accumulator
1
0
1
0
0
1
1
0
0
M
D
XORK†
Exclusive-OR immediate with accumulator with
shift
2
1
1
0
1
ZAC
Zero accumulator
1
1
1
0
0
1
0
1
ZALH
Zero low accumulator and load high accumulator
1
0
1
0
0
0
0
ZALR‡
Zero low accumulator and load high accumulator
with rounding
1
0
1
1
1
1
ZALS
Zero accumulator and load low accumulator with
sign extension suppressed
1
0
1
0
0
0
2
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
M
D
0
1
1
M
D
0
0
1
M
D
2
1
0
S
AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS
INSTRUCTION BIT CODE
DESCRIPTION
NO.
WORDS
15
14
13
12
11
10
9
8
ADRK‡
Add to auxiliary register short immediate
1
0
1
1
1
1
1
1
0
CMPR†
Compare auxiliary register with auxiliary
register AR0
1
1
1
0
0
1
1
1
0
LAR
Load auxiliary register
1
0
0
1
1
0
LARK
Load auxiliary register short immediate
1
1
1
0
0
0
LARP
Load auxiliary register pointer
1
0
1
0
1
0
1
0
1
1
LDP
Load data memory page pointer
1
0
1
0
1
0
0
1
0
M
LDPK
Load data memory page pointer immediate
1
1
1
0
0
1
0
0
LRLK†
Load auxiliary register long immediate
2
1
1
0
1
0
MAR
Modify auxiliary register
1
0
1
0
1
0
SAR
Store auxiliary register
1
0
1
1
1
0
SBRK‡
Subtract from auxiliary register short immediate
1
0
1
1
1
1
MNEMONIC
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.
12
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• HOUSTON, TEXAS 77251–1443
7
6
5
4
3
K
0
1
0
1
0
M
R
K
1
R
1
1
0
0
0
1
R
D
DP
0
R
0
CM
D
R
1
0
1
0
0
0
0
M
D
M
D
K
0
0
0
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary (continued)
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
MNEMONIC
INSTRUCTION BIT CODE
NO.
WORDS
DESCRIPTION
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
1
0
1
APAC
Add P register to accumulator
1
1
1
0
0
1
1
1
0
0
LPH†
Load high P register
1
0
1
0
1
0
0
1
1
M
D
LT
Load T register
1
0
0
1
1
1
1
0
0
M
D
LTA
Load T register and accumulate previous product
1
0
0
1
1
1
1
0
1
M
D
LTD
Load T register, accumulate previous product,
and move data
1
0
0
1
1
1
1
1
1
M
D
LTP†
Load T register and store P register in
accumulator
1
0
0
1
1
1
1
1
0
M
D
LTS†
Load T register and subtract previous product
1
0
1
0
1
1
0
1
1
M
D
MAC†
Multiply and accumulate
2
0
1
0
1
1
1
0
1
M
D
MACD†
Multiply and accumulate with data move
2
0
1
0
1
1
1
0
0
M
D
MPY
Multiply (with T register, store product in
P register)
1
0
0
1
1
1
0
0
0
M
D
MPYA‡
Multiply and accumulate previous product
1
0
0
1
1
1
0
1
0
M
MPYK
Multiply immediate
1
1
0
1
MPYS‡
Multiply and subtract previous product
1
0
0
1
1
1
0
1
1
M
MPYU‡
Multiply unsigned
1
1
1
0
0
1
1
1
1
M
PAC
Load accumulator with P register
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
0
0
SPAC
Subtract P register from accumulator
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
1
0
SPH‡
Store high P register
1
0
1
1
1
1
1
0
1
M
SPL‡
Store low P register
1
0
1
1
1
1
1
0
0
M
SPM†
Set P register output shift mode
1
1
1
0
0
1
1
1
0
0
SQRA†
Square and accumulate
1
0
0
1
1
1
0
0
1
M
D
SQRS†
Square and subtract previous product
1
0
1
0
1
1
0
1
0
M
D
D
K
D
D
D
D
0
0
0
1
0
PM
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.
POST OFFICE BOX 1443
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13
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary (continued)
BRANCH/CALL INSTRUCTIONS
MNEMONIC
INSTRUCTION BIT CODE
NO.
WORDS
DESCRIPTION
15
14
13
12
11
10
9
8
7
2
1
1
1
1
1
1
1
1
1
Branch to address specified by accumulator
1
1
1
0
0
1
1
1
0
0
Branch on auxiliary register not zero
2
1
1
1
1
1
0
1
1
1
D
Branch if TC bit ≠ 0
2
1
1
1
1
1
0
0
1
1
D
Branch if TC bit = 0
2
1
1
1
1
1
0
0
0
1
D
Branch on carry
2
0
1
0
1
1
1
1
0
1
D
Branch if accumulator ≥ 0
2
1
1
1
1
0
1
0
0
1
D
BGZ
Branch if accumulator > 0
2
1
1
1
1
0
0
0
1
1
D
BIOZ
Branch on I/O status = 0
2
1
1
1
1
1
0
1
0
1
D
BLEZ
Branch if accumulator ≤ 0
2
1
1
1
1
0
0
1
0
1
D
BLZ
Branch if accumulator < 0
2
1
1
1
1
0
0
1
1
1
D
BNC‡
Branch on no carry
2
0
1
0
1
1
1
1
1
1
D
BNV†
Branch if no overflow
2
1
1
1
1
0
1
1
1
1
D
BNZ
Branch if accumulator ≠ 0
2
1
1
1
1
0
1
0
1
1
D
BV
Branch on overflow
2
1
1
1
1
0
0
0
0
1
D
BZ
Branch if accumulator = 0
2
1
1
1
1
0
1
1
0
1
CALA
Call subroutine indirect
1
1
1
0
0
1
1
1
0
0
CALL
Call subroutine
2
1
1
1
1
1
1
1
0
1
RET
Return from subroutine
1
1
1
0
0
1
1
1
0
0
B
Branch unconditionally
BACC†
BANZ
BBNZ†
BBZ†
BC‡
BGEZ
6
5
4
3
2
1
0
1
0
1
1
0
0
D
0
1
0
0
D
0
1
0
0
0
1
0
0
1
1
0
4
3
2
1
0
1
1
FO
D
I/O AND DATA MEMORY OPERATIONS
MNEMONIC
INSTRUCTION BIT CODE
NO.
WORDS
DESCRIPTION
15
14
13
12
11
10
9
8
7
2
1
1
1
0
1
1
0
1
M
D
2
1
1
1
1
1
1
0
0
M
D
Data move in data memory
1
0
1
0
1
0
1
1
0
M
Format serial port registers
1
1
1
0
0
1
1
1
0
0
IN
Input data from port
1
1
0
0
0
PA
M
OUT
Output data to port
1
1
1
1
0
PA
M
RFSM‡
Reset serial port frame synchronization mode
1
1
1
0
0
1
1
1
0
0
0
1
1
D
0 1
1
0
RTXM†
Reset serial port transmit mode
1
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
RXF†
Reset external flag
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
0
0
SFSM‡
Set serial port frame synchronization mode
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
1
1
STXM†
Set serial port transmit mode
1
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
1
SXF†
Set external flag
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
0
1
TBLR
Table read
1
0
1
0
1
1
0
0
0
M
D
TBLW
Table write
1
0
1
0
1
1
0
0
1
M
D
BLKD†
Block move from data memory to data memory
BLKP†
Block move from program memory to data
memory
DMOV
FORT†
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
6
5
D
0
0
0
1
D
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary (concluded)
CONTROL INSTRUCTIONS
MNEMONIC
INSTRUCTION BIT CODE
NO.
WORDS
DESCRIPTION
15
14
13
12
11
10
9
8
7
1
1
1
0
0
0
1
1
0
1
0
M
D
1
1
1
M
D
1
1
1
0
0
1
1
1
0
0
0
0
0
Configure block as program memory
Disable interrupt
1
1
1
1
1
0
1
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
EINT
Enable interrupt
IDLE†
1
1
1
0
0
1
1
1
0
0
0
LST
Idle until interrupt
Load status register STO
1
1
1
0
1
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
M
LST1†
Load status register ST1
1
D
0
1
0
1
0
0
0
1
M
D
NOP
POP
No operation
Pop top of stack to low accumulator
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
1
POPD†
Pop top of stack to data memory
PSHD†
1
0
1
1
1
1
0
1
0
M
PUSH
Push data memory value onto stack
1
0
1
0
1
0
1
0
0
M
Push low accumulator onto stack
1
1
1
0
0
1
1
1
0
0
0
0
1
RC‡
Reset carry bit
1
1
1
0
0
1
1
1
0
0
0
1
RHM‡
Reset hold mode
1
1
1
0
0
1
1
1
0
0
0
ROVM
Reset overflow mode
1
1
1
0
0
1
1
1
0
0
0
RPT†
Repeat instruction as specified by data
memory value
1
0
1
0
0
1
0
1
1
M
RPTK†
Repeat instruction as specified by immediate
value
1
1
1
0
0
1
0
1
1
RSXM†
Reset sign-extension mode
1
1
1
0
0
1
1
1
0
0
0
0
0
RTC‡
Reset test/control flag
1
1
1
0
0
1
1
1
0
0
0
1
SC‡
Set carry bit
1
1
1
0
0
1
1
1
0
0
0
1
SHM‡
Set hold mode
1
1
1
0
0
1
1
1
0
0
0
SOVM
Set overflow mode
1
1
1
0
0
1
1
1
0
0
0
SST
Store status register ST0
1
0
1
1
1
1
0
0
0
M
SST1†
Store status register ST1
1
0
1
1
1
1
0
0
1
M
SSXM†
Set sign-extension mode
1
1
1
0
0
1
1
1
0
0
0
0
0
STC‡
Set test/control flag
1
1
1
0
0
1
1
1
0
0
0
1
1
TRAP†
Software interrupt
1
1
1
0
0
1
1
1
0
0
0
0
1
BIT†
Test bit
BITT†
Test bit specified by T register
CNFD†
Configure block as data memory
CNFP†
DINT
B
6
5
4
3
2
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
0
1
1
1
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
0
1
1
1
0
0
1
1
1
1
1
0
D
D
D
K
D
D
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
development systems and software support
Texas Instruments offers concentrated development support and complete documentation for designing an
SMJ320C25-based microprocessor system. When developing an application, tools are provided to evaluate
the performance of the processor, to develop the algorithm implementation, and to fully integrate the design’s
software and hardware modules. When questions arise, additional support can be obtained by calling the
nearest Texas Instruments Regional Technology Center (RTC).
Sophisticated development operations are performed with the SMJ320C25 Macro Assembler/linker, Simulator,
and Emulator (XDS). The macro assembler and linker are used to translate program modules into object code
and link them together. This puts the program modules into a form which can be loaded into the SMJ320C25
Simulator or Emulator. The simulator provides a quick means for initially debugging SMJ320C25 software while
the emulator provides the real-time in-circuit emulation necessary to perform system level debug efficiently.
Table 3 gives a complete list of SMJ320C25 software and hardware development tools.
Table 3. SMJ/SMJ320C25 Software and Hardware Support
MACRO ASSEMBLERS/LINKERS
Host Computer
Operating System
Part Number
DECVAX
VMS
TMDS324210-08
TI/IBM PC
MS/PC-DOS
TMDS3242810-02
SIMULATORS
Host Computer
Operating System
Part Number
DECVAX
VMS
TMDS3242211-08
TI/IBM PC
MS/PC-DOS
TMDS3242811-02
EMULATORS
16
Model
Power Supply
Part Number
XDS/22
Included
TMDS3262221
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
† All voltage values are with respect to VSS.
recommended operating conditions‡
SMJ320C25-50
VCC
VSS
VIH
VIL
IOH
IOL
Supply voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.75
5
5.25
4.5
5
5.5
Supply voltage
High le el inp
High-level
inputt voltage
oltage
SMJ320C25
0
0
READY
3.00
2.35
D15–D0
2.20
2.20
FSX
2.20
2.30
CLKR, CLKX
3.50
3.50
CLKIN
4.00
3.50
All others
3.00
UNIT
V
V
V
3.00
D15–D0, FSX, CLKIN, CLKR, CLKX
0.80
0.80
HOLD
0.70
0.70
All others
0.80
0.70
High-level output current
300
300
mA
Low-level output current
2
2
mA
125
°C
Low-level
Low
level in
input
ut voltage
TC
Operating case temperature
–55
125
–55
‡ TC MAX at maximum rated operating conditions at any point on case TC MIN at initial (time zero) power up
V
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
POST OFFICE BOX 1443
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17
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SMJ320C25,
SMJ320C25-50
MIN
VOH
VOL
High-level output voltage
Low-level output voltage
VCC = MIN, IOH = MAX
VCC = MIN, IOL = MAX
IZ
Three-state current
VCC = MAX
II
Input current
ICC
S ppl current
Supply
c rrent
Ci
Input capacitance
24
VI = VSS to VCC
UNIT
MAX
3
V
0.3
X2/CLKIN
All other pins
TYP§
0.6
V
–20
20
mA
–20
20
–10
10
Normal
A
mA
185
VCC = MAX
MAX, fx = MAX
Idle/R5L5
100
Co
Output capacitance
§ All typical values are at VCC = 5 V, TA = 25°C
mA
15
pF
15
pF
CLOCK CHARACTERISTICS AND TIMING
The SMJ320C25 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency
of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be either fundamental or
overtone mode, and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation of 1 mW,
and be specified at a load capacitance of 20 pF. Note that overtone of crystals require an additional tuned LC
circuit (see the application report, Hardware Interfacing to the TMS320C25).
SMJ320C25-50
PARAMETER
TEST CONDITIONS
MIN
6.7†
fx
Input clock frequency
TA = – 55°C MIN
C1, C2
TC = 125°C MAX
† These values are derived from characterization data and are not tested.
X1
TYP
Crystal
C2
Figure 2. Internal Clock Options
18
POST OFFICE BOX 1443
MAX
50.0
10
X2/CLKIN
C1
SMJ320C25
• HOUSTON, TEXAS 77251–1443
MIN
6.7†
TYP
MAX
40.0
10
UNIT
MHz
pF
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the following table.
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
PARAMETER
tc(C)
td(CIH–C)
Cycle time, CLKOUT1/CLKOUT2
SMJ320C25
MAX
MIN
80
600
100
600
ns
5
28
5
30
(1S
Q–6
Q+3
Q–6
Q+6
ns
Delay time, CLKIN high to CLKOUT1/CLKOUT2/STRB high/low
NOM
MAX
UNIT
MIN
Delay time, CLKOUT1 high to CLKOUT2 low,
td(C1–C2)
tf(C)
tr(C)
Delay time, CLKOUT2 high to CLKOUT1 high, etc.
Q
Fall time, CLKOUT1/CLKOUT2/STRB
5
5
ns
Rise time, CLKOUT1/CLKOUT2/STRB
3
5
ns
tw(CL)
Pulse duration, CLKOUT1/CLKOUT2 low
tw(CH)
Pulse duration, CLKOUT1/CLKOUT2 high
† .This parameter is not production tested
NOTE 1: Q = 1/4tc(C)
2Q – 7
2Q + 5
2Q – 8
2Q
2Q + 8
ns
2Q – 5
2Q + 7
2Q – 8
2Q
2Q + 8
ns
timing requirements over recommended operating conditions (see Note 1 )
SMJ320C25-50
SMJ320C25
MIN
MAX
MIN
MAX
20
150
UNIT
tc(CI)
tw(CIL)
Cycle time, CLKIN
25
150
ns
Pulse duration, CLKIN low, tc(CI) = 25 ns (see Note 2)
8
10
15
ns
tw(CIH)
tsu(S)
Pulse duration, CLKIN high, tc(CI) = 25 ns (see Note 2)
8
10
15
ns
Setup time, SYNC before CLKIN low
4
5
Q–5
ns
Q–4
th(S)
Hold time, SYNC from CLKIN low
4
8
ns
NOTES: 1: Q = 1/4tc(C)
2. Rise and fall times, assuming a 40–60% duty cycle, are incorporated within this specification CLKIN rise and fall times must be less
than 5 ns
Figure 3. Test Load Circuit
POST OFFICE BOX 1443
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
2.0 V
VIH (Min)
1.88 V
0.92 V
VIL (Max)
0.80 V
2.4 V
VOH (Min)
2.2 V
0.8 V
VOL (Max)
0.6 V
0
0
(a) Input
(b) Output
Figure 4. Voltage Reference Levels
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
PARAMETER
td(C1–S) STRB from CLKOUT1 (if STRB is present)
td(C2–S) CLKOUT2 to STRB (if STRB is present)
SMJ320C25
MAX
MIN
TYP
MAX
Q–5
Q+3
Q–6
Q
Q+6
ns
–2
5
–6
0
6
ns
tsu(A)
th(A)
Address setup time before STRB low (see Note 3)
tw(SL)
tw(SH)
STRB low pulse duration (no wait states, see Note 4)
2Q – 5
2Q + 5
2Q – 5
STRB high pulse duration (between consecutive cycles, see Note 4)
2Q – 5
2Q + 5
2Q – 5
Address hold time after STRB high (see Note 3)
tsu(D)W Data write setup time before STRB high (no wait states)
th(D)W Data write hold time from STRB high
ten(D)
tdis(D)
Data bus starts being driven after STRB low (write cycle)
Q – 13
Q – 12
ns
Q–4
Q–8
ns
2Q – 17
2Q – 20
Q–5
0†
Q – 10
0†
Q + 15†
Data bus three-state after STRB high (write cycle)
td(MSC) MSC valid from CLKOUT1
† These values are derived from characterization data and not tested.
UNIT
MIN
–5
10
–10
2Q
2Q + 5
ns
2Q + 5
ns
ns
Q
ns
ns
Q
Q + 15†
ns
0
10
ns
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
MIN
MAX
SMJ320C25
MIN
Access time, read data from address time (read cycle, see Notes 3 and 5)
th(D)R
td(SL–R)
Hold time, data read from STRB high
td(C2H–R)
th(SL–R)
Delay time, READY valid after CLKOUT2 high
Hold time, READY after STRB low (no wait states)
Q–1
Q+3
ns
th(C2H–R)
td(M–R)
Hold time, READY after CLKOUT2 high
Q–1
Q+3
ns
17
23
0
Delay time, READY valid after STRB low (no wait states)
3Q – 35
UNIT
ta(A)
tsu(D)R
Setup time, data read before STRB high
3Q – 31
MAX
Q – 21
Delay time, READY valid after MSC valid
ns
0
Q – 20
2Q – 25
ns
ns
Q – 20
ns
Q – 20
ns
2Q – 25
ns
th(M–R)
Hold time, READY after MSC valid
0
0
ns
NOTES: 1: 0 = 1/4tc(C)
3. A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as ”address”
4. Delays between CLKOUT1 /CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no
wait states.
5. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R + tr(C).
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
RS, INT, BIO, and XF timing
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
PARAMETER
td(RS)
Delay time, CLKOUT1 low to reset state entered
td(IACK) Delay time, CLKOUT1 to IACK valid
td(XF)
Delay time, XF valid before falling edge of STRB
SMJ320C25
MIN
TYP
MAX
22†
MIN
TYP
MAX
22†
–5†
0
7
–8†
0
8
Q – 10
Q – 12
UNIT
ns
ns
ns
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
MIN
tsu(IN)
th(IN)
Setup time, INT/BIO/RS before CLKOUT1 high
tw(IN)
tw(RS)
Pulse duration, INT/BIO low
SMJ320C25
MAX
MIN
25
UNIT
32
ns
0
0
ns
tc(C)
3tc(C)
tc(C)
3tc(C)
ns
Hold time, INT/BIO/RS after CLKOUT1 high
Pulse duration, RS low
MAX
ns
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
PARAMETER
td(C1L-AL)
tdis(AL-A)
MIN
–1
Delay time, HOLDA low after CLKOUT1 low
TYP
Disable time, HOLDA low to address three-state
SMJ320C25
MAX
MIN
11
–1
TYP
10
0
tdis(C1L-A)
Disable time, address three-state after CLKOUT1 low (HOLD
mode, see Note 7 )
td(HH-AH)
ten(A-C1L)
MAX
0
UNIT
ns
ns
20†
20†
ns
Delay time, HOLD high to HOLDA high
19
25
ns
Enable time, address driven before CLKOUT1 low (HOLD mode,
see Note 7 )
8†
8†
ns
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
MIN
MAX
SMJ320C25
UNIT
MIN
UNIT
MAX
td(C2H-H) Delay time, HOLD valid after CLKOUT2 high
Q – 19
Q – 24
ns
† These values are derived from characterization data and not tested.
NOTES: 1. Q = 1/4tc(C)
6. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagram occurs. INT/BIO fall time must be less than 8 ns.
7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as ’”address”.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
serial port timing
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
PARAMETER
MIN
MAX
SMJ320C25
MIN
MAX
UNIT
td(CH-DX)
td(FL-DX)
Delay time, DX valid after CLKX rising edge (see Note 8)
75
80
ns
Delay time, DX valid after FSX falling edge (TXM = 0. see Note 8)
40
45
ns
td(CH-FS)
FSX valid after CLKX rising edge (TXM = 1 )
40
45
ns
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
MIN
SMJ320C25
MAX
MIN
MAX
UNIT
fsx
tc(SCK)
Serial port frequency
1.25
6250
1.25
5000
Serial port clock (CLKX/CLKR) cycle time
160
800 000
200
800 000
tw(SCK1
tw(SCK)
Serial port clock (CLKX/CLKR) low pulse duration (see Note 9)
64
80
ns
Serial port clock (CLKX/CLKR) high pulse duration (see Note 9)
64
80
ns
tsu(FS)
th(FS)
FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)
tsu(DR)
th(DR)
OR setup time before CLKR falling edge
FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)
OR hold time after CLKR falling edge
kHz
ns
5
18
ns
10
20
ns
5
10
ns
10
20
ns
NOTES: 1: Q = 1/4tc(C)
8. The last occurrence of FSX falling and CLKX rising.
9. The duty cycle of the serial port clock must be within 40–60% .Serial port clock (CLKX/CLKR) rise and fall times must be less than
25 ns.
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
TIMING DIAGRAMS
Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.2 V with the
exception of CLKOUT1, CLKOUT2, and STRB timing that are referenced from a falling edge low voltage of
1.1 V and a rising edge low voltage of 2.2 V.
tc(CI)
tf(CI)
tr(CI)
X/2CLKIN
tw(CIH)
th(S)
tsu(S)
tw(CIL)
tsu(S)
SYNC
tc(C)
tw(CL)
td(CIH-C)
td(CIH-C)
CLKOUT1
tw(CH)
tr(C)
td(CIH-C)
tf(C)
STRB
td(CIH-C)
tc(C)
tw(CL)
CLKOUT2
td(C1-C2)
td(C1-C2)
td(C1-C2)
tf(C)
tr(C)
tw(CH)
td(C1-C2)
Figure 5. Clock Timing
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23
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
td(C1-S)
CLKOUT1
td(C1-S)
CLKOUT2
td(C2-S)
td(C2-S)
STRB
tw(SH)
tsu(A)
th(A)
tw(SL)
A15-A0,
BR, PS, DS
or IS
Valid
ta(A)
R/W
td(SL-R)
tsu(D)R
READY
th(SL-R)
D15-D0
th(D)R
Data In
Figure 6. Memory Read Timing
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
CLKOUT2
STRB
th(A)
tsu(A)
A15-A0,
BR, PS, DS
or IS
Valid
R/W
READY
tsu(D)W
D15-D0
th(D)W
Data Out
ten(D)
tdis(D)
Figure 7. Memory Write Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
CLKOUT2
STRB
th(C2H-R)
A15-A0, BR,
PS, DS, R/W or
IS
Valid
td(C2H-R)
th(C2H-R)
td(C2H-R)
READY
td(M-R)
D15-D0
(For Read
Operation)
th(M-R)
th(M-R)
td(M-R)
Data In
D15-D0
(For Write
Operation)
Data Out
td(MSC)
td(MSC)
MSC
Figure 8. One Wait-State Memory Access Timing
26
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
tsu(IN)
td(RS)
tsu(IN)
th(IN)
RS
tw(RS)
A15-A0
Valid
Fetch
Location 0
D15-D0
Valid
PS
Begin
Program
Execution
STRB
Control
Signals†
IACK
Serial Port
Control‡
† Control signals are DS, IS, R/W, and XF.
‡ Serial port controls are DX and FSX.
Figure 9. Reset Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
STRB
tsu(IN)
th(IN)
tw(IN)
INT2-INT0
td(IACK)
tf(IN)
A15-A0
FETCH N
FETCH N + 1
FETCH I
FETCH I + 1
td(IACK)
IACK
Figure 10. Interrupt Timing
CLKOUT1
STRB
FETCH Branch Address
FETCH
BIOZ
A15-A0
PC = N
PC = N + 1
PC = N + 2
or Branch Address
tsu(IN)
th(IN)
BIO
Valid
Figure 11. BIO Timing
28
FETCH Next Instruction
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
STRB
td(XF)
A15-A0
FETCH
SXF/RXF
Valid
Valid
Valid
PC = N
PC = N + 1
PC = N + 2
PC = N + 3
XF
Valid
Figure 12. External Flag Timing
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29
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
CLKOUT2
STRB
td(C2H-H)†
HOLD
A15-A0
N
N+1
PS, DS,
or IS
Valid
Valid
N+2
R/W
tdis(C1L-A)
In
D15-D0
In
tdis(AL-A)
HOLDA
td(C1L-AL)
FETCH
N
N+1
–
–
N–2
N –1
N
–
EXECUTE
† HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown occurs;
otherwise, a delay of one CLKOUT2 cycle occurs.
Figure 13. HOLD Timing (part A)
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
CLKOUT2
ten(A-C1L)
STRB
td(C2H-H)†
HOLD
Valid
PS, DS,
or IS
R/W
In
D15-D0
td(HH-AH)
HOLDA
A15-A0
FETCH
N+2
–
–
–
N+2
N+2
–
–
–
N+1
EXECUTE
† HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown occurs;
otherwise, a delay of one CLKOUT2 cycle occurs.
Figure 14. HOLD Timing (part B)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
31
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
tc(SCK)
tr(SCK)
tw(SCK)
CLKR
th(DR)
tf(SCK)
th(FS)
tw(SCK)
FSR
tsu(FS)
tsu(DR)
DR
Figure 15. Serial Port Receive Timing
tc(SCK)
tr(SCK)
tw(SCK)
CLKX
td(CH-DX)
tf(SCK)
tw(SCK)
th(FS)
FSX
(Input,
TXM = 0)
tsu(FS)
td(CH-DX)
td(FL-DX)
N=1
DX
td(CH-FS)
td(CH-FS)
FSX
(Output,
TXM = 1)
Figure 16. Serial Port Transmit Timing
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N = 8,16
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
MECHANICAL DATA
FD (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
44 TERMINAL SHOWN
NO. OF
TERMINALS
**
18
28
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.064
(1,63)
0.080
(2,03)
28
0.442
(11,23)
0.458
(11,63)
0.064
(1,63)
0.080
(2,03)
44
0.640
(16,26)
0.660
(16,76)
0.069
(1,75)
0.120
(3,05)
52
0.739
(18,78)
0.761
(19,33)
0.082
(2,08)
0.120
(3,05)
68
0.938
(28,83)
0.962
(24,43)
0.082
(2,08)
0.120
(3,05)
84
1.135
1.165
(28,83) (29,59)
0.082
(2,08)
0.120
(3,05)
17
29
A SQ
39
7
40
1
B
A
6
0.095 (2,41)
0.075 (1,91)
0.025 (0,64)
45°
0.015 (0,38)
B
0.025 0.050
(0,64 1,27)
35 Places
0.015 (0,38)
0.003 (0,08) R
0.025 (0,64)
TYP
0.028 (0,71)
TYP
0.022 (0,56)
0.015 (0,38) TYP
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
45° 3 Places
0.035 (0,89)
0.050 (1,27)
4040136/B 03/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
33
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
FJ (S-CQCC-J**)
J-LEADED CERAMIC CHIP CARRIER
44 PINS SHOWN
A
B
6
1
Index Mark
(Optional)
40
7
39
0.043 (1,09)
0.033 (0,84)
C
0.025 (0,64)
0.015 (0,38)
29
17
0.015 (0,38) MIN
0.058 (1,47)
0.042 (1,07)
18
E
0.025 (0,64)
RAD
0.036 (0,89)
28
0.011 (0,28)
0.007 (0,18)
29
17
0.085 (2,16)
0.065 (1,65)
D
0.050 (1,27)
0.030 (0,76)
× 45°
3 Places
0.050 (1,27)
6
DIM
PINS **
0.020 (0,51)
0.010 (0,25)
39
7
1
40
0.145 (3,68)
0.100 (2,54)
E
C
D
MAX
MIN
MAX
MIN
BSC
BSC
MAX
MIN
0.700
0.680
0.659
0.641
0.500
0.630
0.080
0.058
(2,03)
(1,47)
0.095
0.072
(2,41)
(1,83)
B
A
44
(17,78) (17,27) (16,74) (16,28) (12,70) (16,00)
1.000
0.980
0.960
0.940
0.800
0.930
68
(25,40) (24,89) (24,38) (23,88) (20,32) (23,62)
4040139/C 10/98
NOTES: A.
B.
C.
D.
34
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
The index mark may appear on top or bottom depending on package vendor.
This package is hermetically sealed with a metal lid.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
GB (S-CPGA-P68)
CERAMIC PIN GRID ARRAY PACKAGE
0.970 (24,63)
0.950 (24,13)
0.536 (13,61)
0.800 (20,32) TYP
0.524 (13,31)
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
0.088 (2,23)
0.072 (1,83)
0.100 (2,54)
0.194 (4,98)
0.166 (4,16)
0.055 (1,39)
0.045 (1,14)
0.050 (1,27) DIA
4 Places
0.018 (0,46) DIA TYP
4040114-14/C 04/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Index mark may appear on top or bottom depending vendor.
Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within
0.030 (0,76) diameter relative to the edges of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold plated or solder dipped.
G. Falls within MIL STD 1835 CMGA1-PN, CMGA13-PN and JEDEC MO-067 AA, MO-066 AA respectively
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
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