CGS2535V/CGS2535TV Commercial Quad 1 to 4 Clock Drivers/Industrial Quad 1 to 4 Clock Drivers General Description These Clock Generation and Support clock drivers are specifically designed for driving memory arrays requiring large fanouts while operating at high speeds. This device meets the rise and fall time requirements of the 90 and 100 MHz Pentium™ processors. The CGS2535 is a non-inverting 4 to 16 driver with CMOS I/O structures. The CGS2535 specification guarantees part-to-part skew variation. Features n Guaranteed: — 1.0 ns rise and fall times while driving 12 inches of 50Ω microstrip terminated with 25 pF Connection Diagrams — 350 ps pin-to-pin skew (tOSLH and tOSHL) n 650 ps part-to-part variation on positive or negative transition @ 5V VCC n Operates with either 3.3V or 5.0V supply n Inputs 5V tolerant with VCC in 3.3V range n Symmetric output current drive: 24 mA IOH/IOL n Industrial temperature range −40˚C to +85˚C n Symmetric package orientation n Large fanout for memory driving applications n Guaranteed 2 kV ESD protection n Implemented on National’s ABT family process n 28-pin PLCC for optimum skew performance CGS2535 Pin Assignment for 28-Pin PLCC DS011954-2 DS011954-5 Truth Table Input Output In (0–3) ABCD Out (0–3) Pentium™ is a trademark of Intel Corporation. © 1997 National Semiconductor Corporation DS011954 http:\\www.national.com CGS2535V Commercial Quad 1 to 4 Clock Drivers/CGS2535TV Industrial Quad 1 to 4 Clock Drivers March 1997 Absolute Maximum Ratings 900 LFM (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Input Voltage (VI) Input Current Current Applied to Output (High/Low) Operating Temp. Industrial grade Comm. grade Storage Temperature Range Airflow 0 LFM 225 LFM 500 LFM 27˚C/W Recommended Operating Conditions 7.0V 7.0V −30 mA Supply Voltage VCC 4.75V to 5.25V VCC 3.0V to 3.6V Maximum Input Rise/Fall Time (0.8V to 2.0V) Free Air Operating Temperature Commercial Industrial Twice the Rated IOH/IOL −40˚C to +85˚C 0˚C to +70˚C −65˚C to +150˚C Typical θJA 62˚C/W 43˚C/W 34˚C/W 5 ns 0˚C to + 70˚C −40˚C to + 85˚C Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation. DC Electrical Characteristics Over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25˚C. Symbol VIH VIL Parameter Conditions Input High Level Voltage Input Low Level Voltage VIK Input Clamp Voltage VOH High Level Output Voltage II = −18 mA IOH = −50 µA IOH = −24 mA VOL Low Level Output Voltage IOL = 50 µA IOL = 24 mA Input Current @ Max Input Voltage II VIH = 7V VIH = VCC VIH = VCC IIH High Level Input Current IIL Low Level Input Current IOLD Minimum Dynamic Output Current (Note 2) VIL = 0V VOLD = 1.65V (max) VOLD = 0.9V (max) IOHD Minimum Dynamic Output Current (Note 2) VOHD = 3.85V (min) VOHD = 2.1V (min) ICC CIN Min 3.0 2.1 4.5 3.15 5.5 3.85 Typ Input Capacitance 3.0 0.9 4.5 1.35 5.5 1.65 4.5 −1.2 3.0 2.9 4.5 4.4 5.5 5.4 3.0 2.46 4.5 3.76 5.5 4.76 Note 3: At VCC = 3.3V, IOLD = 55 mA min; @ VCC = 3.6V, IOLD = 64 mA min At VCC = 3.3V, IOHD = −58 mA min; @ VCC = 3.6V, IOHD = −66 mA min 2 Units V V V V 3.0 0.1 4.5 0.1 5.5 0.1 3.0 0.44 4.5 0.44 5.5 0.44 5.5 7 3.6 1 5 V V µA µA 5.5 −5 µA 5.5 75 mA 3.0 (Note 3) 36 5.5 −75 3.0 (Note 3) −25 mA 3.6 75 5.5 235 5.0 Note 2: Maximum test duration 2.0 ms, one output loaded at a time. Max V 5.5 Supply Current http:\\www.national.com VCC (V) 5 µA pF AC Electrical Characteristics (Notes 4, 5, and 6) Over recommended operating free air temperature specified. All typical values are measured at VCC = 5V, TA = 25˚C. VCC Symbol Parameter (V) (Note 11) CGS2535 TA = +25˚C TA = −40˚C to +85˚C CL = 50 pF, RL = 500Ω (Note 7) CL = 50 pF, RL = 500Ω Min fmax tPLH tPHL tPLH tPHL tOSLH Frequency Maximum Typ Max Min Typ 3.0 100 5.0 125 Units Max MHz Low-to-High Propagation Delay 3.3 4.5 2.5 4.5 CK to On @ 1 MHz (Note 13) 5.0 3.5 2.0 3.5 High-to-Low Propagation Delay 3.3 4.5 2.5 4.5 CK to On @ 1 MHz (Note 13) 5.0 3.5 2.0 3.5 Low-to-High Propagation Delay 3.3 5.0 2.5 5.0 CK to On @ 66.67 MHz (Note 13) , (Note 14) 5.0 4.5 2.0 4.5 High-to-Low Propagation Delay 3.3 5.0 2.5 5.0 CK to On @ 66.67 MHz (Note 13) , (Note 14) 5.0 4.5 2.0 4.5 Maximum Skew Common Edge 3.3 150 350 300 350 Output-to-Output Variation 5.0 150 350 300 350 Maximum Skew Common Edge 3.3 150 350 300 350 Output-to-Output Variation 5.0 150 350 300 350 ns ns ns ns ps (Note 4) , (Note 6) tOSHL ps (Note 4) , (Note 6) trise, Rise/Fall Time 3.3 3.5 3.5 tfall (from 0.8V/2.0V to 2.0V/0.8V) (Note 8) 5.0 3.0 3.0 trise, Rise/Fall Time 3.3 0.8 1.0 tfall (from 0.8V/2.0V to 2.0V/0.8V) (Note 9) , (Note 14) 5.0 0.4 0.6 ns ns trise, Rise/Fall Time 3.3 1.0 1.0 tfall (from 0.8V/2.0V to 2.0V/0.8V) (Note 10) , (Note 14) 5.0 0.7 0.9 tHigh Pulse Width Duration High 3.3 4.0 4.0 (Note 5) , (Note 6) , (Note 14) 5.0 4.0 4.0 Pulse Width Duration Low 3.3 4.0 4.0 (Note 5) , (Note 6) , (Note 14) 5.0 4.0 Part-to-Part Variation of 3.3 650 1.0 ns Low-to-High Transitions 5.0 650 650 ps tLow tPVLH ns ns 4.0 @ 1 MHz (Note 13) tPVHL Part-to-Part Variation of 3.3 650 1.0 ns High-to-Low Transitions 5.0 650 650 ps @ 1 MHz (Note 13) tPVLH Part-to-Part Variation of 3.3 1.0 1.0 Low-to-High Transitions 5.0 1.0 1.0 Part-to-Part Variation of 3.3 1.0 1.0 High-to-Low Transitions 5.0 1.0 1.0 @ 66.67 MHz (Note 13) , (Note 14) tPVHL ns @ 66.67 MHz (Note 13) , (Note 14) Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device and output bank. The specifications apply to any outputs switching in the same direction either LOW to HIGH (tOSLH) or HIGH to LOW (tOSHL). Note 5: Time high is measured with outputs at 2.0V or above. Time low is measured with outputs at 0.8V or below. Input waveform characteristics for tHigh, tLow measurement: f = 66.67 MHz, duty cycle = 50%. 3 http:\\www.national.com AC Electrical Characteristics (Notes 4, 5, and 6) (Continued) Note 6: The input waveform has a rise and fall time transition time of 2.5 ns (10% to 90%). Note 7: Industrial range (−40˚C to +85˚C) limits apply to the commercial temperature range (0˚C to +70˚C). Note 8: These Rise and Fall times are measured with CL = 50 pF, RL = 500Ω (see Figure 1). Note 9: These Rise and Fall times are measured with CL = 25 pF, RL = 500Ω (see Figure 1), and are guaranteed by design. Note 10: These Rise and Fall times are measured driving 12 inches of 50Ω microstrip terminated with equivalent CL = 25 pF (see Figure 2), and are guaranteed by design. Note 11: Voltage Range 5.0 is 5.0V ± 0.25V, 3.3 is 3.3V ± 0.3V. Note 12: For increased output drive, output pins may be connected together when the corresponding input pins are connected together. Note 13: All 16 outputs switching simultaneously. Note 14: Guaranteed by design. Timing Information DS011954-7 DS011954-9 FIGURE 1. A.C. Load (Notes 8 and 9) CL = Total Load Including Probes DS011954-10 FIGURE 2. A.C. Load (Note 10) CL = Total Load Including Probes http:\\www.national.com 4 CGS2534/35/36/37 Memory Array Driving Another feature associated with these clock drivers is a 350 ps pin-to-pin skew specification. The minimum skew specification allows high speed memory system designers to optimize the performance of their memory sub-system by operating at higher frequencies without having concerns about output-to-output (bank-to-bank) synchronization problems which are associated with driving high capacitive loads (Point B). The diagram below depicts a “2534/35/36/37” a memory subsystem operating at high speed with large memory capacity. The address bus is common to both the memory and the CPU and I/Os. In order to minimize the total load on the address bus, quite often memory arrays are driven by buffers while having the inputs of the buffers tied together. Although this practice was feasible in the conventional memory designs, in today’s high speed, large buswidth designs which require address fetching at higher speeds, this technique produces many undesired results such as cross-talk and over/undershoot. CGS2534/35/36/37 Quad 1 to 4 clock drivers were designed specifically to address these application issues on high speed, large memory arrays systems. These drivers are optimized to drive large loads, with 3.5 ns propagation delays. These drivers produce less noise while reducing the total capacitive loading on the address bus by having only four inputs tied together (see the diagram below, point A). This helps to minimize the overshoot and undershoot by having only four outputs being switched simultaneously. Also this larger fan-out helps to save board space since for every one of these drivers, two conventional buffers were typically being used. These drivers can operate beyond 125 MHz, and are also available in 3V–5V TTL/CMOS versions with large current drive . DS011954-8 Device VCC I/O 2534 5 TTL 2535 3 or 5 CMOS 2536 3 or 5 CMOS 2537 5 TTL Output Configuration Inverting quad 1–4 Non-inverting quad 1–4 Inverting, Non-inverting, ÷2 Inverting quad 1–4 with series 8Ω output resistors 5 http:\\www.national.com Ordering Information (Contact NSC Marketing for specific date of availability) DS011954-11 http:\\www.national.com 6 7 CGS2535V Commercial Quad 1 to 4 Clock Drivers/CGS2535TV Industrial Quad 1 to 4 Clock Drivers Physical Dimensions inches (millimeters) 28-Lead Molded Plastic Leaded Chip Carrier Order Number CGS2535V or CGS2535TV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 http:\\www.national.com National Semiconductor Europe Fax: (+49) 0-180-530 85 86 Email: [email protected] Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Français Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. 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