ETC 74LCX162541

74LCX162541
LOW VOLTAGE CMOS 16-BIT BUS BUFFER (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
■
■
■
■
■
■
■
■
■
■
■
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
tPD = 4.4 ns (MAX.) at VCC = 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3V
PCI BUS LEVELS GUARANTEED AT 12 mA
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
26Ω SERIE RESISTORS IN OUTPUTS
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 162541
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74LCX162541TTR
PIN CONNECTION
DESCRIPTION
The 74LCX162541 is a low voltage CMOS 16 BIT
BUS BUFFER (NON-INVERTED) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
This is composed of two 8-bit sections with separate output-enable signals. For either 8-bit buffers
section, the 3 STATE control gate operates as a
two input AND such that if either nG1 and nG2 are
high, all outputs are in the high impedence state.
This device is designed to be used with 3 state
memory address drivers, etc.
The device circuits is including 26Ω series resistance in the outputs. These resistors permit to reduce line noise in high speed applications.
All inputs and outputs are equipped with protection circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
February 2003
1/10
74LCX162541
INPUT AND OUTPUT EQUIVALENT CIRCUIT
IEC LOGIC SYMBOLS
PIN DESCRIPTION
PIN No
1, 48
2, 3, 5, 6, 8, 9,
11, 12
13, 14, 16, 17,
19, 20, 22, 23
24, 25
36, 35, 33, 32,
30, 29, 27, 26
47, 46, 44, 43,
41, 40, 38, 37
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42
SYMBOL
NAME AND FUNCTION
1G1, 1G2 Output Enable Inputs
1Y1 to 1Y8 Data Outputs
2Y1 to 2Y8 Data Outputs
2G1, 2G2 Output Enable Inputs
2A1 to 2A8 Data Outputs
1A1 to 1A8 Data Outputs
GND
Ground (0V)
VCC
Positive Supply Voltage
TRUTH TABLE
INPUTS
G1
G2
An
Yn
H
X
L
L
X
H
L
L
X
X
H
L
Z
Z
H
L
X : Don‘t Care
Z : High Impedance
2/10
OUTPUT
74LCX162541
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Unit
Supply Voltage
-0.5 to +7.0
V
VI
DC Input Voltage
-0.5 to +7.0
V
VO
DC Output Voltage (OFF State)
VO
DC Output Voltage (High or Low State) (note 1)
-0.5 to +7.0
V
-0.5 to VCC + 0.5
- 50
V
mA
IIK
DC Input Diode Current
IOK
DC Output Diode Current (note 2)
- 50
mA
IO
DC Output Current
± 50
mA
ICC
DC Supply Current per Supply Pin
± 100
mA
IGND
DC Ground Current per Supply Pin
± 100
mA
Tstg
Storage Temperature
-65 to +150
°C
TL
Lead Temperature (10 sec)
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage (note 1)
Value
Unit
2.0 to 3.6
V
VI
Input Voltage
0 to 5.5
V
VO
Output Voltage (OFF State)
0 to 5.5
V
VO
Output Voltage (High or Low State)
0 to VCC
V
IOH, IOL
High or Low Level Output Current (VCC = 3.0 to 3.6V)
IOH, IOL
High or Low Level Output Current (VCC = 2.7V )
Top
dt/dv
Operating Temperature
Input Rise and Fall Time (note 2)
± 12
mA
±8
mA
-55 to 125
°C
0 to 10
ns/V
1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
3/10
74LCX162541
DC SPECIFICATIONS
Test Condition
Symbol
VIH
VIL
VOH
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Ioff
IOZ
ICC
∆ICC
Input Leakage
Current
Power Off Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
ICC incr. per Input
Min.
Max.
2.0
-55 to 125 °C
Min.
Unit
Max.
2.0
V
2.7 to 3.6
0.8
0.8
2.7 to 3.6
IO=-100 µA
VCC-0.2
VCC-0.2
2.7
IO=-8 mA
2.0
2.0
IO=-6 mA
2.4
2.4
IO=-12 mA
2.0
2.0
V
V
2.7 to 3.6
IO=100 µA
2.7
IO=8 mA
0.6
0.6
IO=6 mA
0.55
0.55
IO=12 mA
0.8
0.8
2.7 to 3.6
VI = 0 to 5.5V
±5
±5
µA
0
VI or VO = 5.5V
10
10
µA
2.7 to 3.6
VI = VIH or VIL
VO = 0 to VCC
±5
±5
µA
2.7 to 3.6
VI = VCC or GND
VI or VO= 3.6 to 5.5V
20
20
± 20
± 20
2.7 to 3.6
VIH = VCC - 0.6V
500
500
3.0
II
-40 to 85 °C
VCC
(V)
3.0
VOL
Value
0.2
0.2
V
µA
µA
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Symbol
VOLP
VOLV
Parameter
Dynamic Low Level Quiet
Output (note 1)
TA = 25 °C
VCC
(V)
3.3
Value
Min.
CL = 50pF
VIL = 0V, VIH = 3.3V
Typ.
0.8
-0.8
Unit
Max.
V
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
4/10
74LCX162541
AC ELECTRICAL CHARACTERISTICS
Test Condition
Symbol
Parameter
tPLH tPHL
Propagation Delay
Time
tPZL tPZH
Output Enable Time
tPLZ tPHZ
Output Disable Time
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
VCC
(V)
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
CL
(pF)
RL
(Ω)
Value
ts = tr
(ns)
50
500
2.5
50
500
2.5
50
500
2.5
50
500
2.5
-40 to 85 °C
-55 to 125 °C
Min.
Max.
Min.
Max.
1.5
1.5
1.5
1.5
1.5
1.5
5.6
4.4
6.3
5.9
6.3
5.9
1.0
1.5
1.5
1.5
1.5
1.5
1.5
6.5
5.1
7.2
6.8
7.2
6.8
1.0
Unit
ns
ns
ns
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
CIN
COUT
CPD
Parameter
Value
TA = 25 °C
VCC
(V)
Min.
Typ.
Unit
Max.
Input Capacitance
4
pF
Output Capacitance
10
pF
Power Dissipation Capacitance
(note 1)
3.3
fIN = 10MHz
VIN = 0 or VCC
50
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per
circuit)
5/10
74LCX162541
TEST CIRCUIT
TEST
tPLH, tPHL
SWITCH
Open
tPZL, tPLZ
6V
tPZH, tPHZ
GND
CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
6/10
74LCX162541
WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
7/10
74LCX162541
TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
1.2
A1
0.05
0.047
0.15
A2
MAX.
0.002
0.006
0.9
0.035
b
0.17
0.27
0.0067
0.011
c
0.09
0.20
0.0035
0.0079
D
12.4
12.6
0.488
0.496
E
8.1 BSC
E1
6.0
0.318 BSC
6.2
e
0.236
0.5 BSC
0.244
0.0197 BSC
K
0˚
8˚
0˚
8˚
L
0.50
0.75
0.020
0.030
A
A2
A1
b
K
e
L
E
c
D
E1
PIN 1 IDENTIFICATION
1
7065588C
8/10
74LCX162541
Tape & Reel TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
TYP
MAX.
MIN.
330
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
TYP.
0.504
30.4
0.519
1.197
Ao
8.7
8.9
0.343
0.350
Bo
13.1
13.3
0.516
0.524
Ko
1.5
1.7
0.059
0.067
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
9/10
74LCX162541
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
© http://www.st.com
10/10