74LVC541A OCTAL D-TYPE LATCH HIGH PERFORMANCE PRELIMINARY DATA ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS HIGH SPEED: tPD = 4.2ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 541 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LVC541A is a low voltage CMOS OCTAL BUS BUFFER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. The 3 STATE control gate operates as two input AND such that if either G1 or G2 are high, all eight outputs are in the high impedance state. SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74LVC541AM 74LVC541AMTR 74LVC541ATTR In order to enhance PC board layout, the 74LVC541A offers a pinout having inputs and outputs on opposite sides of the package. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS February 2002 1/9 This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice. 74LVC541A INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION TRUTH TABLE PIN No SYMBOL 1, 19 2, 3, 4, 5, 6, 7, 8, 9 18, 17, 16, 15, 14, 13, 12, 11 10 20 G1, G2 A1 to A8 Output Enable Inputs Data Inputs Y1 to Y8 Data Outputs GND V CC NAME AND FUNCTION Ground (0V) Positive Supply Voltage INPUT OUTPUT G1 G2 An Yn H X L L X H L L X X H L Z Z H L X=Don’t care; Z=High Impedance ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Supply Voltage Value Unit -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (V CC = 0V) -0.5 to +7.0 V VO DC Output Voltage (High or Low State) (note 1) IIK DC Input Diode Current IOK IO -0.5 to VCC + 0.5 V - 50 mA DC Output Diode Current (note 2) - 50 mA DC Output Current ± 50 mA ICC or IGND DC VCC or Ground Current per Supply Pin Tstg Storage Temperature TL Lead Temperature (10 sec) ± 100 mA -65 to +150 °C 300 °C Absolute Maximum Rating are those value beyond which damage to the device may occour. Functional operation under these condition is not implied 1) IO absolute maximum rating must be observed 2) VO < GND, VO > V CC 2/9 74LVC541A RECOMMENDED OPERATING CONDITIONS Symbol V CC Parameter Supply Voltage (note 1) Value Unit 1.65 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage (V CC = 0V) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V High or Low Level Output Current (V CC = 3.0 to 3.6V) High or Low Level Output Current (V CC = 2.7 to 3.0V) ± 24 mA ± 12 mA High or Low Level Output Current (V CC = 2.3 to 2.7V) High or Low Level Output Current (V CC = 1.65 to 2.3V) ±8 mA IOH, IOL IOH, IOL IOH, IOL IOH, IOL Top dt/dv Operating Temperqture Input Rise and Fall Time (note 2) ±4 mA -40 to 85 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V DC SPECIFICATION Test Condition Symbol VIH VIL V OH VOL II Ioff IOZ ICC ∆ICC Parameter Value -40 to 85 °C VCC (V) Min. Max. -55 to 125 °C Min. Max. High Level Input Voltage 1.65 to 1.95 0.65VCC 0.65VCC 2.3 to 2.7 2.7 to 3.6 1.7 2 1.7 2 Low Level Input Voltage 1.65 to 1.95 0.35VCC 0.35VCC 2.3 to 2.7 2.7 to 3.6 0.7 0.8 0.7 0.8 High Level Ouput Voltage 1.65 to 3.6 IO=-100 µA VCC-0.2 VCC-0.2 1.65 IO=-4 mA 1.2 1.2 Low Level Output Voltage Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input Unit V 2.3 IO=-8 mA 1.7 1.7 2.7 IO=-12 mA 2.2 2.2 3.0 IO=-18 mA 2.4 2.4 3.0 IO=-24 mA 2.2 2.2 1.65 to 3.6 IO=100 µA 0.2 0.2 1.65 IO=4 mA 0.45 0.45 V V 2.3 IO=8 mA 0.7 0.7 2.7 IO=12 mA 0.4 0.4 3.0 IO=24 mA 0.55 0.55 3.6 VI = 0 to 5.5V ±5 ±5 µA 0 V I or VO = 5.5V 100 100 µA 3.6 V I = VIH orV IL V O = 0 to 5.5V ±5 ±5 µA VI = VCC or GND 10 10 VI or VO = 3.6 to 5.5V V IH = VCC-0.6V ± 10 ± 10 500 500 3.6 2.7 to 3.6 V µA µA 3/9 74LVC541A DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP V OLV Parameter Value TA = 25 °C VCC (V) Dynamic Low Level Quiet Output (note 1) 3.3 Min. Typ. Unit Max. 0.8 CL = 50pF VIL = 0V, V IH = 3.3V V -0.8 1) Number of output defined as ”n”. Measured with ”n-1” outputs switching from HIGH to LOW or LOW to HIGH. The remaining outputs is measured in the LOW state. AC ELECTRICAL CHARACTERISTICS Test Conditio n Symbol tPLH t PHL tPZL tPZH tPLZ tPHZ tOSLH tOSHL Parameter VCC (V) Propagation Delay Time 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Output Enable Time 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Output Disable Time 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Output To Output 2.7 to 3.6 Skew Time (note1, 2) Value CL (pF) RL (Ω) ts = tr (ns) 30 30 50 50 30 30 50 50 30 30 50 50 1000 500 500 500 1000 500 500 500 1000 500 500 500 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 -40 to 85 °C Min. Max. -55 to 125 °C Min. 1.5 1 1.5 1 1 1 1 1 2 2 2 2 1 Unit Max. ns ns ns 1 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn| 2) Parameter guaranteed by design CAPACITANCE CHARACTERISTICS Test Condition Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (note 1) TA = 25 °C VCC (V) 1.8 2.5 3.3 Value Min. fIN = 10MHz Typ. Unit Max. 4 pF 28 30 34 pF 1) CPD is defined as the value of the IC’s internal equivqlent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average current cqn be obtqined by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) 4/9 74LVC541A TEST CIRCUIT R T = ZOUT of pulse generator (typically 50Ω) TEST CIRCUIT AND WAVEFORM SYMBOL VALUE VCC Symbol CL 1.65 to 1.95V 2.3 to 2.7V 2.7V 3.0 to 3.6V 30pF 30pF 50pF 50pF RL = R1 1000Ω 500Ω 500Ω 500Ω VS 2 x V CC VCC 6V 7V V IH 2 x V CC VCC 2.7V 3.0V VM VCC/2 VCC/2 1.5V 1.5V VOH VCC VCC 3.0V 3.5V VX VOL + 0.15V VOL + 0.15V VOL + 0.3V VOL + 0.3V VY VOH - 0.15V VOH - 0.15V VOH - 0.3V VOH - 0.3V tr = tr <2.0ns <2.0ns <2.5ns <2.5ns 5/9 74LVC541A WAVEFORM 1: PROPAGATION DELAYS, (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) 6/9 74LVC541A SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A a1 MAX. MIN. TYP. 2.65 0.1 0.104 0.2 a2 MAX. 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 M S 0.75 0.029 8° (max.) PO13L 7/9 74LVC541A TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.0256 BSC 0.60 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 8/9 74LVC541A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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