CR4350S CR4350S GAME BOY COLOR DECODER 1.General Description C R4350S is a programmable memory bank controller designed by CMOS technology. It is used for Game Boy Color Card. 2.Features ?? ?? ?? ?? ?? ?? ?? ?? Operation votalge: 3.0V~5.0V. Internal power on reset and adjusting reset time by external capacity. Three modes: MBC1 MBC3 MBC5. External 32768Hz crystal if game code needs clock. For one 16M x 8-bit ROM or two 8M x 8-bit ROMs directly. External 257 TTL for one 8M x 16-bit ROM or two 4M x 16-bit ROMs. Most access 128K x 8-bit RAM. Support one game or multi-game application. 3.Pin Descriptions No. Name I/O 1 VDD Power ２ DATA7 I/O Data input / output ３ DATA6 I/O Data input / output ４ DATA5 I/O Data input / output ５ DATA4 I/O Data input / output ６ DATA3 I/O Data input / output ７ DATA2 I/O Data input / output ８ DATA1 I/O Data input / output 9 DATA0 I/O Data input / output 10 GND Power 11 A15 I Address input 12 A14 I Address input 13 A13 I Address input 14 A12 I Address input 15 SA16 O Expand ROM address output 16 SA15 O Expand RAM address output 17 SA14 O Expand RAM address output 18 SA13 O Expand RAM address output 19 TEST0 O Test mode select (=H is test mode) 20 MOTOR O Drive Motor (only for converting a MBC5 cart to a Rumble cart) 21 XTAL1 O Crystal output File:@doc.CR4350S Function Positive power supply Negative power supply -1- Last rev: 2003/7/15 上午 09:07 CR4350S 22 XTAL2 I Crystal input 23 EA14 O Expand ROM address output 24 EA15 O Expand ROM address output 25 EA16 O Expand ROM address output 26 EA17 O Expand ROM address output 27 EA18 O Expand ROM address output 28 EA19 O Expand ROM address output 29 EA20 O Expand ROM address output 30 EA21 O Expand ROM address output 31 EA22 O Expand ROM address output 32 RESET I Power-On Reset MBC 33 VCC 34 CS1 O ROM chip select control 35 CS2 O ROM chip select control 36 RAMENB O RAM chip select control 37 TEST1 I Test result output 38 GBCRST O (Power-on and Software)Reset GBC 39 VBAT 40 OEB I Output enable input 41 WEB I Write enable input 42 ATCAP I Connect CAP to adjust software reset time Power Come from GBC Power Battery positive pole 4.Pad Diagram NO. NAME X Y NO. NAME X Y 1 2 3 VDD DATA7 DATA6 610 471 332 703 707 707 22 23 24 XTAL2 EA14 EA15 -636 -492 -353 -701 -702 -702 4 5 DATA5 DATA4 193 54 707 707 25 26 EA16 EA17 -214 -75 -702 -702 6 7 DATA3 DATA2 -85 -224 707 707 27 28 EA18 EA19 64 203 -702 -702 8 9 DATA1 DATA0 -363 -502 707 707 29 30 EA20 EA21 342 481 -702 -702 10 11 GND A15 -624 -746 717 712 31 32 EA22 RESET 620 761 -702 -701 12 13 A14 A13 -746 -746 572 433 33 34 VCC CS1 742 742 -517 -378 14 15 A12 SA16 -746 -746 293 138 35 36 CS2 RAMENB 742 742 -239 -100 16 17 SA15 SA14 -746 -746 -2 -141 37 38 TEST1 GBCRST 742 742 39 178 File:@doc.CR4350S -2- Last rev: 2003/7/15 上午 09:07 CR4350S NO. NAME X Y NO. NAME X Y 18 19 SA13 TEST0 -746 -746 -280 -422 39 40 VBAT OEB 742 742 317 458 20 21 MOTOR XTAL1 -746 -776 -562 -701 41 42 WEB ATCAP 742 742 598 737 11 10 9 8 7 6 5 4 3 2 1 42 12 41 13 40 14 39 Y 38 15 37 16 0,0 X 17 36 CR4350S 35 18 CR4350S 19 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 Chip Size: (1920,1830) Unit: um Note: The substrate must be connected to GND File:@doc.CR4350S -3- Last rev: 2003/7/15 上午 09:07 CR4350S 4.Function Description 1. Write (1 st) 7000H Register Format D7 D6 D5 D4 EA22 EA21 EA20 EA19 @ 0 0 0 0 note: @ indicate default value. 2. Write (2 nd) 7001H Register Format D7 D6 D5 D4 Sbit Pack ( Mode ) @ 0 0 0 0 note: @ indicate default value. Game Size: D2 D1 D0 Game Size 0 0 0 32Mbit 0 0 1 16Mbit 0 1 0 8Mbit 0 1 1 4Mbit 1 0 0 2Mbit 1 0 1 1Mbit 1 1 0 512Kbit 1 1 1 256Kbit D3 EA18 0 D2 EA17 0 D3 EA23 0 D2 ( 0 D1 EA16 0 D0 EA15 0 D1 D0 Game Size ) 0 0 Rumble D6 0 1 Pack: Rumble Pack Off On Mode: D5 D4 0 0 MBC3 Mode 0 1 MBC1 Mode 1 0 MBC5 Mode Sbit (SRAM Bit): D7 SRAM 1 SRAM Disable @ 0 SRAM Enable note: @ indicate default value. Chip Select: D3 ROM Chip Select 0 CS1=0 1 CS2=1 3. Write (3 rd ) 7002H Register Format D7 D6 D5 D4 D3 D2 D1 D0 Reset L_Bit RS1 RS0 RB3 RB2 RB1 RB0 @ 0 0 0 0 0 0 0 0 note: @ indicate default value. SRAM BANK SELECT(D3,D2,D1,D0): SRAM 1MBit SRAM 512KBit RB3=SA16. SRAM 256KBit RB3=SA16,RB2=SA15. SRAM 64KBit RB3=SA16,RB2=SA15,RB1=SA14,RB0=SA13. SRAM SIZE: D5 D4 0 0 0 1 File:@doc.CR4350S SRAM SIZE 256KBit 512KBit -4- Last rev: 2003/7/15 上午 09:07 CR4350S 1 0 64KBit 1 1 1MBit L_Bit (Lock Bit) D6 Lock Bit 0 Non Lock 1 Lock note: ‘Lock’indicate that writing 7000H-7002H is inhibited. Reset Bit: 0 System Non Reset 1 System Reset PROGRAM SEQUENCE <1> <2> <3> note: Write XXH to 7000H Write XXH to 7001H Write XXH to 7002H XX=Valid value Select ROM Bank. Select Game size & game mode Select RAM Bank & GB System Reset. Example: : : : ;-------------------------------------first write--------------------------------------------------------LD A, $02 ;$02=00000010B LD [$7000],A ;select ROM address 10000H---1FFFFH ;-------------------------------------second write----------------------------------------------------LD A,$86 ;$86=10000110B LD [$7001],A ;game size 64Kbyte, MBC3 mode, disable SRAM ;-------------------------------------third write-------------------------------------------------------LD A,$C0 LD [$7002],A ;disable writing 7000H register and reset GB system : : : File:@doc.CR4350S -5- Last rev: 2003/7/15 上午 09:07 CR4350S 6. Application Circuit For 8-bit ROM Application 3V File:@doc.CR4350S -6- Last rev: 2003/7/15 上午 09:07 CR4350S For 16-bit ROM Application 3V File:@doc.CR4350S -7- Last rev: 2003/7/15 上午 09:07 CR4350S NOTICE: 1.The information here contained could be changed without notice owing to product and /or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. 2. No responsibility is assumed by us for any consequence resulting from any wrong or improper operation, etc.of the product. File:@doc.CR4350S -8- Last rev: 2003/7/15 上午 09:07