FUJITSU MB91101

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16301-4E
32-bit RISC Microcontroller
CMOS
FR30 MB91101 Series
MB91101/MB91101A
■ DESCRIPTION
The MB91101 and MB91101A are a standard single-chip microcontroller constructed around the 32-bit RISC
CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/
high-speed CPU processing for embedded controller applications. To support the vast memory space accessed
by the 32-bit CPU, the MB91101 and MB91101A normally operate in the external bus access mode and executes
instructions on the internal 1 Kbyte cache memory and 2 Kbytes RAM for enhanced performance.
The MB91101 and MB91101A are optimized for applications requiring high-performance CPU processing such
as navigation systems, high-performance FAXs and printer controllers.
*: FR Family stands for FUJITSU RISC controller.
■ FEATURES
FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
• General purpose registers: 32 bits × 16
• 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
• Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems
supporting high level languages
(Continued)
■ PACKAGES
100-pin Plastic LQFP
100-pin Plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB91101/MB91101A
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots: Reduced overhead time in branch executions
• Internal multiplier/supported at instruction level
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
• Interrupt (push PC and PS): 6 cycles, 16 priority levels
External bus interface
• Clock doubler: Internal 50 MHz, external bus 25 MHz operation
• 25-bit address bus (32 Mbytes memory space)
• 8/16-bit data bus
• Basic external bus cycle: 2 clock cycles
• Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6
• Interface supported for various memory technologies
DRAM interface (area 4 and 5)
• Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
• Unused data/address pins can be configured as input/output ports.
• Little endian mode supported (Select 1 area from area 1 to 5)
DRAM interface
• 2 banks independent control (area 4 and 5)
• Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM
• Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
• Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
• DRAM refresh
CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode
• Supports 8/9/10/12-bit column address width
• 2CAS/1WE, 2WE/1CAS selective
Cache memory
• 1-Kbyte instruction cache memory
• 32 block/way, 4 entry(4 word)/block
• 2 way set associative
• Lock function: For specific program code to be resident in cashe memory
DMA controller (DMAC)
• 8 channels
• Transfer incident/external pins/internal resource interrupt requests
• Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
• Transfer data length: 8 bits/16 bits/32 bits selective
• NMI/interrupt request enables temporary stop operation.
UART
• 3 independent channels
• Full-duplex double buffer
• Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
• Asynchronous (start-stop system), CLK-synchronized communication selective
• Multi-processor mode
• Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate
• External clock can be used as a transfer clock.
• Error detection: Parity, frame, overrun
(Continued)
2
MB91101/MB91101A
(Continued)
10-bit A/D converter (successive approximation conversion type)
• 10-bit resolution, 4 channels
• Successive approximation type: Conversion time of 5.6 µs at 25 MHz
• Internal sample and hold circuit
• Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective
• Start: Software/external trigger/internal timer selective
16-bit reload timer
• 3 channels
• Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective
Other interval timers
• 16-bit timer: 3 channels (U-TIMER)
• PWM timer: 4 channels
• Watchdog timer: 1 channel
Bit search module
First bit transition “1” or “0” from MSB can be detected in 1 cycle.
Interrupt controller
• External interrupt input: Non-maskable interrupt (NMI), normal interrupt × 4 (INT0 to INT3)
• Internal interrupt incident:UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt
module
• Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps).
Others
• Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset
• Low-power consumption mode: Sleep mode/stop mode
• Clock control
Gear function: Operating clocks for CPU and peripherals are independently selective.
Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16).
However, operating frequency for peripherals is less than 25 MHz.
• Packages: LQFP-100 and QFP-100
• CMOS technology (0.35 µm)
• Power supply voltage
5 V: CPU power supply 5.0 V ±10% (internal regulator)
A/D power supply 2.7 V to 3.6 V
3 V: CPU power supply 2.7 V to 3.6 V (without internal regulator)
A/D power supply 2.7 V to 3.6 V
3
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
D24
D25
D26
D27
D28
D29
D30
VSS
D31
A00
VCC5
A01
A02
A03
A04
A05
A06
A07
CS1L/PB5/DREQ2
CS1H/PB6/DACK2
DW1/PB7
VCC3
CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3/EOP1
CS2/PA2
CS1/PA1
CS0
NMI
HST
RST
VSS
MD0
MD1
MD2
RDY/P80
BGRNT/P81
BRQ/P82
RD
WR0
WR1/P85
D16/P20
4
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RAS1/PB4/EOP2
DW0/PB3
CS0H/PB2
CS0L/PB1
RAS0/PB0
INT0/PE0
INT1/PE1
VCC5
X0
X1
VSS
INT2/SC1/PE2
INT3/SC2/PE3
DREQ0/PE4
DREQ1/PE5
DACK0/PE6
DACK1/PE7
OCPA0/PF7/ATG
SO2/OCPA2/PF6
SI2/OCPA1/PF5
SO1/TRG3/PF4
SI1/TRG2/PF3
SC0/OCPA3/PF2
SO0/TRG1/PF1
SI0/TRG0/PF0
MB91101/MB91101A
■ PIN ASSIGNMENT
(Top view)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AN3
AN2
AN1
AN0
AVSS/AVRL
AVRH
AVCC
A24/EOP0
A23/P67
A22/P66
VSS
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
A15
A14
A13
A12
A11
A10
A09
A08
(FPT-100P-M05)
(Continued)
MB91101/MB91101A
(Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CS0L/PB1
RAS0/PB0
INT0/PE0
INT1/PE1
VCC5
X0
X1
VSS
INT2/SC1/PE2
INT3/SC2/PE3
DREQ0/PE4
DREQ1/PE5
DACK0/PE6
DACK1/PE7
OCPA0/PF7/ATG
SO2/OCPA2/PF6
SI2/OCPA1/PF5
SO1/TRG3/PF4
SI1/TRG2/PF3
SC0/OCPA3/PF2
(Top view)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SO0/TRG1/PF1
SI0/TRG0/PF0
AN3
AN2
AN1
AN0
AVSS/AVRL
AVRH
AVCC
A24/EOP0
A23/P67
A22/P66
VSS
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
D24
D25
D26
D27
D28
D29
D30
VSS
D31
A00
VCC5
A01
A02
A03
A04
CS0H/PB2
DW0/PB3
RAS1/PB4/EOP2
CS1L/PB5/DREQ2
CS1H/PB6/DACK2
DW1/PB7
VCC3
CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3/EOP1
CS2/PA2
CS1/PA1
CS0
NMI
HST
RST
VSS
MD0
MD1
MD2
RDY/P80
BGRNT/P81
BRQ/P82
RD
WR0
WR1/P85
D16/P20
D17/P21
D18/P22
(FPT-100P-M06)
5
MB91101/MB91101A
■ PIN DESCRIPTION
Pin no.
1
2
LQFP*
QFP*
25 to 32
28 to 35
33 to 39,
41
36 to 42,
44
42,
44 to 58
45,
47 to 61
Pin name
Circuit
type
D16 to D23
59 to 64,
66,
67
62 to 67,
69,
70
68
71
19
22
Bit 16 to bit 23 of external data bus
C
Can be configured as I/O ports when external data bus width is
set to 8-bit.
D24 to D30,
D31
C
Bit 24 to bit 31 of external data bus
A00,
A01 to A15
F
Bit 00 to bit 15 of external address bus
P20 to P27
A16 to A21,
A22,
A23
P60 to P65,
P66,
P67
Bit 16 to bit 23 of external address bus
F
Can be configured as I/O ports when not used as address bus.
A24
EOP0
RDY
Bit 24 of external address bus
L
C
P80
20
23
BGRNT
24
BRQ
F
23
24
25
26
27
RD
WR0
WR1
P85
External ready input
Inputs “0” when bus cycle is being executed and not completed.
External bus release acknowledge output
Outputs “L” level when external bus is released.
Can be configured as a port when BGRNT is not used.
C
P82
22
Can be configured as DMAC EOP output (ch. 0) when DMAC
EOP output is enabled.
Can be configured as a port when RDY is not used.
P81
21
Description
External bus release request input
Inputs “1” when release of external bus is required.
Can be configured as a port when BRQ is not used.
L
L
F
Read strobe output pin for external bus
Write strobe output pin for external bus
Relation between control signals and effective byte locations is
as follows:
16-bit bus width
8-bit bus width
D15 to D08
WR0
WR0
D07 to D00
WR1
(I/O port enabled)
WR1 is High-Z during resetting.
Attach an external pull-up resister when using at 16-bit bus
width.
Can be configured as a port when WR1 is not used.
*1: FPT-100P-M05
*2: FPT-100P-M06
(Continued)
6
MB91101/MB91101A
Pin no.
LQFP*1
QFP*2
11
14
10
13
9
12
Pin name
Circuit
type
CS0
L
CS1
PA1
CS2
PA2
F
F
CS3
11
10
6
9
5
8
CS4
PA4
CS5
PA5
CLK
F
F
F
PA6
96
99
RAS0
97
100
F
98
99
1
2
F
EOP output pin for DMAC (ch. 1)
This function is available when EOP output for DMAC is enabled.
Chip select 4 output (“L” active)
Can be configured as a port when CS4 is not used.
Chip select 5 output (“L” active)
Can be configured as a port when CS5 is not used.
System clock output
Outputs clock signal of external bus operating frequency.
RAS output for DRAM bank 0
Refer to the DRAM interface for details.
CASL output for DRAM bank 0
Refer to the DRAM interface for details.
F
CASH output for DRAM bank 0
Refer to the DRAM interface for details.
PB2
Can be configured as a port when CS0H is not used.
DW0
WE output for DRAM bank 0 (“L” active)
Refer to the DRAM interface for details.
F
Can be configured as a port when DW0 is not used.
RAS output for DRAM bank 1
Refer to the DRAM interface for details.
RAS1
3
Can be configured as a port when CS2 is not used.
Can be configured as a port when CS0L is not used.
PB3
100
Chip select 2 output (“L” active)
Can be configured as a port when RAS0 is not used.
PB1
CS0H
Can be configured as a port when CS1 is not used.
Can be configured as a port when CLK is not used.
PB0
CS0L
Chip select 1 output (“L” active)
Can be configured as a port when CS3 and EOP1 are not used.
F
EOP1
7
Chip select 0 output (“L” active)
Chip select 3 output (“L” active)
PA3
8
Description
PB4
EOP2
F
Can be configured as a port when RAS1 and EOP2 are not
used.
DMAC EOP output (ch. 2)
This function is available when DMAC EOP output is enabled.
*1: FPT-100P-M05
*2: FPT-100P-M06
(Continued)
7
MB91101/MB91101A
Pin no.
LQFP*1
QFP*2
Pin name
Circuit
type
CASL output for DRAM bank 1
Refer to the DRAM interface for details.
CS1L
PB5
1
4
Can be configured as a port when CS1L and DREQ2 are not used.
F
DREQ2
5
PB6
F
3
6
Can be configured as a port when CS1H and DACK2 are not used.
External transfer request acknowledge output pin for DMAC (ch. 2)
This function is available when transfer request output for DMAC is
enabled.
DACK2
DW1
External transfer request input pin for DMA
This pin is used for input when external trigger is selected to cause
DMAC operation, and it is necessary to disable output for other
functions from this pin unless such output is made intentionally.
CASH output for DRAM bank 1
Refer to the DRAM interface for details.
CS1H
2
Description
F
PB7
WE output for DRAM bank 1 (“L” active)
Refer to the DRAM interface for details.
Can be configured as a port when DW1 is not used.
16 to 18
19 to 21
MD0 to
MD2
G
Mode pins 0 to 2
MCU basic operation mode is set by these pins.
Directly connect these pins with VCC or VSS for use.
92
95
X0
A
Clock (oscillator) input
91
94
X1
A
Clock (oscillator) output
14
17
RST
B
External reset input
13
16
HST
H
Hardware standby input (“L” active)
12
15
NMI
H
NMI (non-maskable interrupt pin) input (“L” active)
F
External interrupt request input pins
These pins are used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from
these pins unless such output is made intentionally.
95,
94
89
98,
97
INT0,
INT1
PE0,
PE1
Can be configured as I/O ports when INT0, INT1 are not used.
INT2
External interrupt request input pin
This pin is used for input during corresponding interrupt is enabled,
and it is necessary to disable output for other functions from this pin
unless such output is made intentionally.
92
F
SC1
Clock I/O pin for UART1
Clock output is available when clock output of UART1 is enabled.
PE2
Can be configured as the I/O port when INT2 and SC1 are not used.
This function is available when UART1 clock output is disabled.
*1: FPT-100P-M05
*2: FPT-100P-M06
(Continued)
8
MB91101/MB91101A
Pin no.
LQFP*1
QFP*2
Pin name
Circuit
type
External interrupt request input pin
This pin is used for input during corresponding interrupt is enabled,
and it is necessary to disable output for other functions from this pin
unless such output is made intentionally.
INT3
88
87,
86
91
90,
89
F
SC2
UART2 clock I/O pin
Clock output is available when UART2 clock output is enabled.
PE3
Can be configured as the I/O port when INT3 and SC2 are not used.
This function is available when UART2 clock output is disabled.
DREQ0,
DREQ1
External transfer request input pins for DMA
These pins are used for input when external trigger is selected to
cause DMAC operation, and it is necessary to disable output for
other functions from these pins unless such output is made intentionally.
F
PE4,
PE5
Can be configured as I/O ports when DREQ0, DREQ1 are not
used.
DACK0
85
84
76
Description
88
F
External transfer request acknowledge output pin for DMAC (ch. 0)
This function is available when transfer request output for DMAC is
enabled.
PE6
Can be configured as the I/O port when DACK0 is not used.
This function is available when transfer request acknowledge output for DMAC or DACK0 output is disabled.
DACK1
External transfer request acknowledge output pin for DMAC (ch. 1)
This function is available when transfer request output for DMAC is
enabled.
87
F
PE7
Can be configured as the I/O port when DACK1 is not used.
This function is available when transfer request output for DMAC or
DACK1 output is disabled.
SI0
UART0 data input pin
This pin is used for input during UART0 is in input operation, and it
is necessary to disable output for other functions from this pin unless such output is made intentionally.
79
F
TRG0
PWM timer external trigger input pin
This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.
PF0
Can be configured as the I/O port when SI0 and TRG0 are not used.
*1: FPT-100P-M05
*2: FPT-100P-M06
(Continued)
9
MB91101/MB91101A
Pin no.
1
LQFP*
QFP*
2
Pin name
Circuit
type
UART0 data output pin
This function is available when UART0 data output is enabled.
SO0
TRG1
77
78
79
80
81
80
81
F
PWM timer external trigger input pin
This function is available when serial data output of PF1, UART0
are disabled.
PF1
Can be configured as the I/O port when SO0 and TRG1 are not
used.
This function is available when serial data output of UART0 is disabled.
SC0
UART0 clock I/O pin
Clock output is available when UART0 clock output is enabled.
OCPA3
F
PWM timer output pin
This function is available when PWM timer output is enabled.
PF2
Can be configured as the I/O port when SC0 and OCPA3 are not
used.
This function is available when UART0 clock output is disabled.
SI1
UART1 data input pin
This pin is used for input during UART1 is in input operation, and it
is necessary to disable output for other functions from this pin unless such output is made intentionally.
82
83
Description
F
TRG2
PWM timer external trigger input pin
This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.
PF3
Can be configured as the I/O port when SI1 and TRG2 are not used.
SO1
UART1 data output pin
This function is available when UART1 data output is enabled.
TRG3
F
PWM timer external trigger input pin
This function is available when PF4, UART1 data outputs are disabled.
PF4
Can be configured as the I/O port when SO1 and TRG3 are not
used.
This function is available when UART1 data output is disabled.
SI2
UART2 data input pin
This pin is used for input during UART2 is in input operation, and it
is necessary to disable output for other functions from this pin unless such output is made intentionally.
84
F
OCPA1
PF5
PWM timer output pin
This function is available when PWM timer output is enabled.
Can be configured as the I/O port when SI2 and OCPA1 are not
used.
*1: FPT-100P-M05
*2: FPT-100P-M06
(Continued)
10
MB91101/MB91101A
(Continued)
Pin no.
LQFP*1
QFP*2
Pin name
Circuit
type
UART2 data output pin
This function is available when UART2 data output is enabled.
SO2
82
85
OCPA2
F
PWM timer output pin
This function is available when PWM timer output is enabled.
Can be configured as the I/O port when SO2 and OCPA2 are
not used.
This function is available when UART2 data output is disabled.
PF6
83
Description
OCPA0
PWM timer output pin
This function is available when PWM timer output is enabled.
PF7
Can be configured as the I/O port when OCPA0 and ATG are
not used.
This function is available when PWM timer output is disabled.
86
F
External trigger input pin for A/D converter
This pin is used for input when external trigger is selected to
cause A/D converter operation, and it is necessary to disable
output for other functions from this pin unless such output is
made intentionally.
ATG
72 to 75
75 to 78
AN0 to AN3
D
Analog input pins of A/D converter
69
72
AVCC
—
Power supply pin (VCC) for A/D converter
70
73
AVRH
—
Reference voltage input (high) for A/D converter
Make sure to turn on and off this pin with potential of AVRH or
more applied to AVCC.
71
74
AVSS / AVRL
—
Power supply pin (VSS) for A/D converter and reference voltage
input pin (low)
43,
93
46,
96
VCC5
—
5 V power supply pin (VCC) for digital circuit
Always two pins must be connected to the power supply (connect to 3 V power supply when operating at 3 V).
4
7
VCC3
—
Bypass capacitor pin for internal capacitor.
Also connect this pin to 3 V power supply when operating at
3 V.
15,
40,
65,
90
18,
43,
68,
93
VSS
—
Earth level (VSS) for digital circuit
*1: FPT-100P-M05
*2: FPT-100P-M06
Note: In most of the above pins, I/O ports and resource I/O are multiplexed, e.g. P82 and BRQ. In case of conflict
between output of I/O ports and resource I/O, priority is always given to the output of resource I/O.
11
MB91101/MB91101A
■ DRAM CONTROL PIN
Pin name
12
Data bus 16-bit mode
2CAS/1WR mode
1CAS/2WR mode
Data bus 8-bit mode
—
RAS0
Area 4 RAS
Area 4 RAS
Area 4 RAS
RAS1
Area 5 RAS
Area 5 RAS
Area 5 RAS
CS0L
Area 4 CASL
Area 4 CAS
Area 4 CAS
CS0H
Area 4 CASH
Area 4 WEL
Area 4 CAS
CS1L
Area 5 CASL
Area 5 CAS
Area 5 CAS
CS1H
Area 5 CASH
Area 5 WEL
Area 5 CAS
DW0
Area 4 WE
Area 4 WEH
Area 4 WE
DW1
Area 5 WE
Area 5 WEH
Area 5 WE
Remarks
Correspondence of “L”,
“H” to lower address 1
bit (A0) in data bus 16bit mode
“L”: “0”
“H”: “1”
CASL:CAS which A0
corresponds to “0” area
CASH:CAS which A0
corresponds to “1” area
WEL: WE which A0 corresponds to “0” area
WEH:WE which A0 corresponds to “1” area
MB91101/MB91101A
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
Clock input
A
• Oscillation feedback resistance 1 MΩ
approx.
With standby control
X0
Standby control signal
• CMOS level
Hysteresis input
Without standby control
With pull-up resistance
VCC
B
P-ch
P-ch
R
N-ch
VSS
Digital input
• CMOS level I/O
With standby control
C
R
P-ch
Digital output
N-ch
Digital output
Digital input
Standby control signal
• Analog input
D
R
P-ch
Digital output
N-ch
Digital output
Analog input
(Continued)
13
MB91101/MB91101A
(Continued)
Type
F
Circuit
R
Remarks
P-ch
Digital output
N-ch
Digital output
• CMOS level output
• CMOS level
Hysteresis input
With standby control
Digital input
Standby control signal
• CMOS level input
Without standby control
P-ch
G
R
N-ch
Digital input
• CMOS level
Hysteresis input
Without standby control
P-ch
H
R
N-ch
Digital input
• CMOS level output
P-ch
Digital output
N-ch
Digital output
L
14
MB91101/MB91101A
■ HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over
rating across VCC and VSS may cause latchup.
This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.
Take care that the analog power supply (AVCC , AVRH) and the analog input do not exceed the digital power
supply (VCC) when the analog power supply turned on or off.
2. Treatment of Unused Pins
Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.
3. External Reset Input
It takes at least 5 machine cycle to input “L” level to the RST pin and to ensure inner reset operation properly.
4. Remarks for External Clock Operation
When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at
“H” output in stop mode).
And it can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than.
• Using an external clock
X0
X1
MB91101/MB91101A
Using an external clock (normal)
Note: Stop mode (oscillation stop mode) can not be used.
X0
Open
X1
MB91101/MB91101A
Using an external clock (can be used at 12.5 MHz and less than.)
(5 V power supply only)
5. Power Supply Pins
When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside of
the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to
prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to
observe the total output current standard, connect all VCC and VSS pins to the power supply or GND.
It is preferred to connect VCC and VSS of the MB91101and MB91101A to power supply with minimal impedance
possible.
It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between VCC and
VSS at a position as close as possible to the MB91101 and MB91101A.
15
MB91101/MB91101A
The MB91101 and MB91101A have an internal regulator. When using with 5 V power supply, supply 5 V to VCC5
pin and make sure to connect about 0.1 µF bypass capacitor to VCC3 pin for regulator. And another 3 V power
supply is needed for the A/D convertor. When using with 3 V power supply, connect both VCC5 pin and VCC3 pin
to the 3 V power supply.
• Connecting to a power supply
[Using with 3 V power supply]
[Using with 5 V power supply]
3V
5V
3V
VCC5
AVCC
VCC3
AVRH
AVSS
VSS
GND
VCC5
VCC3
AVCC
About
0.1 µF
AVRH
AVSS
GND
VSS
6. Crystal Oscillator Circuit
Noises around X0 and X1 pins may cause malfunctions of the MB91101 and MB91101A. In designing the PC
board, layout X0 and X1 pins, crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as
close as possible.
It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for
stable operation.
7. Turning-on Sequence of A/D Converter Power Supply and Analog Input
Make sure to turn on the digital power supply (VCC) before turning on the A/D converter (AVCC, AVRH) and applying
voltage to analog input (AN0 to AN3).
Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been
switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies may
be turned on simultaneously.) Make sure that AVRH never exceeds AVCC when turning on/off power supplies.
8. Fluctuation of Power Supply Voltage
Warranty range for normal operation against fluctuation of power supply voltage VCC is as given in rating. However,
sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is recommended
to make every effort to stabilize the power supply voltage to IC. It is also recommended that by controlling power
supply as a reference of stabilizing, VCC ripple fluctuation (P-P value) at the commercial frequency (50 Hz to
60 Hz) should be less than 10% of the standard VCC value and the transient regulation should be less than
0.1 V/ms at instantaneous deviation like turning off the power supply.
9. Mode Setting Pins (MD0 to MD2)
Connect mode setting pins (MD0 to MD2) directly to VCC or VSS.
Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and
make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.
10. Internal DC Regulator
Internal DC regulator stops in stop mode. When the regulator stops owing to the increase of inner leakage
current (ICCH) in stop mode, malfunction caused by noise or any troubles about power supply in normal operation,
the internal 3 V power supply voltage may decrease less than the warranty range for normal operation. So when
using the internal regulator and stop mode with 5 V power supply, never fail to support externally so that 3 V
power supply voltage might not decrease. However, even in such a case, the internal regulator can be restarted
16
MB91101/MB91101A
by inputting the reset procedure. (In this case, set the reset to “L” level within the oscillation stabilizing waiting
time.)
• Using STOP mode with 5 V power supply
5V
VCC5
3.6 kΩ
VCC3
VSS
0.1 µF
approx.
6.8 kΩ
11. Pin Condition at Turning on the Power Supply
The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on
the power supply and then starting oscillation and then the operation of the internal regulator becomes stable.
So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 MHz.
Take care that the pin condition may be output condition at initial unstable condition.
(With the MB91101A, however, initalization can be achieved in less than about 42 ms after turning on the internal
power supply by maintaining the RST pin at "L" level.)
12. Source Oscillation Input at Turning on the Power Supply
At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting.
13. Hardware Stand-by at Turning on the Power Supply
When turning on the power supply with the HST pin being set to “L” level, the hardware doesn’t stand by. However
the HST pin becomes available after the reset cancellation, the HST pin must once be back to “H” level.
14. Power on Reset
Make sure to make power on reset at turning on the power supply or returning on the power supply when the
power supply voltage is below the warranty range for normal operation.
15. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self oscillating circuit evevn
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
16. Watchdog timer function
The watchdog timer supported by the FR family monitors the program that performs the reset delay operation
for a specified time. If the program hangs and the reset delay operation is not performed, the watchdog timer
resets the CPU. Therefore, once the watchdog timer is enabled, operation continues until the CPU is reset.
As an exception, a reset delay automatically occurs if the CPU stops program execution.
17
MB91101/MB91101A
■ BLOCK DIAGRAM
I-bus (16 bits)
FR CPU
Bit search module
DREQ0 to
DREQ2
DACK0 to
DACK2
EOP0 to
EOP2
3
3
D-bus (32 bits)
RAM (2 Kbytes)
Instruction cache (1 Kbyte)
Bus converter
(Harvard↔Princeton)
DMA controller (DMAC)
(8 ch.)
3
Bus converter (32 bits↔16 bits)
16
25
X0
X1
RST
HST
Clock control unit
(Watchdog timer)
2
Bus controller
6
Interrupt control unit
C-bus (32 bits)
AN0 to AN3
AVCC
AVSS /AVRL
AVRH
ATG
4
4
10-bit A/D converter
(4 ch.)
RAS0
RAS1
CS0L
CS0H
CS1L
CS1H
DW0
DW1
DRAM controller
Reload timer (3 ch.)
R-bus (16 bits)
INT0 to INT3
NMI
D16 to D31
A00 to A24
RD
WR0, WR1
RDY
CLK
CS0 to CS5
BRQ
BGRNT
Port 0 to port B
Port
Other pins
UART (3 ch.)
(Baud rate timer)
3
3
MD0 to MD2, P20 to P27, P60 to P67,
P80 to P82, P85, PA1 to PA6,
PB0 to PB7, PE0 to PE7, PF0 to PF7,
VCC3, VCC5, VSS
PWM timer (4 ch.)
4
4
SI0 to SI2
SO0 to SO2
SC0 to SC2
OCPA0 to OCPA3
TRG0 to TRG3
Note: Pins are display for functions (Actually some pins are multiplexer).
When using REALOS, time control should be done by using external interrupt or inner timer.
18
MB91101/MB91101A
■ CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory
space.
• Memory space
Address
External ROM/external bus mode
0000 0000H
I/O area
Direct addressing area
0000 0400H
See “■ I/O MAP”
I/O area
0000 0800H
Access inhibited
0000 1000H
Embedded RAM
0000 1800H
Access inhibited
0001 0000H
External area
FFFF FFFFH
• Direct addressing area
The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an
address can be specified in a direct operand of a code.
Direct areas consists of the following areas dependent on accessible data sizes.
Byte data access:
000H to 0FFH
Half word data access: 000H to 1FFH
Word data access:
000H to 3FFH
19
MB91101/MB91101A
2. Registers
The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose
registers on memory.
• Dedicated registers
Program counter (PC):
32-bit length, indicates the location of the instruction to be executed.
Program status (PS):
32-bit length, register for storing register pointer or condition codes
Table base register (TBR): Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap)
processing.
Return pointer (RP):
Holds address to resume operation after returning from a subroutine.
System stack pointer (SSP): Indicates system stack space.
User's stack pointer (USP): Indicates user’s stack space.
Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division
Initial value
32 bits
PC
Program counter
PS
Program status
Indeterminate
XXXX XXXXH
Table base register
000F FC00H
Return pointer
XXXX XXXXH
SSP
System stack pointer
0000 0000 H
USP
User’s stack pointer
XXXX XXXXH
Indeterminate
MDH
Multiplication/division result
register
XXXX XXXXH
Indeterminate
Indeterminate
TBR
RP
MDL
Indeterminate
XXXX XXXXH
• Program status (PS)
The PS register is for holding program status and consists of a condition code register (CCR), a system condition
code register (SCR) and a interrupt level mask register (ILM).
31 to 21 20
PS
—
19
18
16 15 to 11 10
ILM4 ILM3 ILM2 ILM1 ILM0
ILM
20
17
—
D1
9
8
7
6
5
4
3
2
1
0
D0
T
—
—
S
I
N
Z
V
C
SCR
CCR
MB91101/MB91101A
• Condition code register (CCR)
S-flag:
I-flag:
N-flag:
Z-flag:
V-flag:
Specifies a stack pointer used as R15.
Controls user interrupt request enable/disable.
Indicates sign bit when division result is assumed to be in the 2’s complement format.
Indicates whether or not the result of division was “0”.
Assumes the operand used in calculation in the 2’s complement format and indicates whether or not
overflow has occurred.
C-flag: Indicates if a carry or borrow from the MSB has occurred.
• System condition code register (SCR)
T-flag: Specifies whether or not to enable step trace trap.
• Interrupt level mask register (ILM)
ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a
level mask. When an interrupt request issued to the CPU is higher than the level held by ILM,
the interrupt request is accepted.
ILM4
ILM3
ILM2
ILM1
ILM0
Interrupt level
High-low
0
0
0
0
0
0
High
:
:
0
1
0
:
:
0
0
:
:
1
1
1
15
:
:
1
1
31
Low
21
MB91101/MB91101A
■ GENERAL-PURPOSE REGISTERS
R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator
and a memory access pointer (field for indicating address).
• Register bank structure
32 bits
Initial value
XXXX
R0
XXXXH
:
:
:
:
:
:
:
:
R1
:
:
R12
R13
AC (accumulator)
R14
FP (frame pointer)
XXXX
XXXXH
R15
SP (stack pointer)
0000
0000H
Of the above 16 registers, following registers have special functions. To support the special functions, part of
the instruction set has been sophisticated to have enhanced functions.
R13: Virtual accumulator (AC)
R14: Frame pointer (FP)
R15: Stack pointer (SP)
Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000H (SSP value).
22
MB91101/MB91101A
■ SETTING MODE
1. Pin
• Mode setting pins and modes
Mode setting
pins
Mode name
Reset vector
access area
External data
bus width
MD2 MD1 MD0
Bus mode
0
0
0
External vector mode 0
External
8 bits
0
0
1
External vector mode 1
External
16 bits
0
1
0
—
—
—
0
1
1
Internal vector mode
Internal
(Mode register)
1
—
—
—
—
—
External ROM/external bus
mode
Inhibited
Single-chip mode*
Inhibited
*: The MB91101 and MB91101A do not support single-chip mode.
2. Registers
• Mode setting registers (MODR) and modes
Address
0000 07FFH
M1
M0
*
*
*
*
*
*
Initial value
Access
XXXX XXXXB
W
Bus mode setting bit
W :Write only
X :Indeterminate
* :Always write “0” except for M1 and M0.
• Bus mode setting bits and functions
M1
M0
Functions
0
0
Single-chip mode
0
1
Internal ROM/external bus mode
1
0
External ROM/external bus mode
1
1
—
Note
Inhibited
Note: Because of without internal ROM, the MB91101 and MB91101A allow “10B” setting value only.
23
MB91101/MB91101A
■ I/O MAP
Address
Abbreviation
Register name
0000H
0001H
Initial value
R/W
XXXXXXXXB
R/W
XXXXXXXXB
(Reserved)
PDR2
Port 2 data register
0002H
to
0004H
0005H
Read/write
(Reserved)
PDR6
Port 6 data register
0006H
(Reserved)
0007H
0008H
PDRB
Port B data register
R/W
XXXXXXXXB
0009H
PDRA
Port A data register
R/W
_ XXXXXX _B
R/W
_ _ X _ _ XXXB
000AH
000BH
(Reserved)
PDR8
Port 8 data register
000CH
to
0011H
(Reserved)
0012H
PDRE
Port E data register
R/W
XXXXXXXXB
0013H
PDRF
Port F data register
R/W
XXXXXXXXB
0014H
to
001BH
(Reserved)
001CH
SSR0
Serial status register 0
R/W
0 0 0 0 1 _ 0 0B
001DH
SIDR0/SODR0
Serial input register 0/serial output register 0
R/W
XXXXXXXXB
001EH
SCR0
Serial control register 0
R/W
0 0 0 0 0 1 0 0B
001FH
SMR0
Serial mode register 0
R/W
0 0 _ _ 0 _ 0 0B
0020H
SSR1
Serial status register 1
R/W
0 0 0 0 1 _ 0 0B
0021H
SIDR1/SODR1
Serial input register 1/serial output register 1
R/W
XXXXXXXXB
0022H
SCR1
Serial control register 1
R/W
0 0 0 0 0 1 0 0B
0023H
SMR2
Serial mode register 1
R/W
0 0 _ _ 0 _ 0 0B
0024H
SSR2
Serial status register 2
R/W
0 0 0 0 1 _ 0 0B
0025H
SIDR2/SODR2
Serial input register 2/serial output register 2
R/W
XXXXXXXXB
0026H
SCR2
Serial control register 2
R/W
0 0 0 0 0 1 0 0B
0027H
SMR2
Serial mode register 2
R/W
0 0 _ _ 0 _ 0 0B
(Continued)
24
MB91101/MB91101A
Address
0028H
0029H
002AH
002BH
Abbreviation
Register name
TMRLR0
16-bit reload register ch. 0
W
TMR0
16-bit timer register ch. 0
R
002CH
002FH
0030H
0031H
0032H
0033H
TMCSR0
16-bit reload timer control status register
ch. 0
TMRLR1
16-bit reload register ch. 1
W
TMR1
16-bit timer register ch. 1
R
0034H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
16-bit reload timer control status register
ch. 1
ADCR
A/D converter data register
ADCS
A/D converter control status register
TMRLR2
16-bit reload register ch. 2
W
TMR2
16-bit timer register ch. 2
R
0044H
to
0077H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
_ _ _ _ 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R
R/W
_ _ _ _ 0 0 0 0B
0 0 0 0 0 0 0 0B
_ _ _ _ _ _ XXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Reserved)
0041H
0043H
R/W
TMCSR1
0040H
0042H
XXXXXXXXB
(Reserved)
0035H
0036H
Initial value
(Reserved)
002DH
002EH
Read/write
TMCSR2
16-bit reload timer control status register
ch. 2
R/W
_ _ _ _ 0 0 0 0B
0 0 0 0 0 0 0 0B
(Reserved)
(Continued)
25
MB91101/MB91101A
Address
0078H
0079H
Abbreviation
UTIM0/UTIMR0
Register name
U-TIMER register ch. 0/reload register ch. 0
007AH
007BH
007CH
007DH
0080H
0081H
UTIMC0
U-TIMER control register ch. 0
R/W
UTIM1/UTIMR1
U-TIMER register ch. 1/reload register ch. 1
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 _ _ 0 0 0 0 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(Reserved)
UTIMC1
U-TIMER control register ch. 1
R/W
UTIM2/UTIMR2
U-TIMER register ch. 2/reload register ch. 2
R/W
0082H
0083H
R/W
Initial value
(Reserved)
007EH
007FH
Read/write
0 _ _ 0 0 0 0 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(Reserved)
UTIMC2
U-TIMER control register ch. 2
0084H
to
0093H
R/W
0 _ _ 0 0 0 0 1B
(Reserved)
0094H
EIRR
External interrupt cause register
R/W
0 0 0 0 0 0 0 0B
0095H
ENIR
Interrupt enable register
R/W
0 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
0096H
to
0098H
0099H
(Reserved)
ELVR
009AH
to
00D1H
External interrupt request level setting register
(Reserved)
00D2H
DDRE
Port E data direction register
W
0 0 0 0 0 0 0 0B
00D3H
DDRF
Port F data direction register
W
0 0 0 0 0 0 0 0B
00D4H
to
00DBH
00DCH
00DDH
(Reserved)
GCN1
00DEH
00DFH
General control register 1
R/W
0 0 1 1 0 0 1 0B
0 0 0 1 0 0 0 0B
(Reserved)
GCN2
General control register 2
R/W
0 0 0 0 0 0 0 0B
(Continued)
26
MB91101/MB91101A
Address
00E0H
Abbreviation
Register name
Read/write
Initial value
1 1 1 1 1 1 1 1B
PTMR0
Ch. 0 timer register
R
PCSR0
Ch. 0 cycle setting register
W
PDUT0
Ch. 0 duty setting register
W
00E6H
PCNH0
Ch. 0 control status register H
R/W
0 0 0 0 0 0 0 _B
00E7H
PCNL0
Ch. 0 control status register L
R/W
0 0 0 0 0 0 0 0B
PTMR1
Ch. 1 timer register
R
PCSR1
Ch. 1 cycle setting register
W
PDUT1
Ch. 1 duty setting register
W
00EEH
PCNH1
Ch. 1 control status register H
R/W
0 0 0 0 0 0 0 _B
00EFH
PCNL1
Ch. 1 control status register L
R/W
0 0 0 0 0 0 0 0B
PTMR2
Ch. 2 timer register
R
PCSR2
Ch. 2 cycle setting register
W
PDUT2
Ch. 2 duty setting register
W
00F6H
PCNH2
Ch. 2 control status register H
R/W
0 0 0 0 0 0 0 _B
00F7H
PCNL2
Ch. 2 control status register L
R/W
0 0 0 0 0 0 0 0B
PTMR3
Ch. 3 timer register
R
PCSR3
Ch. 3 cycle setting register
W
PDUT3
Ch. 3 duty setting register
W
00FEH
PCNH3
Ch. 3 control status register H
R/W
0 0 0 0 0 0 0 _B
00FFH
PCNL3
Ch. 3 control status register L
R/W
0 0 0 0 0 0 0 0B
00E1H
00E2H
00E3H
00E4H
00E5H
00E8H
00E9H
00EAH
00EBH
00ECH
00EDH
00F0H
00F1H
00F2H
00F3H
00F4H
00F5H
00F8H
00F9H
00FAH
00FBH
00FCH
00FDH
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
27
MB91101/MB91101A
Address
Abbreviation
0100H
to
01FFH
Register name
Read/write
(Reserved)
0200H
0201H
0202H
Initial value
XXXXXXXXB
DPDP
DMAC parameter descriptor pointer
R/W
XXXXXXXXB
XXXXXXXXB
0203H
X 0 0 0 0 0 0 0B
0204H
0 0 0 0 0 0 0 0B
0205H
0206H
DACSR
DMAC control status register
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0207H
0 0 0 0 0 0 0 0B
0208H
XXXXXXXXB
0209H
020AH
DATCR
DMAC pin control register
R/W
020BH
(Reserved)
03E4H
03E6H
_ _ _ _ _ _ _ _B
ICHCR
Instruction cache control register
R/W
03E7H
_ _ _ _ _ _ _ _B
(Reserved)
03F0H
03F2H
_ _ _ _ _ _ _ _B
_ _ 0 0 0 0 0 0B
03E8H
to
03EFH
03F1H
XXXX 0 0 0 0B
XXXX 0 0 0 0B
020CH
to
03E3H
03E5H
XXXX 0 0 0 0B
XXXXXXXXB
BSD0
Bit search module 0-detection data register
W
XXXXXXXXB
XXXXXXXXB
03F3H
XXXXXXXXB
03F4H
XXXXXXXXB
03F5H
03F6H
03F7H
BSD1
Bit search module 1-detection data register
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
28
MB91101/MB91101A
Address
Abbreviation
Register name
Read/write
03F8H
03F9H
03FAH
Initial value
XXXXXXXXB
BSDC
Bit search module transition-detection data
register
W
XXXXXXXXB
XXXXXXXXB
03FBH
XXXXXXXXB
03FCH
XXXXXXXXB
03FDH
03FEH
BSRR
Bit search module detection result register
R
03FFH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
0400H
ICR00
Interrupt control register 0
R/W
_ _ _ 1 1 1 1 1B
0401H
ICR01
Interrupt control register 1
R/W
_ _ _ 1 1 1 1 1B
0402H
ICR02
Interrupt control register 2
R/W
_ _ _ 1 1 1 1 1B
0403H
ICR03
Interrupt control register 3
R/W
_ _ _ 1 1 1 1 1B
0404H
ICR04
Interrupt control register 4
R/W
_ _ _ 1 1 1 1 1B
0405H
ICR05
Interrupt control register 5
R/W
_ _ _ 1 1 1 1 1B
0406H
ICR06
Interrupt control register 6
R/W
_ _ _ 1 1 1 1 1B
0407H
ICR07
Interrupt control register 7
R/W
_ _ _ 1 1 1 1 1B
0408H
ICR08
Interrupt control register 8
R/W
_ _ _ 1 1 1 1 1B
0409H
ICR09
Interrupt control register 9
R/W
_ _ _ 1 1 1 1 1B
040AH
ICR10
Interrupt control register 10
R/W
_ _ _ 1 1 1 1 1B
040BH
ICR11
Interrupt control register 11
R/W
_ _ _ 1 1 1 1 1B
040CH
ICR12
Interrupt control register 12
R/W
_ _ _ 1 1 1 1 1B
040DH
ICR13
Interrupt control register 13
R/W
_ _ _ 1 1 1 1 1B
040EH
ICR14
Interrupt control register 14
R/W
_ _ _ 1 1 1 1 1B
040FH
ICR15
Interrupt control register 15
R/W
_ _ _ 1 1 1 1 1B
0410H
ICR16
Interrupt control register 16
R/W
_ _ _ 1 1 1 1 1B
0411H
ICR17
Interrupt control register 17
R/W
_ _ _ 1 1 1 1 1B
0412H
ICR18
Interrupt control register 18
R/W
_ _ _ 1 1 1 1 1B
0413H
ICR19
Interrupt control register 19
R/W
_ _ _ 1 1 1 1 1B
0414H
ICR20
Interrupt control register 20
R/W
_ _ _ 1 1 1 1 1B
0415H
ICR21
Interrupt control register 21
R/W
_ _ _ 1 1 1 1 1B
0416H
ICR22
Interrupt control register 22
R/W
_ _ _ 1 1 1 1 1B
(Continued)
29
MB91101/MB91101A
Address
Abbreviation
Register name
Read/write
Initial value
0417H
ICR23
Interrupt control register 23
R/W
_ _ _ 1 1 1 1 1B
0418H
ICR24
Interrupt control register 24
R/W
_ _ _ 1 1 1 1 1B
0419H
ICR25
Interrupt control register 25
R/W
_ _ _ 1 1 1 1 1B
041AH
ICR26
Interrupt control register 26
R/W
_ _ _ 1 1 1 1 1B
041BH
ICR27
Interrupt control register 27
R/W
_ _ _ 1 1 1 1 1B
041CH
ICR28
Interrupt control register 28
R/W
_ _ _ 1 1 1 1 1B
041DH
ICR29
Interrupt control register 29
R/W
_ _ _ 1 1 1 1 1B
041EH
ICR30
Interrupt control register 30
R/W
_ _ _ 1 1 1 1 1B
041FH
ICR31
Interrupt control register 31
R/W
_ _ _ 1 1 1 1 1B
042FH
ICR47
Interrupt control register 47
R/W
_ _ _ 1 1 1 1 1B
0430H
DICR
Delayed interrupt control register
R/W
_ _ _ _ _ _ _ 0B
0431H
HRCL
Hold request cancel request level setting register
R/W
_ _ _ 1 1 1 1 1B
0432H
to
047FH
(Reserved)
0480H
RSRR/WTCR
Reset cause register/
watchdog peripheral control register
R/W
1 XXXX _ 0 0B
0481H
STCR
Standby control register
R/W
0 0 0 1 1 1 _ _B
0482H
PDRR
DMA controller request squelch register
R/W
_ _ _ _ 0 0 0 0B
0483H
CTBR
Timebase timer clear register
W
XXXXXXXXB
0484H
GCR
Gear control register
R/W
1 1 0 0 1 1 _ 1B
0485H
WPR
Watchdog reset occurrence postpone register
W
XXXXXXXXB
R/W
0 0 _ _ 0 _ _ _B
W
0 0 0 0 0 0 0 0B
W
0 0 0 0 0 0 0 0B
0486H
(Reserved)
0487H
0488H
PCTR
0489H
to
0600H
0601H
(Reserved)
DDR2
0602H
to
0604H
0605H
0606H
0607H
PLL control register
Port 2 data direction register
(Reserved)
DDR6
Port 6 data direction register
(Reserved)
(Continued)
30
MB91101/MB91101A
Address
Abbreviation
Register name
Read/write
Initial value
0608H
DDRB
Port B data direction register
W
0 0 0 0 0 0 0 0B
0609H
DDRA
Port A data direction register
W
_ 0 0 0 0 0 0 _B
_ _ 0 _ _ 0 0 0B
060AH
060BH
(Reserved)
DDR8
Port 8 data direction register
W
ASR1
Area select register 1
W
AMR1
Area mask register 1
W
ASR2
Area select register 2
W
AMR2
Area mask register 2
W
ASR3
Area select register 3
W
AMR3
Area mask register 3
W
ASR4
Area select register 4
W
AMR4
Area mask register 4
W
ASR5
Area select register 5
W
AMR5
Area mask register 5
W
0620H
AMD0
Area mode register 0
R/W
_ _ _ 0 0 1 1 1B
0621H
AMD1
Area mode register 1
R/W
0 _ _ 0 0 0 0 0B
0622H
AMD32
Area mode register 32
R/W
0 0 0 0 0 0 0 0B
0623H
AMD4
Area mode register 4
R/W
0 _ _ 0 0 0 0 0B
0624H
AMD5
Area mode register 5
R/W
0 _ _ 0 0 0 0 0B
0625H
DSCR
DRAM signal control register
W
0 0 0 0 0 0 0 0B
RFCR
Refresh control register
060CH
060DH
060EH
060FH
0610H
0611H
0612H
0613H
0614H
0615H
0616H
0617H
0618H
0619H
061AH
061BH
061CH
061DH
061EH
061FH
0626H
0627H
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 1 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 1 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
_ _ XXXXXXB
0 0 _ _ _ 0 0 0B
(Continued)
31
MB91101/MB91101A
(Continued)
Address
0628H
0629H
Abbreviation
EPCR0
Register name
External pin control register 0
062AH
062BH
062CH
062DH
062EH
062FH
W
Initial value
_ _ _ _ 1 1 0 0B
_ 1 1 1 1 1 1 1B
(Reserved)
EPCR1
External pin control register 1
DMCR4
DRAM control register 4
R/W
DMCR5
DRAM control register 5
R/W
0630H
to
07FDH
W
1 1 1 1 1 1 1 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 _B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 _B
(Reserved)
07FEH
LER
Little endian register
W
_ _ _ _ _ 0 0 0B
07FFH
MODR
Mode register
W
XXXXXXXXB
Note : Do not use (reserved).
32
Read/write
MB91101/MB91101A
■ INTERRUPT CAUSES, INTERRUPT VECTORS
AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt number
Interrupt level
Decimal
Hexadecimal
Register
Offset
TBR default
address
Reset
0
00
—
3FCH
000FFFFCH
Reserved for system
1
01
—
3F8H
000FFFF8H
Reserved for system
2
02
—
3F4H
000FFFF4H
Reserved for system
3
03
—
3F0H
000FFFF0H
Reserved for system
4
04
—
3ECH
000FFFECH
Reserved for system
5
05
—
3E8H
000FFFE8H
Reserved for system
6
06
—
3E4H
000FFFE4H
Reserved for system
7
07
—
3E0H
000FFFE0H
Reserved for system
8
08
—
3DCH
000FFFDCH
Reserved for system
9
09
—
3D8H
000FFFD8H
Reserved for system
10
0A
—
3D4H
000FFFD4H
Reserved for system
11
0B
—
3D0H
000FFFD0H
Reserved for system
12
0C
—
3CCH
000FFFCCH
Reserved for system
13
0D
—
3C8H
000FFFC8H
Exception for undefined instruction
14
0E
—
3C4H
000FFFC4H
NMI request
15
0F
FH fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
UART0 receive complete
20
14
ICR04
3ACH
000FFFACH
UART1 receive complete
21
15
ICR05
3A8H
000FFFA8H
UART2 receive complete
22
16
ICR06
3A4H
000FFFA4H
UART0 transmit complete
23
17
ICR07
3A0H
000FFFA0H
UART1 transmit complete
24
18
ICR08
39CH
000FFF9CH
UART2 transmit complete
25
19
ICR09
398H
000FFF98H
DMAC0 (complete, error)
26
1A
ICR10
394H
000FFF94H
DMAC1 (complete, error)
27
1B
ICR11
390H
000FFF90H
DMAC2 (complete, error)
28
1C
ICR12
38CH
000FFF8CH
DMAC3 (complete, error)
29
1D
ICR13
388H
000FFF88H
DMAC4 (complete, error)
30
1E
ICR14
384H
000FFF84H
DMAC5 (complete, error)
31
1F
ICR15
380H
000FFF80H
Interrupt causes
(Continued)
33
MB91101/MB91101A
Interrupt number
Interrupt level
Decimal
Hexadecimal
Register
Offset
TBR default
address
DMAC6 (complete, error)
32
20
ICR16
37CH
000FFF7CH
DMAC7 (complete, error)
33
21
ICR17
378H
000FFF78H
A/D converter (successive approximation conversion type)
34
22
ICR18
374H
000FFF74H
16-bit reload timer 0
35
23
ICR19
370H
000FFF70H
16-bit reload timer 1
36
24
ICR20
36CH
000FFF6CH
16-bit reload timer 2
37
25
ICR21
368H
000FFF68H
PWM 0
38
26
ICR22
364H
000FFF64H
PWM 1
39
27
ICR23
360H
000FFF60H
PWM 2
40
28
ICR24
35CH
000FFF5CH
PWM 3
41
29
ICR25
358H
000FFF58H
U-TIMER 0
42
2A
ICR26
354H
000FFF54H
U-TIMER 1
43
2B
ICR27
350H
000FFF50H
U-TIMER 2
44
2C
ICR28
34CH
000FFF4CH
Reserved for system
45
2D
ICR29
348H
000FFF48H
Reserved for system
46
2E
ICR30
344H
000FFF44H
Reserved for system
47
2F
ICR31
340H
000FFF40H
Reserved for system
48
30
ICR32
33CH
000FFF3CH
Reserved for system
49
31
ICR33
338H
000FFF38H
Reserved for system
50
32
ICR34
334H
000FFF34H
Reserved for system
51
33
ICR35
330H
000FFF30H
Reserved for system
52
34
ICR36
32CH
000FFF2CH
Reserved for system
53
35
ICR37
328H
000FFF28H
Reserved for system
54
36
ICR38
324H
000FFF24H
Reserved for system
55
37
ICR39
320H
000FFF20H
Reserved for system
56
38
ICR40
31CH
000FFF1CH
Reserved for system
57
39
ICR41
318H
000FFF18H
Reserved for system
58
3A
ICR42
314H
000FFF14H
Reserved for system
59
3B
ICR43
310H
000FFF10H
Reserved for system
60
3C
ICR44
30CH
000FFF0CH
Reserved for system
61
3D
ICR45
308H
000FFF08H
Reserved for system
62
3E
ICR46
304H
000FFF04H
Delayed interrupt cause bit
63
3F
ICR47
300H
000FFF00H
Interrupt causes
(Continued)
34
MB91101/MB91101A
(Continued)
Interrupt number
Interrupt level
Decimal
Hexadecimal
Register
Offset
TBR default
address
Reserved for system (used in REALOS*)
64
40
—
2FCH
000FFEFCH
Reserved for system (used in REALOS*)
65
41
—
2F8H
000FFEF8H
Used in INT instructions
66
to
255
42
to
FF
—
2F4H
to
000H
000FFEF4H
to
000FFC00H
Interrupt causes
*: REALOS/FR uses interrupt number 0x40 and 0x41 for system code.
35
MB91101/MB91101A
■ PERIPHERAL RESOURCES
1. I/O Ports
There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register
(DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on
the register corresponds to an external pin. In port registers input/output register of the port configures input/
output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. Bit “0” specifies input and “1” specifies output.
• For input (DDR = “0”) setting;
PDR reading operation: reads level of corresponding external pin.
PDR writing operation: writes set value to PDR.
• For output (DDR = “1”) setting;
PDR reading operation: reads PDR value.
PDR writing operation: outputs PDR value to corresponding external pin.
• Block diagram
Resource input
0
1
Data bus
PDR read
0
PDR
(Port data register)
Resource output
1
Resource output enable
DDR
(Data direction register)
36
Pin
MB91101/MB91101A
• Port data register
Address
bit 7
bit 0
Initial value
000001H
PDR2
XXXXXXXXB
(R/W)
000005H
PDR6
XXXXXXXXB
(R/W)
00000BH
PDR8
- - X - - XXXB
(R/W)
000009H
PDRA
- XXXXXX -B
(R/W)
000008H
PDRB
XXXXXXXXB
(R/W)
000012H
PDRE
XXXXXXXXB
(R/W)
000013H
PDRF
XXXXXXXXB
(R/W)
( ) :Access
R/W :Readable and writable
X :Indeterminate
• Data direction register
Address
DDR2
Initial value
0 0 0 0 0 0 0 0B
(W)
000605H
DDR6
0 0 0 0 0 0 0 0B
(W)
00060BH
DDR8
- - 0 - - 0 0 0B
(W)
000609H
DDRA
- 0 0 0 0 0 0 -B
(W)
000608H
DDRB
0 0 0 0 0 0 0 0B
(W)
0000D2H
DDRE
0 0 0 0 0 0 0 0B
(W)
0000D3H
DDRF
0 0 0 0 0 0 0 0B
(W)
000601H
bit 7
bit 0
( ) :Access
W :Write only
– :Unused
37
MB91101/MB91101A
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.
DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system.
• 8 channels
• Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer
• Transfer all through the area
• Max 65536 of transfer cycles
• Interrupt function right after the transfer
• Selectable for address transfer increase/decrease by the software
• External transfer request input pin, external transfer request accept output pin, external transfer complete
output pin three pins for each
• Block diagram
DREQ0 to DREQ2
3
Edge/level
detection circuit
3
3
DACK0 to DACK2
3
Sequencer
EOP0 to EOP2
8
Interrupt request
5
Inner resource
Transfer request
Data buffer
Switcher
DACSR
DATCR
Mode
BLK DEC
BLK
DMACT
INC / DEC
SADR
DADR
38
Data bus
DPDP
MB91101/MB91101A
• Registers (DMAC internal registers)
Address
bit 31
00000200H
00000201H
00000202H
00000203H
bit 16
bit 0
DPDP
00000204H
00000205H
00000206H
00000207H
DACSR
00000208H
00000209H
0000020AH
0000020BH
DATCR
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
X 0 0 0 0 0 0 0B
(R/W)
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(R/W)
XXXXXXXXB
XXXX 0 0 0 0B
XXXX 0 0 0 0B
XXXX 0 0 0 0B
(R/W)
( ) :Access
R/W :Readable and writable
X :Indeterminate
• Registers (DMA descriptor)
Address
DPDP + 0H
DPDP + 0CH
DPDP + 54H
bit 31
bit 0
DMA
ch.0
Descriptor
DMA
ch.1
Descriptor
DMA
ch.7
Descriptor
39
MB91101/MB91101A
3. UART
The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication, and it has the following features.
The MB91101 and MB91101A consist of 3 channels of UART.
• Full double double buffer
• Both a synchronous (start-stop system) communication and CLK synchronous communication are available.
• Supporting multi-processor mode
• Perfect programmable baud rate
Any baud rate can be set by internal timer (refer to section “4. U-TIMER”).
• Any baud rate can be set by external clock.
• Error checking function (parity, framing and overrun)
• Transfer signal: NRZ code
• Enable DMA transfer/start by interrupt.
40
MB91101/MB91101A
• Block diagram
Control signals
Receive interrupt
(to CPU)
SC (clock)
Transmit interrupt
(to CPU)
Transmit clock
From U-TIMER
Clock select
circuit
Receive clock
From external clock
SC
SI
(receive data)
Receive control circuit
Transmit control circuit
Start bit detect
circuit
Transmit start
circuit
Receive bit counter
Transmit bit counter
Receive parity
counter
Transmit parity
counter
SO (transmit data)
Receive status
judge circuit
Receive shifter
Receive error
generate signal
for DMA
(to DMAC)
Transmit shifter
Receive
complete
Transmit
start
SODR
SIDR
R-bus
MD1
MD0
SMR
register
SCR
register
CS0
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signals
41
MB91101/MB91101A
• Register configuration
Address
bit 15
Initial value
0000001EH
SCR0
0 000010 0B
(R/W)
00000022H
SCR1
0 000010 0B
(R/W)
00000026H
SCR2
0 000010 0B
(R/W)
0000001FH
SMR0
0 0 - - 0 - 0 0B
(R/W)
00000023H
SMR1
0 0 - - 0 - 0 0B
(R/W)
00000027H
SMR2
0 0 - - 0 - 0 0B
(R/W)
0000001CH
SSR0
0 0 0 0 1 - 0 0B
(R/W)
00000020H
SSR1
0 0 0 0 1 - 0 0B
(R/W)
00000024H
SSR2
0 0 0 0 1 - 0 0B
(R/W)
XXXXXXXXB
(R/W)
XXXXXXXXB
(R/W)
XXXXXXXXB
(R/W)
0000001DH
SIDR0/SODR0
00000021H
SIDR1/SIDR1
00000002H
()
R/W
–
X
42
bit 0
bit 8
:Access
:Readable and writable
:Unused
:Indeterminate
SIDR2/SIDR2
MB91101/MB91101A
4. U-TIMER (16-bit Timer for UART Baud Rate Generation)
The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and
reload value of U-TIMER allows flexible setting of baud rate.
The U-TIMER operates as an interval timer by using interrupt issued on counter underflow.
The MB91101 and MB91101A have 3 channel U-TIMER embedded on the chip. An interval of up to 216 × φ can
be counted.
• Block diagram
bit 15
bit 0
UTIMR (reload register)
Load
bit 15
bit 0
UTIM ( U-TIMER register)
Underflow
Clock
φ
(Peripheral clock)
Control
f.f.
To UART
• Register configuration
Address
bit 15
00000078H
00000079H
0000007CH
0000007DH
00000080H
00000081H
bit 0
UTIM0/UTIMR0
UTIM1/UTIMR1
UTIM2/UTIMR2
Initial value
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(R/W)
(R/W)
(R/W)
0000007BH
UTIMC0
0 - - 0 0 0 0 1B
(R/W)
0000007FH
UTIMC1
0 - - 0 0 0 0 1B
(R/W)
00000083H
UTIMC2
0 - - 0 0 0 0 1B
(R/W)
( ) :Access
R/W :Readable and writable
–
:Unused
43
MB91101/MB91101A
5. PWM Timer
The PWM timer can output high accurate PWM waves efficiently.
The MB91101 and MB91101A have inner 4-channel PWM timers, and has the following features.
• Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16-bit
compare resister with a buffer for duty setting, and a pin controller.
• The count clock of a 16-bit down counter can be selected from the following four inner clocks.
Inner clock φ, φ/4, φ/16, φ/64
• The counter value can be initialized “FFFFH” by the resetting or the counter borrow.
• PWM output (each channel)
• Resister description
• Block diagram (general construction)
16-bit reload timer
ch.0
16-bit reload timer
ch.1
General control
register 2
General control
register 1
(cause selection)
4
4
External TRG0 to TRG3
44
TRG input
PWM timer ch.0
PWM0
TRG input
PWM timer ch.1
PWM1
TRG input
PWM timer ch.2
PWM2
TRG input
PWM timer ch.3
PWM3
MB91101/MB91101A
• Block diagram (for one channel)
PDUT
PCSR
Prescaler
1/1
1/4
1 / 16
1 / 64
cmp
ck
Load
16-bit down counter
Start
Borrow
PPG mask
S
Peripheral clock
Q
PWM output
R
Enable
TRG input
Edge detect
Interrupt
selection
Reverse bit
IRQ
Soft trigger
45
MB91101/MB91101A
• Register configuration
Address
bit 8
bit 15
000000DCH
000000DDH
GCN1
000000DFH
GCN2
Initial value
0 0 1 1 0 0 1 0B
0 0 0 1 0 0 0 0B
(R/W)
0 0 0 0 0 0 0 0B
(R/W)
000000E0H
000000E1H
PTMR0
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
(R)
000000E2H
000000E3H
PCSR0
XXXXXXXXB
XXXXXXXXB
(W)
000000E4H
000000E5H
PDUT0
XXXXXXXXB
XXXXXXXXB
(W)
0000000-B
(R/W)
0 0 0 0 0 0 0 0B
(R/W)
000000E6H
PCNH0
000000E7H
PCNL0
000000E8H
000000E9H
PTMR1
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
(R)
000000EAH
000000EBH
PCSR1
XXXXXXXXB
XXXXXXXXB
(W)
000000ECH
000000EDH
PDUT1
XXXXXXXXB
XXXXXXXXB
(W)
0000000 -B
(R/W)
0 0 0 0 0 0 0 0B
(R/W)
000000EEH
PCNH1
000000EFH
PCNL1
000000F0H
000000F1H
PTMR2
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
(R)
000000F2H
000000F3H
PCSR2
XXXXXXXXB
XXXXXXXXB
(W)
000000F4H
000000F5H
PDUT2
XXXXXXXXB
XXXXXXXXB
(W)
0000000-B
(R/W)
0 0 0 0 0 0 0 0B
(R/W)
000000F6H
PCNH2
000000F7H
PCNL2
000000F8H
000000F9H
PTMR3
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
(R)
000000FAH
000000FBH
PCSR3
XXXXXXXXB
XXXXXXXXB
(W)
000000FCH
000000FDH
PDUT3
XXXXXXXXB
XXXXXXXXB
(W)
0000000-B
(R/W)
0 0 0 0 0 0 0 0B
(R/W)
000000FEH
PCNH3
000000FFH
()
R/W
R
W
–
X
46
bit 0
:Access
:Readable and writable
:Read only
:Write only
:Unused
:Indeterminate
PCNL3
MB91101/MB91101A
6. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal
count clock and control registers.
Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock).
The DMA transfer can be started by the interruption.
The MB91101 and MB91101A consist of 3 channels of the 16-bit reload timer.
• Block diagram
16
16-bit reload register
8
Reload
RELD
16
OUTE
16-bit down counter UF
OUTL
2
OUT
CTL.
R-bus
GATE
INTE
2
IRQ
UF
CSL1
Clock selector
CNTE
CSL0
TRG
2
Retrigger
IN CTL.
EXCK
φ φ φ
– – –
21 2 3 2 5
PWM (ch.0, ch.1)
A/D (ch.2)
3
Prescaler
clear
MOD2
MOD1
Internal clock
MOD0
3
47
MB91101/MB91101A
• Register configuration
Address
bit 15
0000002EH
0000002FH
00000036H
00000037H
00000042H
00000043H
0000002AH
0000002BH
TMCSR0
TMCSR1
TMCSR2
TMR0
00000032H
00000033H
TMR1
0000003EH
0000003FH
TMR2
00000028H
00000029H
TMRLR0
00000030H
00000031H
TMRLR1
0000003CH
0000003DH
TMRLR2
()
R/W
R
W
–
X
48
bit 0
:Access
:Readable and writable
:Read only
:Write only
:Unused
:Indeterminate
Initial value
- - - - 0 0 0 0B
0 0 0 0 0 0 0 0B
- - - - 0 0 0 0B
0 0 0 0 0 0 0 0B
- - - - 0 0 0 0B
0 0 0 0 0 0 0 0B
(R/W)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(R)
(R/W)
(R/W)
(R)
(R)
(W)
(W)
(W)
MB91101/MB91101A
7. Bit Search Module
The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and
returns locations of the transitions.
• Block diagram
Input latch
Detection
mode
D-bus
Address
decoder
Single-detection data recovery
Bit search circuit
Search result
• Register configuration
Address
bit 31
bit 16
000003F0H
000003F1H
000003F2H
000003F3H
BSD0
000003F4H
000003F5H
000003F6H
000003F7H
BSD1
000003F8H
000003F9H
000003FAH
000003FBH
BSDC
000003FCH
000003FEH
000003FDH
000003FFH
BSRR
()
R/W
R
W
X
bit 0
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(W)
(R/W)
(W)
(R)
:Access
:Readable and writable
:Read only
:Write only
:Indeterminate
49
MB91101/MB91101A
8. 10-bit A/D Converter (Successive Approximation Conversion Type)
The A/D converter is the module which converts an analog input voltage to a digital value, and it has following
features.
• Minimum converting time: 5.6 µs/ch. (system clock: 25 MHz)
• Inner sample and hold circuit
• Resolution: 10 bits
• Analog input can be selected from 4 channels by program.
Single convert mode: 1 channel is selected and converted.
Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable.
Continuous convert mode: Converting the specified channel repeatedly.
Stop convert mode: After converting one channel then stop and wait till next activation synchronizing at
the beginning of conversion can be performed.
• DMA transfer operation is available by interruption.
• Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reload timer
(rising edge).
• Block diagram
AVCC
AVR
AVSS
Internal voltage generator
MPX
AN0
AN2
Successive approximation
register
Input circuit
AN1
Comparator
AN3
Decoder
R-bus
Sample & hold circuit
Data register (ADCR)
A/D control register (ADCS)
Trigger start
ATG
Timer start
TIM2
(Output signal of 16-bit reload timer ch.2)
φ
(Peripheral clock)
50
Operating clock
Prescaler
MB91101/MB91101A
• Register configuration
Address
bit 0
bit 15
0000003AH
0000003BH
ADCS
00000038H
00000039H
ADCR
()
R/W
R
–
X
Initial value
0 0 0 0 0 0 0B
0 0 0 0 0 0 0B
- - - - - - XXB
XXXXXXXXB
(R/W)
(R)
:Access
:Readable and writable
:Read only
:Unused
:Indeterminate
51
MB91101/MB91101A
9. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.
• Block diagram
IM *6
INT0*2
Priority judgment
OR
5
NMI
5
NMI processing
4
Level judgment
ICR00
RI00 *7
•
•
•
RI47 *
6
•
•
•
Vector judgment
6
HLDCAN*3
VCT5 to
VCT0*5
ICR47
7
(DLYIRQ)
•
•
Level
vector
generation
HLDREQ
cancel
request
LEVEL4 to
LEVEL0*4
DLYI*1
R-bus
*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11.
Delayed Interrupt Module” for detail).
*2: INT0 is a wake-up signal to clock control block in the sleep or stop status.
*3: HLDCAN is a bus release request signal for bus masters other than CPU.
*4: LEVEL4 to LEVEL0 are interrupt level outputs.
*5: VCT5 to VCT0 are interrupt vector outputs.
*6: IM is an interrupt mask signal.
*7: RI00 to RI47 are interrupt request signals.
52
MB91101/MB91101A
• Register configuration
Address
bit 7
bit 0
Initial value
Address
bit 0
bit 7
Initial value
00000400H
ICR00
- - - 11111 B (R/W)
00000411H
ICR17
- - - 11111 B (R/W)
00000401H
ICR01
- - - 11111 B (R/W)
00000412H
ICR18
- - - 11111 B (R/W)
00000402H
ICR02
- - - 11111 B (R/W)
00000413H
ICR19
- - - 11111 B (R/W)
00000403H
ICR03
- - - 11111 B (R/W)
00000414H
ICR20
- - - 11111 B (R/W)
00000404H
ICR04
- - - 11111 B (R/W)
00000415H
ICR21
- - - 11111 B (R/W)
00000405H
ICR05
- - - 11111 B (R/W)
00000416H
ICR22
- - - 11111 B (R/W)
00000406H
ICR06
- - - 11111 B (R/W)
00000417H
ICR23
- - - 11111 B (R/W)
00000407H
ICR07
- - - 11111 B (R/W)
00000418H
ICR24
- - - 11111 B (R/W)
00000408H
ICR08
- - - 11111 B (R/W)
00000419H
ICR25
- - - 11111 B (R/W)
00000409H
ICR09
- - - 11111 B (R/W)
0000041AH
ICR26
- - - 11111 B (R/W)
0000040AH
ICR10
- - - 11111 B (R/W)
0000041BH
ICR27
- - - 11111 B (R/W)
0000040BH
ICR11
- - - 11111 B (R/W)
0000041CH
ICR28
- - - 11111 B (R/W)
0000040CH
ICR12
- - - 11111 B (R/W)
0000041DH
ICR29
- - - 11111 B (R/W)
0000040DH
ICR13
- - - 11111 B (R/W)
0000041EH
ICR30
- - - 11111 B (R/W)
0000040EH
ICR14
- - - 11111 B (R/W)
0000041FH
ICR31
- - - 11111 B (R/W)
0000040FH
ICR15
- - - 11111 B (R/W)
0000042FH
ICR47
- - - 11111 B (R/W)
00000410H
ICR16
- - - 11111 B (R/W)
00000431H
HRCL
- - - 11111 B (R/W)
00000430H
DICR
- - - - - - - 0 B (R/W)
()
:Access
R/W :Readable and writable
–
:Unused
53
MB91101/MB91101A
10. External Interrupt/NMI Control Block
The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to
INT3 pins.
Detecting levels can be selected from “H”, “L”, rising edge and falling edge (not for NMI pin).
• Block diagram
8
Interrupt enable register
9
5
Gate
R-bus
Interrupt
request
Cause F/F
Edge detection circuit
INT0 to INT3
NMI
8
Interrupt cause register
8
Request level setting register
• Register configuration
Address
bit 15
bit 8
00000095H
00000094H
ENIR
()
:Access
R/W :Readable and writable
Initial value
00000000 B (R/W)
00000000 B (R/W)
EIRR
00000099H
54
bit 0
ELVR
00000000 B (R/W)
MB91101/MB91101A
11. Delayed Interrupt Module
Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed
interrupt module, an interrupt request to CPU can be generated/cancelled by the software.
Refer to the section “9. Interrupt Controller” for delayed interrupt module block diagram.
• Register configuration
Address
bit 7
00000430H
bit 0
DICR
Initial value
- - - - - - - 0B
(R/W)
( ) :Access
R/W :Readable and writable
–
:Unused
55
MB91101/MB91101A
12. Clock Generation (Low-power consumption mechanism)
The clock control block is a module which undertakes the following functions.
•
•
•
•
•
•
CPU clock generation (including gear function)
Peripheral clock generation (including gear function)
Reset generation and cause hold
Standby function (including hardware standby)
DMA request prohibit
PLL (multiplier circuit) embedded
• Block diagram
[Gear control block]
Gear control register (GCR)
X0
X1
Oscillator
circuit
PCTR register
PLL
1/2
Internal
interrupt request
Internal reset
Selection
circuit
R-bus
CPU gear
Peripheral
gear
CPU clock
Internal bus clock
External bus clock
Peripheral
DMA clock
Internal
peripheral clock
Internal clock
generation
circuit
[Stop/sleep control block]
Standby control
register (STCR)
STOP state
Status
transition
control circuit
CPU hold enable
HST pin
SLEEP state
CPU hold request
Reset
generation
F/F
[DMA prohibit circuit]
DMA
request
DMA request prohibit
register (PDRR)
[Reset cause circuit]
Power on sel
RST pin
Reset cause register (RSRR)
[Watchdog control block]
Watchdog reset generation
postpone register (WPR)
Watchdog reset
postpone register
Timebase timer clear
register (CTBR)
Timebase timer
56
Count clock
Internal reset
MB91101/MB91101A
• Register configuration
Address
00000480H
bit 15
bit 8
RSRR/WTCR
00000481H
00000482H
STCR
PDRR
00000483H
00000484H
CTBR
GCR
00000485H
00000488H
()
R/W
W
–
X
bit 0
WPR
PCTR
Initial value
1XXXX - 0 0B
(R/W)
0 0 0 1 1 1 - -B
(R/W)
- - - - 0 0 0 0B
(R/W)
XXXXXXXXB
(W)
1 1 0 0 1 1 - 1B
(R/W)
XXXXXXXXB
(W)
0 0 - - 0 - - -B
(R/W)
:Access
:Readable and writable
:Write only
:Unused
:Indeterminate
57
MB91101/MB91101A
13. External Bus Interface
The external bus interface controls the interface between the device and the external memory and also the
external I/O, and has the following features.
• 25-bit (32 Mbytes) address output
• 6 independent banks owing to the chip select function.
Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.
Total 32 Mbytes × 6 area setting is available by the address pin and the chip select pin.
• 8/16-bit bus width setting are available for every chip select area.
• Programmable automatic memory wait (Max for 7 cycles) can be inserted.
• DRAM interface support
Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F)
Single CAS DRAM
Hyper DRAM
2 banks independent control (RAS, CAS, etc. control signals)
DRAM select is available from 2CAS/1WE and 1CAS/2WE.
Hi-speed page mode supported
CBR/self refresh supported
Programmable wave form
• Unused address/data pin can be used for I/O port.
• Little endian mode supported
• Clock doubler: Internal bus 50 MHz, external bus 25 MHz
58
MB91101/MB91101A
• Block diagram
Address bus
32
A-OUT
Data bus
32
External data bus
Write buffer
Switch
Read buffer
Switch
MUX
DATA BLOCK
ADDRESS BLOCK
+1 or +2
External address bus
Inpage
Shifter
Address buffer
6
ASR
AMR
CS0 to CS5
Comparator
8
DRAM control
RAS0, RAS1
CS0L, CS1L
CS0H, CS1H
DW0, DW1
Underflow
DMCR
Refresh counter
To TBT
3
External pin control block
All blocks control
4
Registers and control
RD
WR0, WR1
BRQ
BGRNT
CLK
RDY
59
MB91101/MB91101A
• Register configuration
Address
0000060CH
0000060DH
bit 31
bit 16
bit 0
ASR1
0000060EH
0000060FH
00000610H
00000611H
AMR1
ASR2
00000612H
00000613H
00000614H
00000615H
00000616H
00000617H
00000618H
00000619H
AMR2
ASR3
AMR3
ASR4
0000061AH
0000061BH
0000061CH
0000061DH
AMR4
ASR5
0000061EH
0000061FH
00000620H
AMR5
AMD0
AMD1
00000621H
00000622H
AMD32
AMD4
00000623H
00000624H
00000625H
00000626H
00000627H
00000628H
00000629H
AMD5
DSCR
RFCR
EPCR0
0000062BH
0000062CH
0000062DH
EPCR1
DMCR4
0000062EH
0000062FH
000007FEH
000007FFH
()
R/W
W
–
X
60
:Access
:Readable and writable
:Write only
:Unused
:Indeterminate
DMCR5
LER
MODR
Initial value
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 1 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 1 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 1B
(W)
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(W)
- - - 0 0 1 1 1B
(R/W)
0 - - 0 0 0 0 0B
(R/W)
0 0 0 0 0 0 0 0B
(R/W)
0 - - 0 0 0 0 0B
(R/W)
0 - - 0 0 0 0 0B
(R/W)
0 0 0 0 0 0 0 0B
(W)
- - XXXXXXB
0 0 - - - 0 0 0B
(R/W)
- - - - 1 1 0 0B
- 1 1 1 1 1 1 1B
(W)
1 1 1 1 1 1 1 1B
(W)
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 -B
(R/W)
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 -B
(R/W)
- - - - - 0 0 0B
(W)
XXXXXXXXB
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
MB91101/MB91101A
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Symbol
Parameter
Rating
Unit
Remarks
Min
Max
VCC5
VSS – 0.3
VSS + 6.5
V
VCC3
—
—
V
VCC5
VCC3 – 0.3
VSS + 6.5
V
*1
VCC3
VSS – 0.3
VSS + 3.6
V
*1
Analog supply voltage
AVCC
VSS – 0.3
VSS + 3.6
V
*2
Analog reference voltage
AVRH
VSS – 0.3
VSS + 3.6
V
*2
Analog pin input voltage
VIA
VSS – 0.3
AVCC + 0.3
V
Input voltage
VI
VSS – 0.3
VCC5 + 0.3
V
Output voltage
VO
VSS – 0.3
VCC5 + 0.3
V
“L” level maximum output current
IOL
—
10
mA
*3
“L” level average output current
IOLAV
—
4
mA
*4
“L” level maximum total output current
ΣIOL
—
100
mA
“L” level average total output current
ΣIOLAV
—
50
mA
*5
“H” level maximum output current
IOH
—
–10
mA
*3
“H” level average output current
IOHAV
—
–4
mA
*4
“H” level maximum total output current
ΣIOH
—
–50
mA
“H” level average total output current
ΣIOHAV
—
–20
mA
Power consumption
PD
—
500
mW
Operating temperature
TA
–40
+70
°C
Storage temperature
Tstg
–55
+150
°C
At 5 V power supply
Power supply
voltage
At 3 V power supply
*5
*1: VCC5 must not be less than VSS – 0.3 V.
*2: Care must be taken that AVCC and AVRH do not exceed VCC5 + 0.3 V and VSS + 3.6 V.
Also care must be taken that AVRH does not exceed AVCC.
*3: Maximum output current is a peak current value measured at a corresponding pin.
*4: Average output current is an average current for a 100 ms period at a corresponding pin.
*5: Average total output current is an average current for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
61
MB91101/MB91101A
2. Recommended Operating Conditions
(1) At 5 V operation (4.5 V to 5.5 V)
(VSS = AVSS = 0.0 V)
Value
Symbol
Parameter
Unit
Remarks
Min
Max
VCC5
4.5
5.5
V
Normal operation
VCC5
*1
*1
V
Retaining the RAM state in
stop mode
VCC3
—
—
V
*2
Analog supply voltage
AVCC
VSS + 2.7
VSS + 3.6
V
Analog reference voltage
AVRH
VSS – 0.3
AVCC
V
Operating temperature
TA
–40
+70
°C
Smoothing capacitor
CS
0.1
1.0
µF
Power supply voltage
VCC3 pin, *3
*1: At VCC5, the RAM state holding is not warranted in stop mode.
*2: VCC3 is used for the bypass capacitor pin.
*3: Use the ceramic capacitor or the capacitor whose frequency characteristic is equivalent to that of the ceramic
capacitor.
And select the larger capacity bypass capacitor to connect to the power supply (VCC5) than CS.
(2) At 3 V operation (2.7 V to 3.6 V)
(VSS = AVSS = 0.0 V)
Value
Symbol
Parameter
Unit
Remarks
Min
Max
VCC5
2.7
3.6
V
Normal operation
VCC5
2.7
3.6
V
Retaining the RAM state in
stop mode
VCC3
2.7
3.6
V
*
Analog power supply voltage
AVCC
VSS + 2.7
VSS + 3.6
V
Analog reference voltage
AVRH
AVSS
AVCC
V
Operating temperature
TA
–40
+70
°C
Power supply voltage
*: Connect to VCC5 for the power supply pin.
• Connecting to a power supply
Using with 3 V power supply
Using with 5 V power supply
3V
5V
3V
VCC5
AVCC
AVRH
AVSS
VSS
GND
62
VCC3
VCC5
AVCC
About
0.1 µF
AVRH
AVSS
GND
VSS
VCC3
MB91101/MB91101A
VCC (V)
Normal operation warranty range (TA = -40°C to +70°C)
Net masked area are fCPP.
Power supply at 5 V
Supply voltage
5.5
4.5
3.0 V ±0.3 V
Power supply at 3 V
3.6
3.3
3.0
2.7
3.3 V ±0.3 V
0
25
Internal clock
0.625
40
50
fCP/fCPP
(MHz)
Max internal clock frequency setting
fCP/fCPP
(MHz)
fCP
50
CPU
40
fCPP
PLL system (4 multiplication)
25
Peripheral
20
Divide-by-2 system
12.5
5
0
0
10 12.5
25
50
External clock
fC
(MHz)
Source oscillating input clock
Self-oscillation
Notes: • When using PLL, the external clock must be used between 10.0 MHz and 12.5 MHz.
• PLL oscillation stabilizing period > 100 µs
• The setting of internal clock must be within above ranges.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
63
MB91101/MB91101A
3. DC Characteristics
Parameter
Symbol
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Pin name
Condition
VIH
Input pin except for hysteresis input
Value
Unit Remarks
Min
Typ
Max
—
0.65 × VCC3
—
VCC5 + 0.3
V
*
VIHS
HST, NMI,
RST,
PA1 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7
—
0.8 × VCC3
—
VCC5 + 0.3
V
Hysteresis
input *
VIL
Input other than
following symbols
—
VSS – 0.3
—
0.25 × VCC3
V
*
VILS
HST, NMI,
RST,
PA1 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7
—
VSS – 0.3
—
0.2 × VCC3
V
Hysteresis
input *
VCC5 = 4.5 V
IOH = – 4.0 mA
VCC5 – 0.5
—
—
“H” level output
VOH
voltage
D16 to D31,
A00 to A24,
P60 to P67,
P80 to P82,
P85,
PA1 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7
CS0, WR0
“L” level output
VOL
voltage
D16 to D31,
A00 to A24,
P60 to P67,
P80 to P82,
P85,
PA1 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7
CS0, WR0
Input leakage
current
ILI
(High-Z output
leakage current)
D16 to D31,
A00 to A23,
P80 to P82,
P85,
PA1 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7
“H” level input
voltage
“L” level input
voltage
VCC5 = VCC3 = 2.7 V
VCC5 – 0.8
IOH = – 4.0 mA
VCC5 = 4.5 V
IOL = 4.0 mA
—
V
—
—
—
0.4
V
VCC5 = VCC3 = 2.7 V
IOL = 4.0 mA
—
—
0.6
VCC5 = 5.5 V
0.45 V < VI < VCC
–5
—
+5
VCC5 = VCC3 = 3.6 V
0.45 V < VI < VCC
µA
–5
—
+5
(Continued)
64
MB91101/MB91101A
(Continued)
Parameter
Pull-up
resistance
Symbol
RPULL
ICC
Power supply
current
ICCS
ICCH
Input
capacitance
CIN
Pin name
RST
VCC5, VCC3
VCC5, VCC3
VCC5, VCC3
Except for VCC5,
VCC3, AVCC,
AVSS, VSS
Condition
Value
Min
Typ
Max
VCC5 = 5.5 V
VI = 0.45 V
25
50
100
VCC5 = VCC3 = 3.6 V
VI = 0.45 V
60
125
250
FC = 12.5 MHz
VCC5 = 5.5 V
—
75
100
FC = 12.5 MHz
VCC5 = VCC3 = 3.6 V
—
75
100
FC = 12.5 MHz
VCC5 = 5.5 V
—
40
60
FC = 12.5 MHz
VCC5 = VCC3 = 3.6 V
—
40
60
TA = +25°C
VCC5 = 5.5 V
—
10
100
TA = +25°C
VCC5 = VCC3 = 3.6 V
—
10
100
—
—
10
—
Unit
Remarks
kΩ
(4 multiplication)
mA
Operation at
50 MHz
mA Sleep mode
µA Stop mode
pF
*: VCC3 = 3.3 ±0.2 V (internal regulator output voltage) when using 5 V power supply, VCC3 = power supply voltage
when using 3 V power supply (internal regulator unused).
65
MB91101/MB91101A
4. AC Characteristics
Measurement Conditions
• VCC5 = 5.0 V ±10%
Parameter
Symbol
Value
Min
Typ
Max
Unit
“H” level input voltage
VIH
—
2.4
—
V
“L” level input voltage
VIL
—
0.8
—
V
“H” level output voltage
VOH
—
2.4
—
V
“L” level output voltage
VOL
—
0.8
—
V
Input
VCC
Remarks
Output
VIH
VOH
VIL
VOL
0.0 V
• VCC5 = VCC3 = 2.7 V to 3.6 V
Parameter
Symbol
Value
Min
Typ
Max
“H” level input voltage
VIH
—
1/2 × VCC3
—
V
“L” level input voltage
VIL
—
1/2 × VCC3
—
V
“H” level output voltage
VOH
—
1/2 × VCC3
—
V
“L” level output voltage
VOL
—
1/2 × VCC3
—
V
VCC
Input
Output
VIH
VOH
VIL
VOL
0.0 V
• Load conditions
Output pin
C = 50 pF
(VCC = 5.0V ± 10%)
66
Unit
Remarks
MB91101/MB91101A
• Load capacitance - Delay characteristics (Output delay with reference to the internal)
35
5 V Fall
Delay time (ns)
30
3 V Rise
25
20
15
5 V Rise
10
5
3 V Fall
0
0
20
40 50 60
80
100
120
Load capacitance (pF)
67
MB91101/MB91101A
(1) Clock Timing Rating
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling time
Internal operating clock
frequency
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol
Condition
Value
Min
Max
Unit
fC
X0, X1
When using PLL
10
12.5
MHz
fC
X0, X1
Self-oscillation
(divide-by-2 input)
10
25
MHz
fC
X0, X1
External clock
(divide-by-2 input)
10
25
MHz
tC
X0, X1
When using PLL
80
100
ns
tC
X0, X1
40
100
ns
—
Remarks
25
—
ns
Input to X0
only, when
using 5 V
power supply
X0, X1
10
—
ns
Input to X0,
X1
tCR,
tCF
X0, X1
—
8
ns
(tCR + tCF)
fCP
—
PWH,
PWL
X0, X1
PWH,
PWL
fCPB
fCPP
tCP
Internal operating clock
cycle time
Pin
name
tCPB
tCPP
—
—
—
—
—
—
CPU system
Bus system
Peripheral system
CPU system
Bus system
Peripheral system
0.625*1
0.625*
25*
1
25
0.625*
20
40*
40
2
50
1
MHz
2
MHz
MHz
1600*
1
ns
1600*
1
ns
1600*
1
ns
*1: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and
a 1/8 gear.
*2: Values when using the doubler and CPU operation at 50 MHz.
68
MB91101/MB91101A
• Clock timing rating measurement conditions
tC
0.8 VCC5
0.2 VCC5
PWH
PWL
tCF
tCR
69
MB91101/MB91101A
(2) Clock Output Timing
Parameter
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol Pin name
Value
Condition
Min
Max
Unit
tCYC
CLK
—
tCP
—
ns
tCYC
CLK
Using the
doubler
tCPB
—
ns
CLK ↑ → CLK ↓
tCHCL
CLK
CLK ↓ → CLK ↑
tCLCH
CLK
Cycle time
—
Remarks
*1
1/2 × tCYC – 10 1/2 × tCYC + 10
ns
*2
1/2 × tCYC – 10 1/2 × tCYC + 10
ns
*3
tCP, tCPB (internal operating clock cycle time): Refer to “(1) Clock Timing Rating.”
*1: tCYC is a frequency for 1 clock cycle including a gear cycle.
Use the doubler when CPU frequency is above 25 MHz.
*2: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,
respectively.
Min : (1 – n/2) × tCYC – 10
Max : (1 – n/2) × tCYC + 10
Select a gear cycle of × 1 when using the doubler.
*3: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,
respectively.
Min : n/2 × tCYC – 10
Max : n/2 × tCYC + 10
Select a gear cycle of × 1 when using the doubler.
tCYC
tCLCH
tCHCL
CLK
70
VOH
VOH
VOL
MB91101/MB91101A
The relation between the input waveform of source oscillation and the output waveform of CLK pin for configured
by CHC/CCK1/CCK0 settings of GCR (gear control register) is as follows:
However, in this chart source oscillation input means X0 input clock.
tC
Source oscillation input
(when using the doublure)
(1) PLL system
(CHC bit of GCR set to “0”)
(a) Gear × 1 CLK pin
CCK1/0: “00”
tCYC
tC
Source oscillation input
(2) 2 dividing system
(CHC bit of GCR set to “1”)
(a) Gear × 1 CLK pin
CCK1/0: “00”
(b) Gear × 1/2 CLK pin
CCK1/0: “01”
(c) Gear × 1/4 CLK pin
CCK1/0: “10”
(d) Gear × 1/8 CLK pin
CCK1/0: “11”
tCYC
tCYC
tCYC
tCYC
71
MB91101/MB91101A
• Ceramic oscillator applications
Recommended circuit (3 contacts)
Recommended circuit (2 contacts)
X0
X0
X1
X1
*
*
C1
C1
C2
C2
C1, C2 internally
connected.
* : Murata Mfg. Co., Ltd.
• Discreet type
Oscillation frequency
Model
[MHz]
5.00 to 6.30
6.31 to 10.0
10.1 to 13.0
13.01 to 15.00
Power supply voltage
C1 = C2 [pF]
VCC5 [V]
CSA
MG
CST
MGW
CSA
MG093
CST
MGW093
CSA
MTZ
30
CST
MTW
(30)
CSA
MTZ093
30
CST
MTW093
(30)
CSA
MTZ
30
CST
MTW
(30)
CSA
MTZ093
30
CST
MTW093
(30)
30
(30)
30
(30)
CSA
MXZ040
15
CST
MXW0C3
(15)
( ): C1 and C2 internally connected 3 contacts type.
72
Load capacitance
2.9 to 5.5
2.7 to 5.5
2.9 to 5.5
2.7 to 5.5
3.0 to 5.5
2.9 to 5.5
3.2 to 5.5
MB91101/MB91101A
(3) Reset/Hardware Standby Input Ratings
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Parameter
Value
Symbol Pin name Condition
Reset input time
tRSTL
RST
Hardware standby input time
tHSTL
HST
—
Unit
Min
Max
tCP × 5
—
ns
tCP × 5
—
ns
Remarks
tCP (internal operating clock cycle time): Refer to “(1) Clock Timing Rating.”
tRSTL, tHSTL
RST
HST
0.2 VCC5
0.2 VCC5
73
MB91101/MB91101A
(4) Power on Supply Specifications (Power-on Reset)
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Parameter
Power supply rising time
Power supply shut off time
Symbol Pin name
tR
VCC
tR
VCC
tR
VCC
tR
VCC
tOFF
VCC
Value
Condition
VCC = 5.0 V
VCC = 3.0/3.3 V
—
Unit
Remarks
Min
Max
50
—
µs
*
—
30
ms
*
50
—
µs
*
—
18
ms
*
1
—
ms
Repeated
operations
tC (clock cycle time): Refer to “(1) Clock Timing Rating.”
*: VCC < 0.2 V before the power supply rising
tR
VCC
0.9 × VCC5
0.2 V
tOFF
Note: Sudden change in supply voltage during operation may initiate a power-on sequence.
To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid
fluctuations in the supply voltage.
VCC
A voltage rising rate of 50 mV/ms or
less is recommended.
VSS
42 ms approx.
VCC
Regulator
Stabilizing time *
RST
0.2 × VCC5
tRSTL + (tC × 219)
tRSTL: Reset input time
*: Reset can’t be done during regulator stabilizing time.
Note: Set RST pin to “L” level when turning on the device, at least the described above duration after the
supply voltage reaches Vcc is necessary before turning the RST to “H” level.
74
MB91101/MB91101A
(5) Normal Bus Access Read/Write Operation
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Parameter
Symbol
Pin name
Condition
Value
Min
Max
Unit
Remarks
tCHCSL
CLK,
CS0 to CS5
—
15
ns
tCHCSH
CLK,
CS0 to CS5
—
15
ns
Address delay time
tCHAV
CLK,
A24 to A00
—
15
ns
Data delay time
tCHDV
CLK,
D31 to D16
—
15
ns
tCLRL
CLK, RD
—
6
ns
tCLRH
CLK, RD
—
6
ns
tCLWL
CLK,
WR0, WR1
—
6
ns
tCLWH
CLK,
WR0, WR1
—
6
ns
tAVDV
A24 to A00,
D31 to D16
—
3/2 × tCYC
– 25
ns
*1
*2
RD ↓→ valid data input time tRLDV
RD,
D31 to D16
—
tCYC – 10
ns
*1
Data set up → RD ↑ time
tDSRH
RD,
D31 to D16
10
—
ns
RD ↑→ data hold time
tRHDX
RD,
D31 to D16
0
—
ns
CS0 to CS5 delay time
RD delay time
WR0, WR1 delay time
Valid address → valid data
input time
—
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
*1:When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC × extended cycle number for
delay) to this rating.
*2: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,
respectively.
Equation: (2 – n/2) × tCYC – 25
75
MB91101/MB91101A
BA2
BA1
tCYC
CLK
VOH
VOH
VOL
VOH
VOL
tCHCSL
CS0 to CS5
tCHCSH
VOH
VOL
tCHAV
A24 to A00
VOH
VOL
VOH
VOL
tCLRL
tCLRH
RD
VOH
VOL
tRLDV
tRHDX
tAVDV
VIH
VIL
D31 to D16
VIH
VIL
Read
tDSRH
tCLWL
WR0, WR1
VOH
VOL
tCLWH
tCHDV
D31 to D16
76
VOH
VOL
Write
VOH
VOL
MB91101/MB91101A
(6) Ready Input Timing
Parameter
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol
Pin name
RDY set up time → CLK ↓ tRDYS
RDY, CLK
CLK ↓→ RDY hold time
RDY, CLK
tRDYH
Value
Condition
—
Unit
Min
Max
15
—
ns
0
—
ns
Remarks
tCYC
CLK
VOH
VOH
VOL
tRDYH
tRDYS
RDY
When wait(s)
is inserted.
RDY
When no wait
is inserted.
VIL
VIH
VOL
VIH
VIL
tRDYH
tRDYS
VIL
VIH
VIH
VIL
77
MB91101/MB91101A
(7) Hold Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol Pin name Condition
Parameter
tCHBGL
CLK,
BGRNT
tCHBGH
CLK,
BGRNT
BGRNT delay time
—
Value
Unit
Min
Max
—
6
ns
—
6
ns
Pin floating → BGRNT ↓ time tXHAL
BGRNT
tCYC – 10
tCYC + 10
ns
BGRNT ↑→ pin valid time
BGRNT
tCYC – 10
tCYC + 10
ns
tHAHV
Remarks
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
Note : There is a delay time of more than 1 cycle from BRQ input to BGRNT change.
tCYC
CLK
VOH
VOH
VOH
VOH
BRQ
tCHBGH
tCHBGL
BGRNT
VOH
VOL
tXHAL
Each pin
78
VOH
VOL
tHAHV
High-Z
VOH
VOL
MB91101/MB91101A
(8) Normal DRAM Mode Read/Write Cycle
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Parameter
Symbol
Pin name
Condition
Value
Min
Max
Unit
Remarks
tCLRAH
CLK, RAS0, RAS1
—
6
ns
tCHRAL
CLK, RAS0, RAS1
—
6
ns
tCLCASL
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
tCLCASH
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
ROW address delay time
tCHRAV
CLK,
A24 to A00
—
15
ns
COLUMN address delay
time
tCHCAV
CLK,
A24 to A00
—
15
ns
tCHDWL
CLK, DW0, DW1
—
15
ns
tCHDWH
CLK, DW0, DW1
—
15
ns
Output data delay time
tCHDV1
CLK,
D31 to D16
—
15
ns
RAS ↓→ valid data input
time
tRLDV
RAS0, RAS1,
D31 to D16
—
5/2 × tCYC
– 16
ns
*1
*2
CAS ↓→ valid data input
time
tCLDV
CS0H, CS0L, CS1H,
CS1L, D31 to D16
—
tCYC – 17
ns
*1
CAS ↑→ data hold time
tCADH
CS0H, CS0L, CS1H,
CS1L, D31 to D16
0
—
ns
RAS delay time
CAS delay time
DW delay time
—
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
*1: When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
*2: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,
respectively.
Equation: (3 – n/2) × tCYC – 16
79
MB91101/MB91101A
Q1
Q2
Q3
Q4
Q5
tCYC
CLK
VOH
VOL
VOH
VOH
VOH
RAS0
RAS1
VOH
VOL
VOL
VOH
VOL
tCLRAH
tCHRAL
tCLCASH
tCLCASH
CS0H
CS0L
CS1H
CS1L
VOH
VOL
tCHCAV
tCHRAV
VOH
VOL
A24 to A00
ROW address
VOH
VOL
VOH
VOL
COLUMN address
VOH
VOL
tRLDV
tCADH
tCLDV
VIH
VIL
D31 to D16
DW0
DW1
VIH
VIL
Read
VOH
VOL
tCHDWH
tCHDWL
D31 to D16
VOH
VOL
tCHDV1
80
Write
VOH
VOL
MB91101/MB91101A
(9) Normal DRAM Mode Fast Page Read/Write Cycle
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Parameter
RAS delay time
Symbol
Pin name
Condition
Value
Min
Max
Unit
tCLRAH
CLK, RAS0, RAS1
—
6
ns
tCLCASL
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
tCLCASH
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
COLUMN address delay
time
tCHCAV
CLK,
A24 to A00
—
15
ns
DW delay time
tCHDWH
CLK, DW0, DW1
—
15
ns
Output data delay time
tCHDV1
CLK,
D31 to D16
—
15
ns
CAS ↓→ valid data input
time
tCLDV
CS0H, CS0L, CS1H,
CS1L,D31 to D16
—
tCYC – 17
ns
CAS ↑→ data hold time
tCADH
CS0H, CS0L, CS1H,
CS1L, D31 to D16
0
—
ns
CAS delay time
—
Remarks
*
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
*: When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
81
MB91101/MB91101A
Q5
Q4
VOH
CLK
Q5
VOL
Q4
Q5
VOH
VOL
VOL
tCLRAH
VOH
RAS0
RAS1
tCLCASL
CS0H
CS0L
CS1H
CS1L
tCLCASH
VOH
VOL
tCHCAV
A24 to A00
VOH
VOL
COLUMN address
VOH
VOL
COLUMN address
tCADH
tCLDV
D31 to D16
VIH
VIL
Read
VIH
VIL
VIH
VIL
VOH
VOL
COLUMN address
Read
VIH
VIL
VIH
VIL
Read
VIH
VIL
tCHDWH
VOH
DW0
DW1
tCHDV1
D31 to D16
82
VOH
VOL
Write
VOH
VOL
VOH
VOL
Write
VOH
VOL
MB91101/MB91101A
(10) Single DRAM Timing
Parameter
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol
Pin name
Condition
Value
Unit Remarks
Min
Max
—
6
ns
6
ns
tCLRAH2
CLK, RAS0, RAS1
tCHRAL2
CLK, RAS0, RAS1
tCHCASL2
CLK, CS0H, CS0L,
CS1H, CS1L
—
n/2 × tCYC
ns
tCHCASH2
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
ROW address delay time
tCHRAV2
CLK,
A24 to A00
—
15
ns
COLUMN address delay
time
tCHCAV2
CLK,
A24 to A00
—
15
ns
tCHDWL2
CLK, DW0, DW1
—
15
ns
tCHDWH2
CLK, DW0, DW1
—
15
ns
Output data delay time
tCHDV2
CLK,
D31 to D16
—
15
ns
CAS ↓→ Valid data input
time
tCLDV2
CS0H, CS0L, CS1H,
CS1L, D31 to D16
—
(1 – n/2) ×
tCYC – 17
ns
CAS ↑→ data hold time
tCADH2
CS0H, CS0L, CS1H,
CS1L, D31 to D16
0
—
ns
RAS delay time
CAS delay time
DW delay time
—
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
83
MB91101/MB91101A
tCYC
*1
Q1
VOH
CLK
Q2
Q3
VOH
VOL
VOH
RAS0
RAS1
Q4S
Q4S
VOH
Q4S
VOH
VOH
VOL
tCHRAL2
tCLRAH2
tCHCASL2
tCHCASH2
CS0H
CS0L
CS1H
CS1L
VOH
VOL
VOH
VOL
A24 to A00
ROW address
tCHRAV2
VOH
VOL
VOH
VOL COLUMN-0
VOH
VOL
COLUMN-1
COLUMN-2
tCHCAV2
tCADH2
tCLDV2
Read-0
D31 to D16
DW0
DW1
VIH
VIL
Read-1
VIH
VIL
Read-2
VOH
VOL
tCHDWL2
D31 to D16
VOH
VOL
Write-0
tCHDV2
*2
VOH
VOL
tCHDWH2
VOH
VOL
tCHDV2
VOH
VOH
VOL
VOL
Write-1
*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.
*2:
84
indicates the timing when the bus cycle begins from the high speed page mode.
Write-2
MB91101/MB91101A
(11) Hyper DRAM Timing
Parameter
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol
Pin name
Condition
Value
Min
Max
Unit Remarks
tCLRAH3
CLK, RAS0, RAS1
—
6
ns
tCHRAL3
CLK, RAS0, RAS1
—
6
ns
tCHCASL3
CLK, CS0H, CS0L,
CS1H, CS1L
—
n/2 × tCYC
ns
tCHCASH3
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
ROW address delay time
tCHRAV3
CLK,
A24 to A00
—
15
ns
COLUMN address delay
time
tCHCAV3
CLK,
A24 to A00
—
15
ns
tCHRL3
CLK, RD
—
15
ns
tCHRH3
CLK, RD
—
15
ns
tCLRL3
CLK, RD
—
15
ns
tCHDWL3
CLK, DW0, DW1
—
15
ns
tCHDWH3
CLK, DW0, DW1
—
15
ns
Output data delay time
tCHDV3
CLK,
D31 to D16
—
15
ns
CAS ↓→ valid data input
time
tCLDV3
CS0H, CS0L, CS1H,
CS1L, D31 to D16
—
tCYC – 17
ns
CAS ↓→ data hold time
tCADH3
CS0H, CS0L, CS1H,
CS1L, D31 to D16
0
—
ns
RAS delay time
CAS delay time
RD delay time
DW delay time
—
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
85
MB91101/MB91101A
tCYC
*1
Q1
CLK
VOH
Q2
Q3
VOH
VOL
VOH
RAS0
RAS1
Q4H
VOH
Q4H
Q4H
VOH
VOL
VOH
VOL
tCHRAL3
tCLRAH3
tCHCASL3
tCHCASH3
CS0H
CS0L
CS1H
CS1L
VOH
VOL
VOH
VOL
A24 to A00
ROW address
tCHRAV3
VOH
VOL
VOHCOLUMN-0
VOL
VOL
VOL
COLUMN-1
COLUMN-2
tCHCAV3
*2
VOL
RD
VOL
tCHRL3
VOH
tCLRL3
tCHRH3
tCLDV3
tCADH3
Read-0
D31 to D16
DW0
DW1
VIH
VIL
Read-1
VIH
VIL
VOH
VOL
tCHDWL3
D31 to D16
VOH
VOL
Write-0
tCHDV3
*2
VOH
VOL
tCHDWH3
VOH
VOL
tCHDV3
VOH
VOH
VOL
VOL
Write-1
*1: Q4H indicates Q4HR (Read) of Hyper DRAM cycle or Q4HW (Write) cycle.
*2:
86
indicates the timing when the bus cycle begins from the high speed page mode.
Write-2
MB91101/MB91101A
(12) CBR Refresh
Parameter
RAS delay time
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol
Pin name
Max
Unit Remarks
—
6
ns
tCHRAL
CLK, RAS0, RAS1
—
6
ns
tCLCASL
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
tCLCASH
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
VOH
—
R2
VOH
VOL
R3
R4
VOH
VOL
VOH
VOL
VOL
tCHRAL
tCLRAH
CS0H
CS0L
CS1H
CS1L
Min
CLK, RAS0, RAS1
tCYC
R1
RAS0
RAS1
Value
tCLRAH
CAS delay time
CLK
Condition
VOL
tCLCASL
VOH
tCLCASH
DW0
DW1
87
MB91101/MB91101A
(13) Self Refresh
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol
Parameter
RAS delay time
Max
Unit
6
ns
tCHRAL
CLK, RAS0, RAS1
—
6
ns
tCLCASL
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
tCLCASH
CLK, CS0H, CS0L,
CS1H, CS1L
—
6
ns
SR2
VOH
SR3
VOL
RAS0
RAS1
88
Min
—
VOH
VOL
—
Remarks
SR3
VOL
tCHRAL
CS0H
CS0L
CS1H
CS1L
Value
CLK, RAS0, RAS1
tCYC
SR1
CLK
Condition
tCLRAH
CAS delay time
VOH
Pin name
tCLRAH
VOH
VOH
VOL
tCLCASL
tCLCASH
MB91101/MB91101A
(14) UART Timing
Parameter
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol Pin name Condition
Value
Min
Max
8 × tCYCP
—
Unit
Serial clock cycle time
tSCYC
—
SCLK ↓→ SCLK ↑
tSCLCH
—
4 × tCYCP –10 4 × tCYCP +10
ns
SCLK ↑→ SCLK ↓
tSCHCL
—
Internal 4 × tCYCP –10 4 × tCYCP +10
shift clock
–80
+80
mode
100
—
ns
ns
SCLK ↓→ SOUT delay time tSLOV
—
Valid SIN → SCLK ↑
tIVSH
—
SCLK ↑→ valid SIN hold
time
tSHIX
—
60
—
ns
Serial clock “H” pulse width
tSHSL
—
4 × tCYCP
—
ns
Serial clock “L” pulse width
tSLSH
—
4 × tCYCP
—
ns
—
150
ns
60
—
ns
60
—
ns
SCLK ↓→ SOUT delay time tSLOV
—
Valid SIN → SCLK ↑
tIVSH
—
SCLK ↑→ valid SIN hold
time
tSHIX
—
External
shift clock
mode
Remarks
ns
ns
tCYCP: A cycle time of peripheral system clock
Note : This rating is for AC characteristics in CLK synchronous mode.
• Internal shift clock mode
tSCYC
tSCLCH
tSCHCL
VOH
SCLK
VOL
VOL
tSLOV
VOH
VOL
SOUT
tIVSH
tSHIX
VIH
VIL
SIN
VIH
VIL
• External shift clock mode
tSLSH
tSHSL
VIH
VIH
SCLK
VIL
VIL
tSLOV
SOUT
VOH
VOL
tIVSH
SIN
VIH
VIL
tSHIX
VIH
VIL
89
MB91101/MB91101A
(15) Trigger System Input Timing
Parameter
A/D start trigger input time
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol
tTRGH,
tTRGL
PWM external trigger input tTRGH,
time
tTRGL
Pin name
Condition
ATG
Value
Unit
Min
Max
5 × tCYCP
—
ns
5 × tCYCP
—
ns
—
TRG0 to TRG3
tCYCP: A cycle time of peripheral system clock
tTRGH
ATG
TRG0 to TRG3
90
VIH
tTRGL
VIH
VIL
VIL
Remarks
MB91101/MB91101A
(16) DMA Controller Timing
Parameter
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Symbol
Pin name
Condition
Value
Unit
Min
Max
DREQ0 to DREQ2
2 × tCYC
—
ns
tCLDL
CLK,
DACK0 to DACK2
—
6
ns
tCLDH
CLK,
DACK0 to DACK2
—
6
ns
EOP delay time
(Normal bus)
(Normal DRAM)
tCLEL
CLK,
EOP0 to EOP2
—
6
ns
tCLEH
CLK,
EOP0 to EOP2
—
6
ns
DACK delay time
(Single DRAM)
(Hyper DRAM)
tCHDL
CLK,
DACK0 to DACK2
—
n/2 × tCYC
ns
tCHDH
CLK,
DACK0 to DACK2
—
6
ns
tCHEL
CLK,
EOP0 to EOP2
—
n/2 × tCYC
ns
tCHEH
CLK,
EOP0 to EOP2
—
6
ns
DREQ input pulse width tDRWH
DACK delay time
(Normal bus)
(Normal DRAM)
EOP delay time
(Single DRAM)
(Hyper DRAM)
—
Remarks
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
tCYC
CLK
VOH
VOH
VOL
VOL
tCLDL
tCLEL
DACK0 to DACK2
EOP0 to EOP2
(Normal bus)
(Normal DRAM)
tCLDH
tCLEH
VOH
VOL
DACK0 to DACK2
EOP0 to EOP2
(Single DRAM)
(Hyper DRAM)
VOH
VOL
tCHDL
tCHEL
tCHDH
tDRWH
DREQ0 to DREQ2
VIH
VIH
91
MB91101/MB91101A
5. A/D Converter Block Electrical Characteristics
(AVCC = 2.7 V to 3.6 V, AVSS = 0.0 V, AVRH = 2.7 V, TA = –40°C to +70°C)
Symbol
Pin name
Resolution
—
Total error
Parameter
Value
Unit
Min
Typ
Max
—
—
10
10
bit
—
—
—
—
±4.0
LSB
Linearity error
—
—
—
—
±3.5
LSB
Differentiation linearity error
—
—
—
—
±2.0
LSB
Zero transition voltage
VOT
AN0 to AN3
–1.5
+0.5
+2.5
LSB
Full-scale transition voltage
VFST
AN0 to AN3 AVRH – 4.5 AVRH – 1.5 AVRH + 0.5 LSB
Conversion time
—
—
5.6 *1
—
—
µs
Analog port input current
IAIN
AN0 to AN3
—
0.1
10
µA
Analog input voltage
VAIN
AN0 to AN3
AVSS
—
AVRH
V
—
AVRH
AVSS
—
AVCC
V
IA
AVCC
—
4
—
mA
Reference voltage
Power supply current
Reference voltage supply current
Conversion variance between channels
2
IAH
AVCC
—
—
5*
IR
AVRH
—
200
—
IRH
AVRH
—
—
5*
—
AN0 to AN3
—
—
4
2
µA
µA
µA
LSB
*1: AVCC = 2.7 V to 3.6 V
*2 Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 3.6 V)
Notes: • As the absolute value of AVRH decreases, relative error increases.
• Output impedance of external circuit of analog input under following conditions;
Output impedance of external circuit < 10 kΩ.
If output impedance of external circuit is too high, analog voltage sampling time may be too short for
accurate sampling (sampling time is 5.6 µs for a machine clock of 25 MHz).
• Analog input circuit
Sample and hold circuit
Analog input
C0
Comparator
RON1
RON1 : 0.2 kΩ
RON2 : 1.4 kΩ
RON3 : 1.4 kΩ
RON4 : 0.2 kΩ
RON2
RON3
RON4
C0 : 16.6 pF
C1 : 4.0 pF
Note: Listed values are for reference purposes only.
92
C1
MB91101/MB91101A
6. A/D Converter Glossary
• Resolution
The smallest change in analog voltage detected by A/D converter.
• Linearity error
A deviation of actual conversion characteristic from a line connecting the zero-traction point (between “00 0000
0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111 1111”).
• Differential linearity error
A deviation of a step voltage for changing the LSB of output code from ideal input voltage.
Differential linearity error
Linearity error
3FF
Ideal characteristic
Actual conversion
characteristic
3FE
N+1
{1 LSB × (N – 1) + VOT}
Actual characteristic
Digital output
Digital output
3FD
VFST
(measured
value)
004
VNT
(measured value)
Actual conversion
characteristic
003
N
N–1
V(N + 1)T
VNT (measured value)
(measured value)
002
Ideal characteristic
N–2
001
VOT (measured value)
AVRL
Actual conversion characteristic
AVRH
AVRL
Linearity error of
digital output N =
1 LSB =
VFST – VOT
1022
VNT – {1 LSB × (N – 1) + VOT}
1 LSB
AVRH
Analog input
Analog input
[LSB]
Differential linearity error
of digital output N =
V(N + 1)T – VNT
1 LSB
– 1 [LSB]
[V]
VOT: A voltage for causing transition of digital output from (000)H to (001)H
VFST: A voltage for causing transition of digital output from (3FE)H to (3FF)H
VNT: A voltage for causing transition of digital output from (N – 1) to N
93
MB91101/MB91101A
• Total error
A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error
3FF
1.5 LSB’
3FE
Actual conversion
characteristic
Digital output
3FD
{1 LSB’ × (N – 1)
+ 0.5 LSB’}
004
VNT
(measured value)
003
Actual conversion
characteristic
002
Ideal characteristic
001
0.5 LSB’
AVRL
AVRH
Analog input
Total error of digital output N =
1 LSB’ (ideal value) =
AVRH – AVRL
1024
VOT’
VNT – {1 LSB’ × (N – 1) + 0.5 LSB’}
1 LSB'
[V]
(ideal value) = AVRL + 0.5 LSB’ [V]
VFST’ (ideal value) = AVRL – 1.5 LSB’ [V]
VNT: A voltage for causing transition of digital output from (N – 1) to N
94
[LSB]
MB91101/MB91101A
■ REFERENCE DATA
(1) Operating frequency vs. ICC characteristics
Internal DC - DC regulator is not used (VCC5 = VCC3 = 3 V)
Internal DC - DC regulator is used (VCC5 = 5 V)
90
90
(VCC)
80
(VCC)
80
3.6 V
4.5 V to 5.5 V
70
70
3.3 V
60
3.0 V
50
ICC (mA)
ICC (mA)
60
2.7 V
40
50
40
30
30
20
20
10
10
0
0
0
10
20
30
f (MHz)
40
50
0
10
20
30
f (MHz)
40
50
Operating conditions : Source oscillation 12.5 MHz (crystal), PLL is used (50 MHz, 25 MHz, 12.5 MHz)
Gear : CPU = 1/1, Peripherals = 1/1
(Doubler is used for 50MHz, Gear peripherals = 1/2)
(2) VCC vs. ICC characteristics
Internal DC - DC regulator is not used (VCC5 = VCC3 = 3 V)
Internal DC - DC regulator is used (VCC5= 5 V)
ICC (mA)
Icc (mA)
18
18
Gear : 1/1
16
16
14
14
Gear : 1/1
Gear : 1/2
12
12
10
10
Gear : 1/2
Gear : 1/4
8
8
Gear : 1/8
Gear : 1/4
6
6
Gear : 1/8
(PLL : off)
4
Gear : 1/8
4
Gear : 1/8
(PLL : off)
2
2
0
0
2.4
VCC (V)
2.7
3.0
3.3
4.5
3.6
5.0
5.5
VCC (V)
Operating conditions : Source oscillation 12.5 MHz (crystal), divide-by-2 input, PLL : ON
Gear : CPU = Peripherals
95
MB91101/MB91101A
■ ORDERING INFORMATION
Part number
96
Package
MB91101APFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB91101APF
100-pin Plastic QFP
(FPT-100P-M06)
Remarks
MB91101/MB91101A
■ PACKAGE DIMENSIONS
100-pin Plastic LQFP
(FPT-100P-M05)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
1
25
C
2003 FUJITSU LIMITED F100007S-c-4-6
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
97
MB91101/MB91101A
(Continued)
100-pin Plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
98
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
2002 FUJITSU LIMITED F100008S-c-5-5
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
MB91101/MB91101A
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0310
 FUJITSU LIMITED Printed in Japan