54ABT373 Octal Transparent Latch with TRI-STATE ® Outputs General Description The ’ABT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. Features n Guaranteed multiple output switching specifications n Output switching specified for both 50 pF and 250 pF loads n Guaranteed simultaneous switching, noise level and dynamic threshold performance n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9321801 n TRI-STATE outputs for bus interfacing n Output sink capability of 48 mA, source capability of 24 mA Ordering Code Military Package Number Package Description 54ABT373J-QML J20A 20-Lead Ceramic Dual-In-Line 54ABT373W-QML W20A 20-Lead Cerpack 54ABT373E-QML E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100206-2 DS100206-1 Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 TRI-STATE Latch (Active HIGH) (Active LOW) Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100206 www.national.com 54ABT373 Octal Transparent Latch with TRI-STATE Outputs July 1998 Functional Description Truth Table The ’ABT373 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Output LE OE Dn On H L H H H L L L L L X On (no change) X H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance State Logic Diagram DS100206-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Over Voltage Latchup (I/O) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) 10V Recommended Operating Conditions −65˚C to +150˚C −55˚C to +125˚C Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. −0.5V to +5.5V −0.5V to VCC twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter ABT373 Min Typ Units VCC Conditions Max VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH Voltage V Min IOH = −24 mA VOL Output LOW Voltage IIH Input HIGH Current 2.0 54ABT 2.5 54ABT 2.0 V Recognized HIGH Signal Recognized LOW Signal IOH = −3 mA 54ABT 0.55 V Min IOL = 48 mA 5 µA Max VIN = 2.7V (Note 4) 7 µA Max VIN = 7.0V −5 µA Max VIN = 0.5V (Note 4) V 0.0 VIN = VCC 5 IBVI Input HIGH Current Breakdown Test IIL Input LOW Current VIN = 0.0V −5 VID Input Leakage Test 4.75 IID = 1.9 µA All Other Pins Grounded VOUT = 2.7V; OE = 2.0V IOZH Output Leakage Current 50 µA 0 − 5.5V IOZL Output Leakage Current −50 µA 0 − 5.5V IOS Output Short-Circuit Current −275 mA Max VOUT = 0.0V ICEX Output High Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max −100 VOUT = 0.5V; OE = 2.0V OE = VCC All Others at VCC or GND ICCT Additional ICC/Input Outputs Enabled 2.5 mA Outputs TRI-STATE 2.5 mA Outputs TRI-STATE 2.5 mA VI = VCC − 2.1V Max Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 4) 0.12 MHz Max Outputs Open, LE = VCC OE = GND, (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested. 3 www.national.com AC Electrical Characteristics Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units CL = 50 pF Min Max tPLH Propagation Delay 1.0 6.8 tPHL Dn to On 1.0 7.0 tPLH Propagation Delay 1.0 7.7 tPHL LE to On 1.5 7.7 tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ 1.0 6.7 1.5 7.2 1.7 8.0 1.0 7.0 ns ns ns ns AC Operating Requirements Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units CL = 50 pF Min ts(H) Setup Time, HIGH 2.5 ts(L) or LOW Dn to LE 2.5 th(H) Hold Time, HIGH 2.5 th(L) or LOW Dn to LE 2.5 Pulse Width, 3.3 tw(H) Max ns ns ns LE HIGH Capacitance Symbol Parameter Typ Units CIN Input Capacitance 5 pF Conditions (TA = 25˚C) VCC = 0V COUT (Note 5) Output Capacitance 9 pF VCC = 5.0V Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to Output tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to Output DS100206-11 DS100206-12 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 4 Capacitance (Continued) tPZH vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output tPZL vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output DS100206-13 DS100206-14 tPHZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output tPLZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output DS100206-15 DS100206-16 tSET LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to LE tSET HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to LE DS100206-17 DS100206-18 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 5 www.national.com Capacitance (Continued) tHOLD HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to LE tHOLD LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to LE DS100206-19 DS100206-20 tPLH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching Data to Output tPHL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching Data to Output DS100206-21 DS100206-22 tPZH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output tPZL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output DS100206-23 DS100206-24 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 6 Capacitance (Continued) tPHZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output tPLZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output DS100206-25 DS100206-26 tPLH vs Load Capacitance TA = 25˚C, 1 Output Switching Data to Output tPHL vs Load Capacitance TA = 25˚C, 1 Output Switching Data to Output DS100206-27 DS100206-28 tPLH vs Load Capacitance TA = 25˚C, 8 Outputs Switching Data to Output tPHL vs Load Capacitance TA = 25˚C, 8 Outputs Switching Data to Output DS100206-29 DS100206-30 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 7 www.national.com Capacitance (Continued) tPZH vs Load Capacitance TA = 25˚C, 8 Outputs Switching OE to Output tPZL vs Load Capacitance TA = 25˚C, 8 Outputs Switching OE to Output DS100206-31 DS100206-32 tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching LE to Output tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching LE to Output DS100206-35 DS100206-36 tPLH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching LE to Output tPHL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching LE to Output DS100206-37 DS100206-38 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 8 Capacitance (Continued) Typical ICC vs Output Switching Frequency CL = 0 pF, VCC = VIH = 5.5V, LE = GND, 1 Output Switching at 50% Duty Cycle Data to Output, Transparent Mode with Unused Data Inputs = VIH tPLH and tPHL vs Number Outputs Switching CL = 50 pF, TA = 25˚C, VCC = 5.0V, Outputs In Phase Data to Output DS100206-33 DS100206-34 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 9 www.national.com AC Loading DS100206-5 DS100206-4 FIGURE 5. Propagation Delay, Pulse Width Waveforms *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load DS100206-7 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times DS100206-6 FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS100206-9 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms DS100206-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions www.national.com 10 11 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 20-Lead Ceramic Flatpak (F) NS Package Number W20A 13 www.national.com 54ABT373 Octal Transparent Latch with TRI-STATE Outputs LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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