54ABT573 Octal D-Type Latch with TRI-STATE ® Outputs General Description The ’ABT573 is an octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. This device is functionally identical to the ’ABT373 but has different pinouts. Features n Inputs and outputs on opposite sides of package allow easy interface with microprocessors n Useful as input or output port for microprocessors n Functionally identical to ’ABT373 n TRI-STATE outputs for bus interfacing n Output sink capability of 48 mA, source capability of 24 mA n Output switching specified for both 50 pF and 250 pF loads n Guaranteed latchup protection n High impedance glitch-free bus loading during entire power up and power down n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9321901 Ordering Code Military Package Package Description Number 54ABT573J-QML J20A 20-Lead Ceramic Dual-In-Line 54ABT573W-QML W20A 20-Lead Cerpack 54ABT573E-QML E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagram Pin Assignment for LCC Pin Assignment for DIP and Cerpack DS100219-39 DS100219-1 Pin Names D0–D7 Description Data Inputs LE Latch Enable Input (Active HIGH) OE TRI-STATE Output Enable Input (Active LOW) O0–O7 TRI-STATE Latch Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100219 www.national.com 54ABT573 Octal D-Type Latch with TRI-STATE Outputs July 1998 Function Table Functional Description Inputs The ’ABT573 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Outputs OE LE D O L H H H L H L L L L X O0 H X X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle Logic Diagram DS100219-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Over Voltage Latchup (I/O) Storage Temperature −65˚C to +150˚C Ambient Temperature under Bias −55˚C to +125˚C Junction Temperature under Bias Ceramic −55˚C to +175˚C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to +5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) Twice the rated IOL (mA) DC Latchup Source Current −500 mA Recommended Operating Conditions 10V Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter ABT573 Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54ABT 2.5 54ABT 2.0 VOL Output LOW Voltage 54ABT IIH Input HIGH Current Typ Units VCC 2.0 V Recognized HIGH Signal 0.8 V −1.2 V Min Recognized LOW Signal IIN = −18 mA V Min IOH = −3 mA 0.55 V Min IOL = 48 mA 5 µA Max IOH = −24 mA Input HIGH Current VIN = 2.7V (Note 4) VIN = VCC 5 IBVI Conditions Max 7 µA Max −5 µA Max VIN = 7.0V Breakdown Test IIL Input LOW Current VID Input Leakage Test 4.75 IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX VIN = 0.5V (Note 4) VIN = 0.0V −5 IID = 1.9 µA V 0.0 µA 0 − 5.5V VOUT = 2.7V; OE = 2.0V VOUT = 0.5V; OE = 2.0V All Other Pins Grounded 50 −50 µA 0 − 5.5V −275 mA Max VOUT = 0.0V Output High Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max −100 OE = VCC All Others at VCC or GND ICCT Additional ICC/Input Outputs Enabled 2.5 mA Outputs TRI-STATE 2.5 mA Outputs TRI-STATE 2.5 mA VI = VCC − 2.1V Max Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 4) 0.12 MHz Max Outputs Open OE = GND, LE = VCC (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed but not tested. 3 www.national.com DC Electrical Characteristics Symbol Parameter Min Max Units VCC VOLP Quiet Output Maximum Dynamic VOL 0.9 V 5.0 VOLV Quiet Output Minimum Dynamic VOL -1.7 V 5.0 Conditions CL = 50 pF, RL = 500Ω TA = 25˚C (Note 5) TA = 25˚C (Note 5) Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units Fig. No. ns Figure 4 ns Figure 4 ns Figure 6 ns Figure 6 CL = 50 pF Min Max tPLH Propagation Delay 1.0 6.4 tPHL Dn to On 1.5 6.7 tPLH Propagation Delay 1.0 7.1 tPHL LE to On 1.5 7.5 tPZH Output Enable Time tPZL 0.8 6.5 1.5 7.2 tPHZ Output Disable Time 1.5 7.7 tPLZ Time 1.0 7.0 AC Operating Requirements Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units Fig. No. CL = 50 pF Min ts(H) Set Time, HIGH 2.5 ts(L) or LOW Dn to LE 2.5 th(H) Hold Time, HIGH 2.5 th(L) or LOW Dn to LE 2.5 tw(H) Pulse Width, 3.3 LE HIGH Capacitance Symbol Parameter Typ Units CIN Input Capacitance 5 pF Conditions (TA = 25˚C) VCC = 0V COUT (Note 6) Output Capacitance 9 pF VCC = 5.0V Note 6: COUT is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012. www.national.com 4 Max ns Figure 7 ns Figure 7 ns Figure 5 Capacitance (Continued) TPLH vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to Output TPHL vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to Output DS100219-10 DS100219-11 TPZH vs Temperature (TA), CL = 50 pF, 1 Output Switching, OE to Output TPZL vs Temperature (TA), CL = 50 pF, 1 Output Switching, OE to Output DS100219-12 DS100219-13 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 5 www.national.com Capacitance (Continued) TPHZ vs Temperature (TA), CL = 50 pF, 1 Output Switching, OE to Output TPLZ vs Temperature (TA), CL = 50 pF, 1 Output Switching, OE to Output DS100219-14 DS100219-15 TSET LOW vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to LE TSET HIGH vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to LE DS100219-16 DS100219-17 THOLD HIGH vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to LE THOLD LOW vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to LE DS100219-18 DS100219-19 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 6 Capacitance (Continued) TPLH vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, Data to Output TPHL vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, Data to Output DS100219-20 DS100219-21 TPZH vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, OE to Output TPZL vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, OE to Output DS100219-22 DS100219-23 TPHZ vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, OE to Output TPLZ vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, OE to Output DS100219-24 DS100219-25 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 7 www.national.com Capacitance (Continued) TPLH vs Load Capacitance TA = 25˚C, 1 Output Switching, Data to Output TPHL vs Load Capacitance TA = 25˚C, 1 Output Switching, Data to Output DS100219-26 DS100219-27 TPLH vs Load Capacitance TA = 25˚C, 8 Outputs Switching, Data to Output TPHL vs Load Capacitance TA = 25˚C, 8 Outputs Switching, Data to Output DS100219-28 DS100219-29 TPZH vs Load Capacitance TA = 25˚C, 8 Outputs Switching, OE to Output TPZL vs Load Capacitance TA = 25˚C, 8 Outputs Switching, OE to Output DS100219-30 DS100219-31 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 8 Capacitance (Continued) TPLH vs Temperature (TA), CL = 50 pF, 1 Output Switching, LE to Output TPHL vs Temperature (TA), CL = 50 pF, 1 Output Switching, LE to Output DS100219-34 DS100219-35 TPLH vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, LE to Output TPHL vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, LE to Output DS100219-36 TPLH and TPHL vs Number Outputs Switching, CL = 50 pF, TA = 25˚C, VCC = 5.0V, Outputs In Phase Data to Output DS100219-37 Typical ICC vs Output Switching Frequency, CL = 0 pF, VCC = VIH = 5.5V, LE = GND, 1 Output Switching at 50% Duty Cycle, Data to Output, Transparent Mode with Unused Data Inputs = VIH DS100219-33 DS100219-32 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 9 www.national.com AC Loading DS100219-4 *Includes jig and probe capacitance DS100219-5 FIGURE 1. Test Load FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100219-7 DS100219-6 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS100219-9 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms DS100219-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier NS Package Number E20A 20-Lead Ceramic Dual-In-Line NS Package Number J20A 11 www.national.com 54ABT573 Octal D-Type Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpack NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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