MICROCIRCUIT DATA SHEET Original Creation Date: 08/06/98 Last Update Date: 03/09/99 Last Major Revision Date: 02/26/99 MNCLC501A-X REV 0A0 HIGH-SPEED OUTPUT CLAMPING OP AMP General Description The CLC501 is a high-speed current-feedback op amp with the unique feature of output voltage clamping. This feature allows both the maximum positive (Vhigh) and negative (Vlow) output voltage levels to be established. This is useful in a number of applications in which "downstream" circuitry must be protected from overdriving input signals. Not only can this prevent damage to downstream circuitry, but can also reduce time delays since saturation is avoided. The CLC501's very fast 1ns overload/clamping recovery time is useful in applications in which information-containing signals follow overdriving signals. Engineers designing high-resolution, subranging A/D systems have long sought an amplifier capable of meeting the demanding requirements of the residue amplifier function. Amplifiers providing the residue function must not only settle quickly, but recover from overdrive quickly, protect the second stage A/D, and provide high fidelity at relatively high gain settings. The CLC501, which excels in these areas, is the ideal design solution in this onerous application. To further support this application, the CLC501 is both characterized and tested at a gain setting of +32, the most common gain setting for residue amplifier applications. The CLC501's other features provide a quick, high-performance design solution. Since the CLC501's current feedback design requires no external compensation, designers need not spend their time designing compensation networks. The small 8-pin package and low, 180mW power consumption make the CLC501 ideal in numerous applications having small power and size budgets. Industry Part Number NS Part Numbers CLC501A CLC501AJ-MLS CLC501AJ-QML* CLC501AWG-MLS CLC501AWG-QML** Prime Die UB1148C Controlling Document 5962-8997401PA*,MXA** Processing Subgrp Description MIL-STD-883, Method 5004 1 2 3 4 5 6 7 8A 8B 9 10 11 Quality Conformance Inspection MIL-STD-883, Method 5005 1 Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at Temp ( oC) +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 MICROCIRCUIT DATA SHEET MNCLC501A-X REV 0A0 Features - Output clamping (Vhigh and Vlow) 1ns recovery from clamping/overdrive 0.05% settling in 12ns Characterized and guaranteed at Av = +32 Low power, 180mW Applications - Residue amplifier in high-accuracy, subranging A/D systems High-speed communications Output clamping applications Pulse amplitude modulation systems 2 MICROCIRCUIT DATA SHEET MNCLC501A-X REV 0A0 (Absolute Maximum Ratings) (Note 1) Supply Voltage (Vs) +7V dc Output Current (Iout) 70mA Junction Temperature (Tj) +175 C Storage Temperature -65 C to +150 C Lead Temperature (soldering, 10 seconds) +300 C Power Dissipation (Pd) (Note 2) TBD Common Mode Input Voltage (Vcm) Vs Thermal Resistance ThetaJA (Junction to Ambient) CERAMIC DIP (Still Air) (500LFPM) SOIC (Still Air) (500LFPM) ThetaJC (Juntion to Case) CERAMIC DIP SOIC Package Weight (Typical) CERAMIC DIP SOIC ESD Tolerance (Note 3) ESD Rating Note 1: Note 2: Note 3: TBD TBD TBD TBD TBD TBD TBD TBD <1000V Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The maximum power dissipation must be derated at elevated temperatures and is dictated by Tjmax (maximum junction temperature), ThetaJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is Pdmax = (Tjmax - TA)/ThetaJA or the number given in the Absolute Maximum Ratings, whichever is lower. Human body model, 100pF discharged through 1.5K Ohms. 3 MICROCIRCUIT DATA SHEET MNCLC501A-X REV 0A0 Recommended Operating Conditions Supply Voltage (Vs) +5V dc Gain Range (Av) +7 to +50 and -1 to -50 Ambient Operating Temperature Range (Ta) -55 C to +125 C 4 MICROCIRCUIT DATA SHEET MNCLC501A-X REV 0A0 Electrical Characteristics DC PARAMETERS: Open Loop Characteristics (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Rl = 100Ohms, Vs = +5V dc, Vhigh = +3V, Vlow = -3V, Av = +32, feedback resistance (Rf) = 1.5kOhms, and gain setting resistance (Rg) = 48.3Ohms. -55 C < Ta < +125 C (note 3) SYMBOL +Iin -Iin Vio Tc (+Iin) PARAMETER Input Bias Current (noninverting) Input Bias Current (inverting) Input Offset Voltage CONDITIONS Rs = 50Ohms Tc (Vio) Average Offset Voltage Drift Rs = 50Ohms Is Supply Current No Load CMRR Common Mode Rejection Ratio MAX UNIT SUBGROUPS +25 uA 1 +35 uA 2 +37 uA 3 +30 uA 1 +40 uA 2 +46 uA 3 +3.0 mV 1 +5.0 mV 2 +4.6 mV 3 1 +100 nA/C 2 1 +150 nA/C 3 1 +100 nA/C 2 1 +200 nA/C 3 1 +20 uV/C 1, 2, 3 24 mA 1, 2 25 mA 3 60 dB 1, 2 55 dB 3 Rs = 50Ohms Average -Input Bias Current Drift Power Supply Rejection Ratio MIN Rs = 50Ohms Rs = 50Ohms PSRR PINNAME Rs = 50Ohms Average +Input Bias Current Drift Tc (-Iin) NOTES +Vs = +4.5V to +5.0V, -Vs = -4.5V to -5.0V Vcm = +1V 1 60 dB 1, 2 Vcm = +1V 1 55 dB 3 +Iout Output Current Rl = 100Ohms 1 +50 mA 1, 2 +Iout Output Current Rl = 100Ohms 1 +30 mA 3 Rout Output Impedance at dc Rl = 100Ohms 1 +Rin Input Resistance Cin Input Capacitance Ta = +25 C +Vout Output Voltage Swing Rl = 100Ohms 0.3 1 100 kOhms 1, 2 1 50 kOhms 3 1 7 +2.4 5 Ohms 1, 2, 3 pF 4 V 4, 5, 6 MICROCIRCUIT DATA SHEET MNCLC501A-X REV 0A0 Electrical Characteristics DC PARAMETERS: CLAMPING CHARACTERISTICS (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Rl = 100Ohms, Vs = +5V dc, Vhigh = +3V, Vlow = -3V, Av = +32, feedback resistance (Rf) = 1.5kOhms, and gain setting resistance (Rg) = 48.3Ohms. -55 C < Ta < +125 C (note 3) SYMBOL PARAMETER Voc Clamp Accuracy ICL Input Bias Current on Vhigh and Vlow CDR CONDITIONS NOTES PINNAME MIN MAX UNIT SUBGROUPS +0.2 V 1, 2, 3 1 +50 uA 1, 2 1 +100 uA 3 Input Offset Voltage Drift After Recovery 1 200 uV 1, 2, 3 OVC Overshoot in Clamp 1 15 % 4 CMC Clamping Range TSO At Vhigh or Vlow Overload Recovery from Clamp 1 +3.3 V 4, 5 1 +3.0 V 6 ns 9, 10, 11 1 3 AC PARAMETERS: FREQUENCY DOMAIN CHARCTERISTICS (The following conditions apply to all the following parameters, unless otherwise specified.) AC: Rl = 100Ohms, Vs = +5V dc, Vhigh = +3V, Vlow = -3V, Av = +32, feedback resistance (Rf) = 1.5kOhms, and gain setting resistance (Rg) = 48.3Ohms. -55 C < Ta < +125 C (note 3) SSBW Small Signal Bandwidth -3dB bandwidth, Vout < 5Vpp -3dB bandwidth, Av = +20, Vout < 2Vpp GFPL Gain Flatness, Peaking Low 60 MHz 4 2 45 MHz 5 2 60 MHz 6 1 85 MHz 4 1 55 MHz 5 1 85 MHz 6 0.1 dB 4 0.1 dB 5, 6 0.2 dB 4 0.2 dB 5, 6 1.0 dB 4 2 1.3 dB 5 2 1.0 dB 6 1 1.0 Deg 4, 5, 6 0.1MHz to 15MHz, Vout < 5Vpp 2 GFPH Gain Flatness, Peaking High > 15MHz, Vout < 5Vpp 2 GFR LPD Gain Flatness, Rolloff Linear Phase Deviation 0.1MHz to 30MHz, Vout < 5Vpp 0.1MHz to 30MHz, Vout < 5Vpp 6 MICROCIRCUIT DATA SHEET MNCLC501A-X REV 0A0 Electrical Characteristics AC PARAMETERS: Distortion and Noise Characteristics (The following conditions apply to all the following parameters, unless otherwise specified.) AC: Rl = 100Ohms, Vs = +5V dc, Vhigh = +3V, Vlow = -3V, Av = +32, feedback resistance (Rf) = 1.5kOhms, and gain setting resistance (Rg) = 48.3Ohms. -55 C < Ta < +125 C (note 3) SYMBOL HD2 PARAMETER 2nd Harmonic Distortion CONDITIONS NOTES 2Vpp at 20MHz SNF INV 3rd Harmonic Distortion Noise Floor Integrated Noise 1MHz to 100MHz MAX UNIT SUBGROUPS dBc 4 -30 dBc 5, 6 -50 dBc 4 2 -50 dBc 5 2 -45 dBc 6 2Vpp at 20MHz > 1MHz MIN -33 2 HD3 PINNAME 1 -156 dBm 1Hz 4, 6 1 -155 dBm 1Hz 5 1 35 uV 4, 6 1 40 uV 5 AC PARAMETERS: Timing Domain Characteristics (The following conditions apply to all the following parameters, unless otherwise specified.) AC: Rl = 100Ohms, Vs = +5V dc, Vhigh = +3V, Vlow = -3V, Av = +32, feedback resistance (Rf) = 1.5kOhms, and gain setting resistance (Rg) = 48.3Ohms. -55 C < Ta < +125 C (note 3) SR Tr Tf Ts OS Slew Rate Rise and Fall Time Rise and Fall Time Settling Time Overshoot Cl < 10pF, measured at +1V with 3V step 1 800 V/uS 4, 6 Cl < 10pF, measured at +1V with 3V step 1 700 V/uS 5 2V step, Cl < 10pF 1 5.8 nS 9, 11 1 7.8 nS 10 1 6.5 nS 9, 11 1 8 nS 10 2V step at +0.05% of the fixed value, Cl < 10pF 1 18 nS 9, 11 2V step at +0.05% of the fixed value, Cl < 10pF 1 24 nS 10 2V step, Cl < 10pF 1 5 % 9, 10, 11 5V step, Cl < 10pF 7 MICROCIRCUIT DATA SHEET MNCLC501A-X REV 0A0 Electrical Characteristics DC PARAMETERS: DRIFT LIMITS (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Rl = 100Ohms, Vs = +5V dc, Vhigh = +3V, Vlow = -3V, Av = +32, (Rf) = 1.5kOhms, (Rg) = 48.3Ohms. "Deltas not required on B-level product. Deltas required for S-level (-MLS) product as specified on Internal Processing Instructions (IPI)." (note 3) SYMBOL PARAMETER CONDITIONS NOTES PINNAME MIN MAX UNIT SUBGROUPS +Iin Input Bias Current (noninverting) Rs = 50 Ohms +2.5 uA 1 -Iin Input Bias Current (inverting) Rs = 50 Ohms +3.0 uA 1 Vio Input Offset Voltage Rs = 50 Ohms +0.3 mV 1 Is Supply Current No Load +2.4 mA 1 Note 1: Note 2: Note 3: If not tested, shall be guaranteed to the limits specified in table I herein. Group A testing only. The limiting terms, "Min" (minimum) and "Max" (maximum) shall be considered to apply to magnitudes only. Negative current shall be defined as conventional current flow out of a device terminal. 8 MICROCIRCUIT DATA SHEET MNCLC501A-X REV 0A0 Graphics and Diagrams GRAPHICS# DESCRIPTION 07070HRA2 CERAMIC SOIC (WG), 10 LEAD (B/I CKT) 07081HRA3 CERDIP (J), 8 LEAD (B/I CKT) J08ARL CERDIP (J), 8 LEAD (P/P DWG) P000409A CERDIP (J), 8 LEAD (PINOUT) P000448A CERAMIC SOIC (WG), 10 LEAD (PINOUT) WG10ARB CERAMIC SOIC (WG), 10 LEAD (P/P DWG) See attached graphics following this page. 9 N/C 1 8 VHIGH VINV 2 7 +VCC 3 6 VOUT 4 5 VLOW VNON-INV -VCC CLC501J 8 - LEAD DIP CONNECTION DIAGRAM TOP VIEW P000409A N MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050 N/C 1 10 VHIGH VINV 2 9 +VCC N/C 3 8 N/C VNON-INV 4 7 VOUT -VCC 5 6 VLOW CLC501AWG 10 - LEAD CERAMIC SOIC CONNECTION DIAGRAM TOP VIEW P000448A N MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050 MICROCIRCUIT DATA SHEET MNCLC501A-X REV 0A0 Revision History Rev ECN # 0A0 M0003288 03/09/99 Rel Date Originator Changes Shaw Mead Initial MDS Release 10