UTRON Rev. 1.0 UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM REVISION HISTORY REVISION DESCRIPTION Preliminary Rev. 0.5 Original. Rev.1.0 1. Revised Features -Access time 70/100ns 55/70/100ns -Operating current 5mA(Icc1,max) 45/35/25mA(Icc max) -Standby current 80/25uA(max) 20/2uA(typ) -Vcc power supply 2.7~3.3V 2.5~3.6V 2. Revised Function block diagram 3. Revised DC electrical characteristics table 4. Revised AC electrical characteristics table 5. Revised Timing waveforms 6. Revised Data retention characteristics table & waveform 7. Revised 48 TFBGA outline dimension, ball size 0.3mm 0.35mm 8. Revised order information UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Date Mar, 2001 May 15,2003 P80042 UTRON UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.0 FEATURES GENERAL DESCRIPTION Fast access time : 55ns (max.) for Vcc=2.7V~3.6V 70/100ns (max.) for Vcc=2.5V~3.6V CMOS low power operating Operating current : 45/35/25mA (Icc max.) Standby current : 20uA(max.) L–version 2uA(max.) LL-version Single 2.5V~3.6V power supply Operating temperature: Commercial : 0℃~70℃ Industrial : -40℃~85℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Data retention voltage : 1.5V (min.) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 48-pin 6mm × 8mm TFBGA The UT62L12916 is a 2,097,152-bit low power CMOS static random access memory organized as 131,072 words by 16 bits. The UT62L12916 operates from a single 2.5V ~ 3.6V power supply and all inputs and outputs are fully TTL compatible. The UT62L12916 is designed for low power system applications. It is particularly well suited for use in high-density low power system applications. FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 128K X 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 Lower Byte I/O9-I/O16 Upper Byte CE2 CE OE WE CONTROL CIRCUIT LB UB UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80042 UTRON UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.0 PIN DESCRIPTION PIN CONFIGURATION LB OE A0 A1 A2 CE2 B I/O 9 UB A3 A4 CE I/O 1 C I/O 1 0 I/O 1 1 A5 A6 I/O 2 I/O 3 V ss I/O 1 2 NC A7 I/O 4 V cc V cc I/O 1 3 NC A16 I/O 5 V ss I/O 1 5 I/O 1 4 A14 A15 I/O 6 I/O 7 I/O 1 6 C IO S A12 A13 WE I/O 8 NC A8 A9 A10 A11 NC A D SYMBOL A0 - A17 I/O1 - I/O16 CE , CE2 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input WE OE Write Enable Input Output Enable Input Lower-byte Control LB UB VCC VSS NC E F Upper-byte Control Power Supply Ground No Connection G H 1 2 3 4 5 6 TFBGA TRUTH TABLE MODE CE CE2 OE H X X X L X X X X L H H Output Disable L H H L H L Read L H L L H L L H X Write L H X L H X Note: H = VIH, L=VIL, X = Don't care. Standby WE LB UB X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 I/O OPERATION I/O1-I/O8 I/O9-I/O16 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z DOUT High – Z DOUT DOUT High – Z DIN DIN High – Z DIN DIN SUPPLY CURRENT ISB, ISB1 ICC,ICC1,ICC2 ICC,ICC1,ICC2 ICC,ICC1,ICC2 P80042 UTRON UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.0 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Commercial Operating Temperature Industrial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 0 to 70 -40 to 85 -65 to 150 1 50 260 UNIT V ℃ ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (TA = 0℃ to 70℃/-40℃ to 85℃(I)) PARAMETER Power Voltage SYMBOL TEST CONDITION VCC ＊1 Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VIH ＊2 VIL ILI ILO VOH VOL Operating Power Supply Current ICC Average Operation Current ICC1 VSS ≦VIN ≦VCC VSS ≦VI/O ≦VCC; Output Disable IOH= -1mA IOL= 2.1mA Cycle time=min, 100%duty I/O=0mA, CE =VIL 100%duty,II/O=0mA, CE ≦0.2V, other pins at 0.2V or Vcc-0.2V ICC2 Standby Current (TTL) ISB Standby Current (CMOS) ISB1 CE =VIH, other pins =VIL or VIH CE =VCC-0.2V other pins at 0.2V or Vcc-0.2V MIN. TYP. MAX. UNIT 55 2.7 3.0 3.6 V 70/100 2.5 3.6 V V 2.2 VCC+0.3 -0.2 0.6 V -1 1 µA -1 1 µA 2.2 V 0.4 V 55 30 45 mA 70 25 35 mA 100 20 25 mA Tcycle= 4 5 mA 1µs Tcycle= 8 10 mA 500ns 0.3 0.5 mA -L 20 80 µA -LL 2 20 µA Notes: 1. Overshoot : Vcc+3.0v for pulse width less than 10ns. 2. Undershoot : Vss-3.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80042 UTRON UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.0 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 30pF, IOH/IOL = -1mA/2.1mA AC ELECTRICAL CHARACTERISTICS (TA = 0℃ to 70℃/-40℃ to 85℃(I)) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change LB , UB Access Time LB , UB to High-Z Output LB , UB to Low-Z Output SYMBOL tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ tBLZ UT62L12916-55 UT62L12916-70 MIN. 55 10 5 10 10 MIN. 70 10 5 10 10 MAX. 55 55 30 20 20 55 25 - MAX. 70 70 35 25 25 70 30 - UT62L12916-100 MIN. 100 10 5 10 10 UNIT MAX. 100 100 50 30 30 100 40 - ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z LB , UB Valid to End of Write SYMBOL tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW UT62L12916-55 UT62L12916-70 UT62L12916-100 MIN. 55 50 50 0 45 0 25 0 5 45 MIN. 70 60 60 0 55 0 30 0 5 60 MIN. 100 80 80 0 70 0 40 0 5 80 MAX. 30 - MAX. 30 - UNIT MAX. 40 - * These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80042 ns ns ns ns ns ns ns ns ns ns ns UTRON UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.0 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and CE2 and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE CE2 tBA LB , UB t BHZ tBLZ OE tOE t CHZ tCLZ tOLZ Dout tOHZ t OH High-Z Data Valid High-Z Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, CE2=high, LB or UB =low. 3.Address must be valid prior to or coincident with CE =low, CE2=high, LB or UB =low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80042 UTRON UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.0 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tW C Address tAW CE t CW CE2 t AS tW P tW R WE tBW LB , UB t W HZ t OW High-Z Dout (4) (4) tDW tDH Din Data Valid WRITE CYCLE 2 ( CE and CE2 Controlled) (1,2,5,6) tW C A ddress tA W CE tW R tA S tC W CE2 tW P WE tB W LB , U B tW H Z D out H igh-Z (4) tD W tD H D in D ata V alid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80042 UTRON UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.0 WRITE CYCLE 3 ( LB , UB Controlled) (1,2,5,6) tWC Address tAW CE tAS tCW tWR CE2 tWP WE tBW LB , UB tWHZ High-Z Dout tDW Din tDH Data Valid Notes : 1. WE , CE , LB , UB must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE , high CE2, low WE , LB or UB =low. 3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE , LB , UB low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80042 UTRON UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.0 DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃/-40℃ to 85℃(I)) PARAMETER Vcc for Data Retention SYMBOL VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tCDR TEST CONDITION CE ≧VCC-0.2V or CE2≦0.2V Vcc=1.5V -L - LL CE ≧VCC-0.2V or CE2≦0.2V See Data Retention Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 1 0.5 50 20 µA µA 0 - - ms 5 - - ms DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) ( CE controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR CE VIH tR CE ≧ VCC-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.5V VCC CE2 VCC(min.) VCC(min.) tCDR tR VIL CE2 ≦ 0.2V VIL Low Vcc Data Retention Waveform (3) ( LB , UB controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR LB,UB VIH tR LB,UB ≧ VCC-0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 VIH P80042 UTRON Rev. 1.0 UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 48 pin 6.0mmX8.0mm TFBGA Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80042 UTRON UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.0 ORDERING INFORMATION COMMERCIAL TEMPERATURE PART NO. ACCESS TIME ( ns ) UT62L12916BS-55L 55 UT62L12916BS-55LL 55 UT62L12916BS-70L 70 UT62L12916BS-70LL 70 UT62L12916BS-100L 100 UT62L12916BS-100LL 100 INDUSTRIAL TEMPERATURE PART NO. UT62L12916BS-55LI UT62L12916BS-55LLI UT62L12916BS-70LI UT62L12916BS-70LLI UT62L12916BS-100LI UT62L12916BS-100LLI STANDBY CURRENT ( µA ) typ. 20 2 20 2 20 2 ACCESS TIME ( ns ) 55 55 70 70 100 100 STANDBY CURRENT ( µA ) typ. 20 2 20 2 20 2 PACKAGE 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA PACKAGE 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA ORDERING INFORMATION (for lead free product) COMMERCIAL TEMPERATURE PART NO. ACCESS TIME ( ns ) UT62L12916BSL-55L 55 UT62L12916BSL-55LL 55 UT62L12916BSL-70L 70 UT62L12916BSL-70LL 70 UT62L12916BSL-100L 100 UT62L12916BSL-100LL 100 INDUSTRIAL TEMPERATURE PART NO. UT62L12916BSL-55LI UT62L12916BSL-55LLI UT62L12916BSL-70LI UT62L12916BSL-70LLI UT62L12916BSL-100LI UT62L12916BSL-100LLI STANDBY CURRENT ( µA ) typ. 20 2 20 2 20 2 ACCESS TIME ( ns ) 55 55 70 70 100 100 STANDBY CURRENT ( µA ) typ. 20 2 20 2 20 2 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 PACKAGE 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA PACKAGE 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA P80042 UTRON Rev. 1.0 UT62L12916/UT62L12916(I) 128K X 16 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 P80042