UTRON Rev. 1.0 UT61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM REVISION HISTORY REVISION DESCRIPTION Preliminary Rev. 0.1 Original. Rev. 1.0 1. Revised Standby current : 10/2mA(max) 0.5mA(typ.) 2. Delete ICC1, ICC2 3. Revised ISB : 30mA 3mA, ISB1:10mA 2mA, 4. Add ISB & ISB1 (typ.) : 1mA & 2mA 5. Add Overshoot : VIH ≤ +6.0V for t ≤ tRC /2. Undershoot : VIL ≤ -2.0V for t ≤ tRC /2. 6. Revised Data retention IDR (max) : 3mA 1Ma 7. Add order information for lead free product UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Date Oct.25,2002 May.20,2003 P80081 UTRON UT61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 FEATURES GENERAL DESCRIPTION The UT61L12816 is a 2,087,152-bit high speed CMOS static random access memory organized as 131,072 words by 16 bits. It is fabricated using high performance and high reliability CMOS technology. Fast access time : 10/12/15ns CMOS Low operating power Operating current : 260/240/220 mA (Icc max.) Standby current : 0.5 mA (typ.) Single 3.0V~3.6V power supply Operating temperature : Commercial : 0℃~70℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Data retention voltage : 2V (min.) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 44-pin 400mil TSOP-II The UT61L12816 operates from a single 3.0V ~ 3.6V power supply and all inputs and outputs are fully TTL compatible. It is designed to allow lower and upper byte access by data byte control ( LB 、 UB )。 FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K × 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 Lower Byte I/O9-I/O16 Upper Byte CE OE WE LB UB CONTROL CIRCUIT UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80081 UTRON UT61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 PIN CONFIGURATION PIN DESCRIPTION 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE A0 5 40 UB 6 39 LB 38 I/O16 37 I/O15 36 I/O14 35 I/O13 34 Vss 33 Vcc 32 I/O12 31 I/O11 CE UT61L12816 A4 I/O1 7 I/O2 8 I/O3 9 I/O4 10 Vcc 11 Vss 12 I/O5 13 I/O6 14 I/O7 15 30 I/O10 I/O8 16 29 I/O9 WE 17 28 NC A16 18 27 A8 A15 19 26 A9 A14 20 25 A10 A13 21 24 A11 A12 22 23 NC SYMBOL A0 - A16 I/O1 - I/O16 CE WE OE LB UB VCC VSS NC DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Lower-Byte Control Upper-Byte Control Power Supply Ground No Connection TSOP II TRUTH TABLE MODE Standby Output Disable Read Write Note: CE OE WE LB UB H X L L L L L L L L X X H H L L L X X X X X H H H H H L L L X H L X L H L L H L X H X L H L L H L L I/O OPERATION I/O1-I/O8 I/O9-I/O16 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT DIN High – Z High – Z DIN DIN DIN SUPPLY CURRENT ISB, ISB1 ICC ICC ICC H = VIH, L=VIL, X = Don't care. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80081 UTRON UT61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 0 to 70 -65 to 150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (TA = 0℃ to 70℃) PARAMETER SYMBOL TEST CONDITION Power Voltage Vcc *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VSS ≦VIN ≦VCC Output Leakage Current ILO VSS ≦VI/O ≦VCC; Output Disabled Output High Voltage VOH IOH= -4mA Output Low Voltage VOL IOL= 8mA Operating Power Supply Current ICC Standby Current (TTL) ISB Standby Current (CMOS) ISB1 Cycle time=min, 100%duty, I/O=0mA, CE =VIL MIN. 3.0 2.0 -0.3 -1 -1 2.4 -10 -12 -15 CE =VIH, other pins =VIL or VIH CE =VCC-0.2V, other pins at 0.2V or Vcc-0.2V - TYP. MAX. UNIT 3.3 3.6 V VCC+0.3 V 0.8 V 1 µA 1 µA V 0.4 V 260 mA 240 mA 220 mA 1 3 mA 0.5 2 Notes: 1. Overshoot : Vcc+3.0v for pulse width less than 8ns. 2. Undershoot : Vss-3.0v for pulse width less than 8ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80081 mA UTRON UT61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 3ns 1.5V CL = 30pF, IOH/IOL = -4mA / 8mA AC ELECTRICAL CHARACTERISTICS (TA =0℃ to 70℃) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change LB , UB Access Time SYMBOL tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH UT61L12816-10 MIN. MAX. 10 10 10 5 3 0 5 5 3 - tBA - 5 UT61L12816-12 MIN. MAX. 12 12 12 6 3 0 6 6 3 - 6 UT61L12816-15 MIN. MAX. 15 15 15 7 3 0 7 7 3 - 7 UNIT ns ns ns ns ns ns ns ns ns ns LB , UB to High-Z Output tBHZ* - 5 - 6 - 7 ns LB , UB to Low-Z Output tBLZ* 0 - 0 - 0 - ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z LB , UB Valid to End of Write UT61L12816-12 UT61L12816-15 SYMBOL UT61L12816-10 MIN. MAX. MIN. MAX. MIN. MAX. tWC 10 12 15 tAW 8 9 10 tCW 8 9 10 tAS 0 0 0 tWP 8 9 10 tWR 0 0 0 tDW 6 7 8 tDH 0 0 0 tOW* 3 3 3 tWHZ* 5 6 7 8 9 10 tBW *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80081 UNIT ns ns ns ns ns ns ns ns ns ns ns UTRON UT61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE tBA LB , UB t BHZ tBLZ OE t CHZ tOE tCLZ tOHZ t OH tOLZ Dout High-Z High-Z Data Valid Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, LB or UB =low. 3.Address must be valid prior to or coincident with CE =low, LB or UB =low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80081 UTRON UT61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tW C Address tAW CE t CW t AS tW P tW R WE tBW LB , UB t W HZ t OW High-Z Dout (4) tDW tDH (4) Din Data Valid WRITE CYCLE 2 ( CE Controlled) (1,2,5,6) tW C A ddress tA W CE tW R tA S tC W tW P WE tB W LB , U B tW H Z D out H igh-Z (4) tD W tD H D in D ata V alid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80081 UTRON UT61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 WRITE CYCLE 3 ( LB , UB Controlled) (1,2,5,6) tWC Address tAW CE tAS tCW tWR tWP WE tBW LB , UB tWHZ High-Z Dout tDW Din tDH Data Valid Notes : 1. WE , CE , LB , UB must be high during all address transitions. 2.A write occurs during the overlap of a low CE , low WE , LB or UB =low. 3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE , LB , UB low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80081