UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 REVISION HISTORY REVISION Preliminary Rev. 0.1 Rev. 1.0 Rev. 1.1 DESCRIPTION Original. 1.Add fast access time : 100ns 2.Revise “FEATURES” Operating : 40/25 40/35/25mA (Icc max.) 3.Revise “FEATURES” Standby : L -version : TA=0℃~50℃,20 uA(max.) 20 uA(TYP.) LL-version : TA=0℃~50℃, 3 uA(max.) 2 uA(TYP.) 4.Revise 36 TFBGA Outline Dimension ball size : 0.3mm 0.35mm 1.Revised “FEATURES” Operating current : 40/35/25mA(ICC max) 20/18/15mA (ICC typ.) 2.TRUTH TABLE & DC ELECTRICAL : Delete ISB2 3.Revised VTERM : -0.5 to Vcc+0.3V -0.5 to 4.6V 4.Added VOH : 2.7V at Vcc=3.0V 5.Revised DC (ICC max) 45/35/25mA 35/30/25mA (ICC typ.) 30/25/20mA 20/18/15mA 6.Add under/overshoot range of VIL & VIH 7.Revised AC tOHZ*@100ns (max): 35ns 30ns tWHZ*(max) :30/30/40 20/25/30ns 8.Revised “Data retention Characteristics” : IDR-LL (Typ.) : NA 1uA, IDR-L (Typ.) : NA 10uA IDR-LL (Max.) : 25uA 6uA tR(min) : 5ns ”tRC” 9.Add order information for lead free product UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Release Date Nov 28, 2001 Aug 30, 2002 Apr 28, 2003 P80082 UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 FEATURES GENERAL DESCRIPTION Fast access time : 55ns(max.) for Vcc=2.7V~3.6V 70/100ns(max.) for Vcc=2.5V~3.6V CMOS low power operation Operating : 20/18/15mA (TYP.) Standby : 20 uA(TYP.) L -version 2 uA(TYP.) LL-version Single 2.5V~3.6V power supply Operating temperature: Industrial : -40℃~85℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Data retention voltage: 1.5V (min) Package : 32-pin 8mm x 20mm TSOP-Ⅰ 32-pin 8mm x 13.4mm STSOP 36-pin 6mm × 8mm TFBGA The UT62L2568(I) is a 2,097,152-bit low power CMOS static random access memory organized as 262,144 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. The UT62L2568(I) is designed for very low power system applications. It is particularly well suited for battery back-up nonvolatile memory applications. It operates from a wide range of 2.5V~ 3.6V supply voltage. Easy memory expansion is provided by using two chip enable input ( CE ,CE2). And all inputs and three-state outputs are fully TTL compatible. FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K × 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 CE CE2 OE WE CONTROL CIRCUIT UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80082 UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 PIN CONFIGURATION A A0 B I/O 5 A1 A2 C E2 A3 A6 A8 WE A4 A7 I/O 1 NC A5 C I/O 6 D Vss Vcc E Vcc Vss F I/O 7 NC G I/O 8 OE CE H A9 A10 A11 I/O 2 A17 A16 A12 A11 A9 A8 A13 WE CE2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 I/O 3 A15 I/O 4 A13 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UT62L2568(I) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 A3 TSOP-1 / STSOP 1 2 3 4 5 6 TFBG A PIN DESCRIPTION SYMBOL A0 - A17 I/O1 - I/O8 CE ,CE2 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs WE OE VCC VSS NC Output Enable Input Power Supply Ground No Connection Write Enable Input UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80082 UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 TRUTH TABLE MODE Standby Output Disable Read Write Note: CE2 X L H H H CE H X L L L OE X X H L X WE X X H H L I/O OPERATION SUPPLY CURRENT ISB,ISB1 ISB,ISB1 ICC,ICC1,ICC2 ICC,ICC1,ICC2 ICC,ICC1,ICC2 High - Z High - Z High - Z DOUT DIN H = VIH, L=VIL, X = Don't care. ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Industrial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 -40 to 85 -65 to 150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.6V, TA = -40℃ to 85℃) PARAMETER SYMBOL TEST CONDITION Power Voltage VCC Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VIH ＊2 VIL ILI ILO VOH VOL ＊1 ICC Operating Current Standby Current (TTL) Standby Current (CMOS) MIN. 2.7 2.5 2.2 - 0.2 -1 VSS ≦VIN ≦VCC -1 VSS ≦VI/O ≦VCC, Output Disabled IOH= - 1mA (IOH= -0.5mA when Vcc<2.7V) 2.2 IOL= 2.1mA Cycle time=Min.100% duty, 55 70 CE =VIL and CE2 = VIH, 100 II/O =0mA 55 70/100 ICC2 100%duty, II/O=0mA, CE ≦0.2V and CE2≧Vcc-0.2V, other pins at 0.2V or Vcc-0.2V ISB CE =VIH or CE2 = VIL ICC1 ISB1 CE =VCC-0.2V or CE2=0.2V, other pins at 0.2V or Vcc-0.2V TCycle= 1µs TCycle= 500ns -L -LL - TYP. MAX. UNIT 3.0 3.6 V 3.0 3.6 V Vcc+0.3 V 0.6 V 1 µA 1 µA 2.7 V 0.4 V 20 35 mA 18 30 mA 15 25 mA 4 5 mA - 8 10 - 0.3 20 2 0.5 80 10 mA mA µA µA Notes: 1. Overshoot : Vcc+3.0v for pulse width less than 10ns. 2. Undershoot : Vss-3.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80082 UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3V 5ns 1.5V CL = 30pF+1TTL, IOH= -1mA, IOL= 2.1mA AC ELECTRICAL CHARACTERISTICS ( TA = - 40℃ to 85℃) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYMBOL tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH UT62L2568(I)-55 UT62L2568(I)-70 UT62L2568(I)-100 UNIT VCC = 2.7V~3.6V VCC = 2.5V~3.6V VCC = 2.5V~3.6V MIN. MAX. MIN. MAX. MIN. MAX. 55 70 100 55 70 100 55 70 100 30 35 50 10 10 10 5 5 5 20 25 30 20 25 30 10 10 10 - ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z SYMBOL tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* UT62L2568(I)-55 UT62L2568(I)-70 UT62L2568(I)-100 UNIT VCC = 2.7V~3.6V VCC = 2.5V~3.6V VCC = 2.5V~3.6V MIN. MAX. MIN. MAX. MIN. MAX. 55 70 100 50 60 80 50 60 80 0 0 0 45 55 70 0 0 0 25 30 40 0 0 0 5 5 5 20 25 30 ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80082 UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and CE2 and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE CE2 OE tCHZ tOE tOHZ tCLZ tOLZ Dout t OH High-Z Data Valid High-Z Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, CE2=high. 3.Address must be valid prior to or coincident with CE =low, CE2=high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80082 UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tW C Address tAW CE t CW CE2 t AS tW P tW R WE t W HZ Dout tOW High-Z (4) (4) tDW Din t DH Data Valid WRITE CYCLE 2 ( CE and CE2 Controlled) (1,2,5,6) tW C A ddress tA W CE tW R tA S tC W CE2 tW P WE tW H Z D out H igh-Z (4) tD W tD H D in D ata V alid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80082 UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 Notes : 1. WE , CE must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE , high CE2, low WE . 3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. DATA RETENTION CHARACTERISTICS (TA = - 40℃ to 85℃) PARAMETER Vcc for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time SYMBOL VDR IDR tCDR TEST CONDITION CE 1 ≧ VCC-0.2V or CE2≦0.2V Vcc=1.5V -L CE 1 ≧ VCC-0.2V - LL or CE2≦0.2V See Data Retention Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 10 80 µA - 1 6 µA 0 - - ns tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) ( CE controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR CE VIH tR CE ≧ VCC-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.5V VCC CE2 VCC(min.) VCC(min.) tCDR tR VIL CE2 ≦ 0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 VIL P80082 UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 PACKAGE OUTLINE DIMENSION 32 pin 8mm x 20mm TSOP-I Package Outline Dimension UNIT SYMBOL A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 ±0.004 0.315 ±0.004 0.020 (TYP) 0.787 ±0.008 0.0197 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ∼5 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 ±0.10 8.00 ±0.10 0.50 (TYP) 20.00 ±0.20 0.50 ±0.10 0.08 ±0.10 0.076 (MAX) o o 0 ∼5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 P80082 UTRON UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 32 pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 12° (2x) 32 16 17 12° (2x) b E e 1 "A" Seating Plane D y 12° (2X) 16 17 0.254 A2 c A GAUGE PLANE A1 0 SEATING PLANE L 12° (2X) L1 "A" DATAIL VIEW 1 32 UNIT SYMBOL A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) MM(REF) 0.049 (MAX) 1.25 (MAX) 0.005 ±0.002 0.130 ±0.05 0.039 ±0.002 1.00 ±0.05 0.008 ±0.01 0.20±0.025 0.005 (TYP) 0.127 (TYP) 0.465 ±0.004 11.80 ±0.10 0.315 ±0.004 8.00 ±0.10 0.020 (TYP) 0.50 (TYP) 0.528±0.008 13.40 ±0.20. 0.0197 ±0.004 0.50 ±0.10 0.0315 ±0.004 0.8 ±0.10 0.003 (MAX) 0.076 (MAX) o o o o 0 ∼5 0 ∼5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80082 UTRON Rev. 1.1 UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM 36 pin 6mm×8mm TFBGA Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 P80082 UTRON Rev. 1.1 UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION INDUSTRIAL TEMPERATURE PART NO. ACCESS TIME (ns) UT62L2568LC-55LI 55 UT62L2568LC-55LLI 55 UT62L2568LC-70LI 70 UT62L2568LC-70LLI 70 UT62L2568LC-100LI 100 UT62L2568LC-100LLI 100 UT62L2568LS-55LI 55 UT62L2568LS-55LLI 55 UT62L2568LS-70LI 70 UT62L2568LS-70LLI 70 UT62L2568LS-100LI 100 UT62L2568LS-100LLI 100 UT62L2568BS-55LI 55 UT62L2568BS-55LLI 55 UT62L2568BS-70LI 70 UT62L2568BS-70LLI 70 UT62L2568BS-100LI 100 UT62L2568BS-100LLI 100 STANDBY CURRENT (µA) TYP. 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 PACKAGE 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA ORDERING INFORMATION (for lead free product) INDUSTRIAL TEMPERATURE PART NO. ACCESS TIME (ns) UT62L2568LCL-55LI 55 UT62L2568LCL-55LLI 55 UT62L2568LCL-70LI 70 UT62L2568LCL-70LLI 70 UT62L2568LCL-100LI 100 UT62L2568LCL-100LLI 100 UT62L2568LSL-55LI 55 UT62L2568LSL-55LLI 55 UT62L2568LSL-70LI 70 UT62L2568LSL-70LLI 70 UT62L2568LSL-100LI 100 UT62L2568LSL-100LLI 100 UT62L2568BSL-55LI 55 UT62L2568BSL-55LLI 55 UT62L2568BSL-70LI 70 UT62L2568BSL-70LLI 70 UT62L2568BSL-100LI 100 UT62L2568BSL-100LLI 100 STANDBY CURRENT (µA) TYP. 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 PACKAGE 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA P80082 UTRON Rev. 1.1 UT62L2568(I) 256K X 8 BIT LOW POWER CMOS SRAM This page is left blank intentionally. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 13 P80082