ICMIC X24165V

ICmic
TM
This X24165 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
IC MICROSYSTEMS
X24165
16K
2048 x 8 Bit
2
Advanced 2-Wire Serial E PROM with Block LockTM Protection
FEATURES
•2.7V to 5.5V Power Supply
•Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1∝A
•Internally Organized 2048 x 8
•New Programmable Block Lock Protection
—Software Write Protection
—Programmable Hardware Write Protect
•Block Lock (0, 1/4, 1/2, or all of the E2PROM
array)
DESCRIPTION
2
The X24165 is a CMOS 16,384 bit serial E PROM,
internally organized 2048 x 8. The X24165 features a
serial interface and software protocol allowing operation on a
simple two wire bus.
Three device select inputs (S0, S1, S2) allow up to eight
devices to share a common two wire bus.
A Write Protect Register at the highest address location,
7FFh, provides three new write protection
features: Software Write Protect, Block Write Protect, and
Hardware Write Protect. The Software Write
Protect feature prevents any nonvolatile writes to the X24165
until the WEL bit in the write protect register is
•2 Wire Serial Interface
•Bidirectional Data Transfer Protocol
•32 Byte Page Write Mode
set. The Block Write Protection feature allows the user to
individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
—Minimizes Total Write Time Per Byte
•Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
•High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
•Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead TSSOP
FUNCTIONAL DIAGRAM
the user to install the X24165 with WP tied to VCC,
program the entire memory array in place, and then
enable the hardware write protection by programming a
WPEN bit in the write protect register. After this,
selected blocks of the array, including the write protect
register itself, are permanently write protected.
2
Xicor E PROMs are designed and tested for applications
requiring extended endurance. Inherent data
WP
H.V. GENERATION
TIMING &
START CYCLE
CONTROL
V
CC
V
SS
SDA
WRITE PROTECT
REGISTER AND
START
STOP
LOGIC
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
SCL
LOAD
+COMPARATOR
S
2
INC
2
E PROM
64 X 256
XDEC
WORD
ADDRESS
COUNTER
S
1
S
0
R/W
YDEC
8
CK
PIN
D
OUT
ACK
Xicor, 1995, 1996 Patents Pending
6551-2.5 5/13/96 T1/C10/D0 NS
1
DATA REGISTER
D
OUT
6551 ILL F01.1
Characteristics subject to change without notice
X24165
PIN CONFIGURATIONS
PIN DESCRIPTIONS
Serial Clock (SCL)
8-LEAD DIP & SOIC
The SCL input is used to clock all data into and out of the
device.
S
0
S
1
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or open
collector outputs.
S
2
V
SS
Up Resistor selection graph at the end of this data
sheet.
bit in the write protect register is set HIGH, write
protection is enabled, and nonvolatile writes are
disabled to the selected blocks as well as the write
protect register itself.
PIN NAMES
Description
SCL
Serial Clock
WP
Write Protect
VSS
Ground
VCC
Supply Voltage
NC
No Connect
V
CC
WP
SCL
SDA
NC
NC
3
4
12
X24165 11
5
6
7
10
9
8
V
CC
WP
NC
NC
NC
SCL
SDA
6551 ILL F02.5
protection is disabled and the X24165 can be written
normally. When this input is held HIGH, and the WPEN
Serial Data
14
13
V
SS
Write Protect (WP)
The write protect input controls the hardware write
protect feature. When held LOW, hardware write
SDA
6
5
1
2
S
2
allows up to eight X24165’s to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to VSS or VCC as appropriate.
If actively driven, they must be driven with
CMOS levels (driven to VCC or VSS).
Device Select Inputs
X24165
S
0
S
1
NC
Device Select (S0, S1, S2)
The device select inputs (S0,S1,S2) are used to set the
first three bits of the 8-bit slave address. This
S0, S1, S2
3
4
8
7
14-LEAD TSSOP
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
Symbol
1
2
6551 FRM T01.2
2
X24165
DEVICE OPERATION
The X24165 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer to
Figures 1 and 2.
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
Start Condition
All command are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is
the clock for both transmit and receive operations.
Therefore, the X24165 will be considered a slave in all
HIGH. The X24165 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
applications.
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
6551 ILL F04
Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)
(6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum
the device requires to perform the internal write operation.
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3
6551 ILL F05
X24165
The X24165 will respond with an acknowledge after
recognition of a start condition and its slave address. If both
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
the device and a write operation have been selected,
the X24165 will respond with an acknowledge after the
receipt of each subsequent eight-bit word.
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
In the read mode the X24165 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the X24165 will
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the
continue to transmit data. If an acknowledge is not
detected, the X24165 will terminate further data trans
-missions.
The master must then issue a stop condition to return the
X24165 to the standby power mode and place the device into
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
6551 ILL F06
4
X24165
The last bit of the slave address defines the operation to be
performed. When set HIGH a read operation is
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
selected, when set LOW a write operation is selected.
next three bits are the device select bits. A system could
have up to eight X24165’s on the bus. The eight
addresses are defined by the state of the S0, S1 and S2
inputs. S1 of the slave address must be the inverse
Following the start condition, the X24165 monitors the SDA
bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24165 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24165 will execute a read or write operation.
of the S1 input pin.
Figure 4. Slave Address
DEVICE
TYPE
IDENTIFIER
1
S
2
S
1
WRITE OPERATIONS
Byte Write
HIGH ORDER
WORD
DEVICE
SELECT
ADDRESS
S
0
A10
A9
A8
For a write operation, the X24165 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of 2048
words in the array. Upon receipt of the word address, the
R/W
X24165 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowledge
6551 ILL F07.2
The master then terminates the transfer by generating a
stop condition, at which time the X24165 begins
the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the X24165 inputs
The next three bits of the slave address are an extension
of the array’s address and are concatenated with
the eight bits of address in the word address field,
providing direct access to the whole 2048 x 8 array.
are disabled, and the device will not respond to any requests
from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.
Figure 5. Byte Write
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24165
S
T
A
R
T
SLAVE
ADDRESS
WORD
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
A
C
K
A
C
K
6551 ILL F08
5
X24165
Flow 1. ACK Polling Sequence
Page Write
The X24165 is capable of a 32 byte page write operation.
It is initiated in the same manner as the byte write
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
operation, but instead of terminating the write cycle after
the first data word is transferred, the master can
transmit up to fifteen more words. After the receipt of
each word, the X24165 will respond with an acknowledge.
ISSUE
START
After the receipt of each word, the five low order ad- dress
bits are internally incremented by one. The high order bits
of the word address remain constant. If the master should
transmit more than 32 words prior to generating the
stop condition, the address counter will “roll over” and
the previously written data will be over- written. As with
the byte write operation, all inputs are disabled until
completion of the internal write cycle. Refer to Figure 6
for the address, acknowledge and data transfer sequence.
ISSUE SLAVE
ADDRESS AND R/W = 0
ACK
RETURNED?
ISSUE STOP
NO
YES
Acknowledge Polling
The Max Write Cycle Time can be significantly reduced
using Acknowledge Polling. To initiate Acknowledge
NEXT
OPERATION
NO
A WRITE?
Polling, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
YES
the device is still busy with the high voltage cycle, then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
ISSUE BYTE
ADDRESS
ISSUE STOP
PROCEED
PROCEED
Refer to Flow 1.
6551 ILL F09
Figure 6. Page Write
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24165
S
T
A
R
T
SLAVE
ADDRESS
WORD ADDRESS (n)
DATA n
DATA n+1
S
T
O
P
DATA n+31
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
6551 ILL F10.1
6
X24165
terminated by the master; by not responding with an acknow
-ledge and by issuing a stop condition. Refer to
READ OPERATIONS
Read operations are initiated in the same manner as
Write operations with the exception that the R/W bit
Figure 7 for the sequence of address, acknowledge and
data transfer.
of the slave address is set HIGH. There are three basic read
operations: current address read, random read
and sequential read.
Random Read
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
the slave address with the R / W bit set HIGH, the master
must first perform a “dummy” write operation.
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
The master issues the start condition, and the slave address with the R/W bit set LOW, followed by the word
ninth clock cycle and then issue a stop condition.
address it is to read. After the word address acknowledge, the
master immediately reissues the start condition
Current Address Read
Internally the X24165 contains an address counter that
maintains the address of the last word read, incremented
and the slave address with the R/W bit set HIGH. This will be
followed by an acknowledge from the
by one or the exact address of the last word written.
Therefore, if the last access read was to address n, the
X24165 and then by the eight-bit word. The read operation is
terminated by the master; by not responding
next read operation would access data from address
n + 1. Upon receipt of the slave address with the R/W
with an acknowledge and by issuing a stop condition. Refer
to Figure 8 for the address, acknowledge and
data transfer sequence.
set HIGH, the X24165 issues an acknowledge and
transmits the eight-bit word. The read operation is
Figure 7. Current Address Read
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
P
S
A
C
K
BUS ACTIVITY:
X24165
DATA
6551 ILL F11
Figure 8. Random Read
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24165
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
WORD
ADDRESS n
S
S
T
O
P
SLAVE
ADDRESS
P
S
A
C
K
A
C
K
A
C
K
DATA n
6551 ILL F12.1
7
X24165
The data output is sequential, with the data from
address n followed by the data from n + 1. The address
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first word is
counter for read operations increments all address bits,
allowing the entire memory contents to be serially read
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
during one operation. At the end of the address space
(address 2047), the counter “rolls over” to 0 and the
it requires additional data. The X24165 continues to
output data for each acknowledge received. The read
X24165 continues to output data for each acknowledge
received. Refer to Figure 9 for the address,
operation is terminated by the master; by not responding
with an acknowledge and then issuing a
acknowledge and data transfer sequence.
stop condition.
Figure 9. Sequential Read
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
A
C
K
A
C
K
S
T
O
P
A
C
K
SDA LINE
BUS ACTIVITY:
X24165
P
A
C
K
DATA n
DATA n+1
DATA n+2
DATA n+x
6551 ILL F13
Figure 10. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
MASTER
TRANSMITTER
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
6551 ILL F14
8
X24165
WEL and RWEL are volatile latches that power-up in the
LOW (disabled) state. A write to any address other
than 7FFh, where the Write Protect Register is located,
will be ignored (no ack) until the WEL bit is set
HIGH. The WEL bit is set by writing 0000001x to
address 7FFh. Once set, WEL remains HIGH until
either reset (by writing 00000000 to 7FFh) or until the part
powers-up again. The RWEL bit controls writes to
WRITE PROTECT REGISTER
The Write Protect Register (WPR) is located at the
highest address, 7FFh.
Figure 11. Write Protect Register
WPR (Addr = 7FFh)
7
6
5
4
3
2
1
0
WPEN
0
0
BP1
BP0
RWEL
WEL
0
the block protect bits. RWEL is set by first setting WEL = 1
and then writing 0000011x to address 7FFh.
RWEL must be set in order to change the block protect bits,
BP0 and BP1, or the WPEN bit. RWEL is reset
6551 ILL F15.1
WPR.1 = WEL –
when the block protect or WPEN bits are changed, or
when the part powers-up again.
Write Enable Latch (Volatile)
0 = Write enable latch reset, writes disabled 1 =
Write enable latch set, writes enabled
Programming the BP or WPEN Bits
A three step sequence is required to change the
non-volatile Block Protect or Write Protect Enable:
If WEL = 0 then “no ACK” after first byte of input data.
WPR.2 = RWEL –
1) Set WEL = 1 (write 00000010 to address 7FFh,
volatile write cycle)
Register Write Enable Latch (Volatile)
0 = Register write enable latch reset, writes
disabled
(Start)
1 = Register write enable latch set, writes enabled
2) Set RWEL = 1 (write 00000110 to address 7FFh,
volatile write cycle)
WPR.3, WPR.4 = BP0, BP1 –
Block Protect Bits (Nonvolatile)
Block Protect section for definition)
(See
(Start)
3) Set BP1, BP0, and/or WPEN bits (Write w00yz010 to
address 7FFh)
WPR.7 = WPEN –
Write Protect Enable Bit (Nonvolatile)
(See Hardware Write Protect section for definition)
w = WPEN, y = BP1, Z = BP0,
Writing to the Write Protect Register
The Write Protect Register is written by performing a
random write of one byte directly to address, 7FFh. If a
page write is performed starting with any address other
than 7FFh, the byte in the array at address 7FFh
(Stop)
Step 3 is a nonvolatile write cycle, requiring 10ms to complete.
RWEL is reset (0) by this write cycle,
requiring another write cycle to set RWEL again before the
block protect bits can be changed. RWEL must be
will be written instead of the Write Protect Register
(assuming writes are not disabled by the block protect
0 in step 3; if w00yz110 is written to address 7FFh,
RWEL is set but WPEN, BP1 and BP0 are not
register).
changed (the device remains at step 2).
The state of the Write Protect Register can be read by
performing a random read at address 7FFh at any
time. If a sequential read starting at any other address than
7FFh is performed, the contents of the byte in the
array at 7FFh is read out instead of the Write Protect
Register.
9
X24165
Block Protect Bits
The Block Protect Bits BP0 and BP1 determine which
blocks of the memory are write-protected:
Programmable Hardware Write Protect
The Write Protect (WP) pin and the Write Protect Enable
(WPEN) bit in the Write Protect Register
Table 1. Block Protect Bits
control the programmable hardware write protect feature.
Hardware write protection is enabled when the
WP pin and the WPEN bit are both HIGH, and
disabled when either the WP pin is LOW or the WPEN
Protected
Addresses
BP1
BP0
0
0
None
0
1
600h–7FFh
Upper 1/4
1
0
400h–7FFh
Upper 1/2
0000h–7FFh
Full Array (WPR
not included)
1
1
bit is LOW. When the chip is hardware write-protected,
non-volatile writes are disabled to the Write Protect
Register, including the BP bits and the WPEN bit itself, as
well as to block-protected sections in the memory
array. Only the sections of the memory array that are not
block-protected can be written. Note that since the
WPEN bit is write-protected, it cannot be changed back
to a LOW state, and write protection is disabled
6551 FRM T02
as long as the the WP pin is held HIGH. Table 2
defines the write protection status for each state of
WPEN and WP.
Table 2. Write Protect Status Table
Memory Array
(Not Block
Protected)
Memory Array
(Block Protected)
BP Bits
WPEN Bit
Writable
Protected
Writable
Writable
0
Writable
Protected
Writable
Writable
1
Writable
Protected
Protected
Protected
WP
WPEN
0
X
X
1
6551 FRM T03
10
X24165
*COMMENT
Stresses above those listed under “Absolute Maximum”
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X24165 ....................................... –65°C to +135°C
Storage Temperature ........................ –65°C to +150°C
Voltage on any Pin with
Respect to VSS .................................... –1V to +7V
D.C. Output Current ..............................................5mA
Lead Temperature (Soldering, 10 Seconds) ...... 300°C
Ratings” may cause permanent damage to the device. This is
a stress rating only and the functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Military
Min.
Max.
Supply Voltage
Limits
0°C
+70°C
X24165
4.5V to 5.5V
–40°C
+85°C
X24165-2.7
2.7V to 5.5V
–55°C
+125°C
6551 FRM T05
6551 FRM T04
D.C. OPERATING CHARACTERISTICS
Limits
Symbol
Parameter
Min.
Max.
Units
ICC1
VCC Supply Current (Read)
1
mA
ICC2
VCC Supply Current (Write)
3
mA
ISB1 (1)
VCC Standby Current
50
∝A
1
∝A
Test Conditions
SCL = VCC X 0.1/VCC X 0.9 Levels @
100KHz, SDA = Open, All Other
Inputs = VSS or VCC – 0.3V
SCL = SDA = VCC, All Other
Inputs = VSS or VCC – 0.3V,
VCC = 5V ± 10%
ISB2 (1)
VCC Standby Current
SCL = SDA = VCC, All Other
Inputs = VSS or VCC – 0.3V,
VCC = 2.7V
ILI
Input Leakage Current
10
∝A
VIN = VSS to VCC
ILO
Output Leakage Current
10
∝A
VOUT = VSS to VCC
VlL (2)
Input LOW Voltage
–1
VCC x 0.3
V
VIH (2)
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output LOW Voltage
0.4
V
IOL = 3mA, VCC = 4.5V
6551 FRM T06.1
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
CI/O (3)
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN (3)
Input Capacitance (S1, S2, SCL)
6
pF
VIN = 0V
6551 FRM T07.1
Notes: (1)Must perform a stop command prior to measurement.
(2)VIL min. and VIH max. are for reference only and are not 100% tested. (3)This
parameter is periodically sampled and not 100% tested.
11
X24165
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
VCC x 0.1 to VCC x 0.9
Input Pulse Levels
Input Rise and
Fall Times
5V
10ns
Input and Output
Timing Levels
1533Ο
OUTPUT
VCC X 0.5
6551 FRM T08.1
100pF
6551 ILL F16
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read
& Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
0
100
KHz
100
ns
3.5
∝s
fSCL
SCL Clock Frequency
TI
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL LOW to SDA Data Out Valid
0.3
tBUF
Time the Bus Must Be Free Before a
New Transmission Can Start
4.7
∝s
tHD:STA
Start Condition Hold Time
4
∝s
tLOW
Clock LOW Period
4.7
∝s
tHIGH
Clock HIGH Period
4
∝s
tSU:STA
Start Condition Setup Time
a Repeated Start Condition)
4.7
∝s
tHD:DAT
Data In Hold Time
0
∝s
tSU:DAT
Data In Setup Time
250
ns
tR
SDA and SCL Rise Time
1
∝s
tF
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
4.7
∝s
tDH
Data Out Hold Time
300
ns
(for
6551 FRM T09.1
POWER-UP TIMING
(4)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
5
ms
6551 FRM T10
Notes: (4)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
These parameters are periodically sampled and not 100% tested.
12
X24165
Bus Timing
t
t
F
t
HIGH
t
LOW
R
SCL
t
t
SU:STA
HD:STA
t
t
HD:DAT
t
SU:DAT
SU:STO
SDA IN
t
t
AA
t
DH
BUF
SDA OUT
6551 ILL F17
Write Cycle Limits
Symbol
tWR
Parameter
(6)
(5)
Min.
Typ.
Write Cycle Time
5
Max.
Units
10
ms
6551 FRM T11.1
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
X24165 bus interface circuits are disabled, SDA is
allowed to remain HIGH, and the device does not
erase/program cycle. During the write cycle, the
respond to its slave address.
Bus Timing
SCL
SDA
ACK
8th BIT
WORD n
t
WR
STOP
CONDITION
6551 ILL F18
START
CONDITION
Notes: (5)Typical values are for TA = 25°C and nominal supply voltage (5V).
(6)tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
SYMBOL TABLE
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
WAVEFORM
RESISTANCE (KΟ)
120
V
R
MIN
100
80
=
R
MAX
=
CC MAX
I
OL MIN
=1.8KΟ
t
R
C
BUS
MAX.
RESISTANCE
60
40
20
MIN.
RESISTANCE
0
0
20
40
60
80100120
BUS CAPACITANCE (pF)
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
Will change
from LOW
to HIGH
to HIGH
May change
from HIGH
Will change
from HIGH
to LOW
to LOW
Don’t Care:
Changes
Changing:
State Not
Allowed
Known
N/A
Center Line
is High
Impedance
6551 ILL F19
13
X24165
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.060 (1.52)
0.020 (0.51)
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.015 (0.38)
MAX.
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2.
PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
14
X24165
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.050" TYPICAL
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
FOOTPRINT
8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
15
X24165
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169
(4.3) .177
(4.5)
.252 (6.4) BSC
.193
(4.9) .200
(5.1)
.047 (1.20)
.0075
(.19) .0118
(.30)
.002
(.05) .006
(.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019
(.50) .029
(.75)
Detail A (20X)
.031
(.80) .041
(1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F32
16
X24165
ORDERING INFORMATION
X24165
P
T G -V
VCC Range
Blank = 4.5V to 5.5V
2.7 = 2.7V to 5.5V
Device
G=RoHS Compliant Lead Free package
Blank = Standard package. Non lead free
Temperature Range
Blank = 0°C to +70°C
I = –40°C to +85°C
M = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC (JEDEC)
V = 14-Lead TSSOP
Part Mark Convention
X24165
XG
X
P = 8-Lead Plastic DIP
Blank = 8-Lead SOIC (JEDEC)
V = 14-Lead TSSOP
G = RoHS compliant lead free
Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from
patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production
and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses
are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign
patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of
the life support device or system, or to affect its safety or effectiveness.
17