ETC XCS05XL

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Spartan and Spartan-XL Families
Field Programmable Gate Arrays
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DS060 (v1.5) March 2, 2000
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Introduction
Product Specification
•
The Spartan™ series is the first high-volume production
FPGA solution to deliver all the key requirements for ASIC
replacement up to 40,000 gates. These requirements
include high performance, on-chip RAM, core solutions and
prices that, in high volume, approach and in many cases
are equivalent to mask programmed ASIC devices.
The Spartan series is the result of more than 14 years of
FPGA design experience and feedback from thousands of
customers. By streamlining the Spartan series feature set,
leveraging advanced hybrid process technologies and
focusing on total cost management, the Spartan series
delivers the key features required by ASIC and other highvolume logic users while avoiding the initial cost, long
development cycles and inherent risk of conventional
ASICs. The Spartan and Spartan-XL families in the
Spartan series have ten members, as shown in Table 1.
•
•
Spartan and Spartan-XL Features
Note: The Spartan series devices described in this data
sheet include the 5V Spartan family and the 3.3V
Spartan-XL family. See the separate data sheet for the
2.5V Spartan-II family.
•
•
•
•
•
•
•
•
First ASIC replacement FPGA for high-volume
production with on-chip RAM
Advanced process technology
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCORE™ and LogiCORE™
predefined solutions available
Unlimited reprogrammability
Low cost
System level features
- Available in both 5V and 3.3V versions
- On-chip SelectRAMTM memory
- Fully PCI compliant
- Low power segmented routing architecture
- Full readback capability for program verification and
internal node observability
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal networks
- IEEE 1149.1-compatible Boundary Scan logic
Versatile I/O and packaging
- Low cost plastic packages available in all densities
- Footprint compatibility in common packages
- Individually programmable output slew-rate control
maximizes performance and reduces noise
- Zero input register hold time simplifies system timing
Fully supported by powerful Xilinx development system
- Foundation Series: Integrated, shrink-wrap software
- Alliance Series: Dozens of PC and workstation third
party development systems supported
- Fully automatic mapping, placement and routing
Additional Spartan-XL Features
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional mux or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compatible
Enhanced Boundary Scan
Express Mode configuration
Chip scale packaging
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
Device
XCS05 & XCS05XL
XCS10 & XCS10XL
XCS20 & XCS20XL
XCS30 & XCS30XL
XCS40 & XCS40XL
Logic
Cells
238
466
950
1368
1862
Max
System
Gates
5,000
10,000
20,000
30,000
40,000
Typical
Gate Range
(Logic and RAM)*
2,000 - 5,000
3,000 - 10,000
7,000 - 20,000
10,000 - 30,000
13,000 - 40,000
CLB
Matrix
10 x 10
14 x 14
20 x 20
24 x 24
28 x 28
Total
CLBs
100
196
400
576
784
Number
of
Flip-flops
360
616
1,120
1,536
2,016
Max.
Available
User I/O
77
112
160
192
224
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
IOB
IOB
IOB
IOB
BSCAN
IOB
Spartan series FPGAs can be used where hardware must
be adapted to different user applications. FPGAs are ideal
The Spartan/XL families leverage the highly successful
XC4000 architecture with many of that family’s features and
benefits. Technology advancements have been derived
from the XC4000XLA process developments.
IOB
The devices are customized by loading configuration data
into internal static memory cells. Re-programming is possible an unlimited number of times. The values stored in
these memory cells determine the logic functions and interconnections implemented in the FPGA. The FPGA can
either actively read its configuration data from an external
serial PROM (Master Serial mode), or the configuration
data can be written into the FPGA from an external device
(Slave Serial mode).
Spartan series devices achieve high-performance, low-cost
operation through the use of an advanced architecture and
semiconductor
technology.
Spartan
and
Spartan-XL devices provide system clock rates exceeding
80 MHz and internal performance in excess of 150 MHz. In
contrast to other FPGA devices, the Spartan series offers
the most cost-effective solution while maintaining leading-edge performance. In addition to the conventional benefit of high volume programmable logic solutions, Spartan
series FPGAs also offer on-chip edge-triggered single-port
and dual-port RAM, clock enables on all flip-flops, fast carry
logic, and many other features.
IOB
Spartan series FPGAs are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources (routing channels), and surrounded by a perimeter of programmable Input/Output
Blocks (IOBs), as seen in Figure 1. They have generous
routing resources to accommodate the most complex interconnect patterns.
for shortening design and development cycles, and also
offer a cost-effective solution for production rates well
beyond 50,000 systems per month.
IOB
General Overview
IOB
OSC
IOB
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
IOB
Routing Channels
IOB
IOB
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
VersaRing Routing Channel
IOB
IOB
IOB
IOB
IOB
IOB
IOB
RDBK
IOB
IOB
IOB
START
-UP
Rev 2.0
Figure 1: Basic FPGA Block Diagram
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Logic Functional Description
fied block diagram in Figure 2. There are three look-up
tables (LUT) which are used as logic function generators,
two flip-flops and two groups of signal steering multiplexers.
There are also some more advanced features provided by
the CLB which will be covered in the “Advanced Features
Description” on page 12.
The Spartan series uses a standard FPGA structure as
shown in Figure 1 on page 2. The FPGA consists of an
array of configurable logic blocks (CLBs) placed in a matrix
of routing channels. The input and output of signals is
achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels.
•
•
•
Function Generators
Two 16 x 1 memory look-up tables (F-LUT and G-LUT) are
used to implement 4-input function generators, each offering unrestricted logic implementation of any Boolean function of up to four independent input signals (F1 to F4 or G1
to G4). Using memory look-up tables the propagation delay
is independent of the function implemented.
CLBs provide the functional elements for implementing
the user’s logic.
IOBs provide the interface between the package pins
and internal signal lines.
Routing channels provide paths to interconnect the
inputs and outputs of the CLBs and IOBs.
A third 3-input function generator (H-LUT) can implement
any Boolean function of its three inputs. Two of these inputs
are controlled by programmable multiplexers (see box "A"
of Figure 2). These inputs can come from the F-LUT or
G-LUT outputs or from CLB inputs. The third input always
comes from a CLB input. The CLB can, therefore, implement certain functions of up to nine inputs, like parity
checking. The three LUTs in the CLB can also be combined
to do any arbitrarily defined Boolean function of five inputs.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA.
Configurable Logic Blocks (CLBs)
The CLBs are used to implement most of the logic in an
FPGA. The principal CLB elements are shown in the simpli-
B
G-LUT
G4
G4
G2
Logic
G3 Function
G
of
G2 G1-G4
G1
G1
G3
SR
D
Q
YQ
CK
EC
H-LUT
Logic
Function
H1 of
H
F,G,H1
F
H1
DIN
F4
F4
F2
Logic
F3 Function
F
of
F2 F1-F4
F1
F1
F3
Y
G
SR
SR
A
D
Q
XQ
CK
EC
F-LUT
K
X
Multiplexer Controlled
by Configuration Program
EC
Rev 1.0
Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
A CLB can implement any of the following functions:
•
•
•
•
SR
Any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables1
Any single function of five variables
Any function of four variables together with some
functions of six variables
Some functions of up to nine variables.
GND
GSR
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
SD
D
RD
EC
Vcc
Each CLB contains two flip-flops that can be used to register (store) the function generator outputs. The flip-flops and
function generators can also be used independently (see
Figure 2 on page 3). The CLB input DIN can be used as a
direct input to either of the two flip-flops. H1 can also drive
either flip-flop via the H-LUT with a slight additional delay.
The two flip-flops have common clock (CK), clock enable
(EC) and set/reset (SR) inputs. Internally both flip-flops are
also controlled by a global initialization signal (GSR) which
is described in detail in “Global Signals: GSR and GTS” on
page 18.
Latches (Spartan-XL only)
The Spartan-XL CLB storage elements can also be configured as latches. The two latches have common clock (K)
and clock enable (EC) inputs. Functionality of the storage
element is described in Table 2.
Table 2: CLB Storage Element Functionality
Flip-Flop
Operation
Latch Operation
(Spartan-XL)
Both
Legend:
X
__/
SR
0*
1*
Q
CK
Flip-Flops
Mode
Power-Up or
GSR
Q
D
Rev 1.1
Multiplexer Controlled
by Configuration Program
Figure 3: CLB Flip-Flop Functional Block Diagram
Clock Input
Each flip-flop can be triggered on either the rising or falling
clock edge. The CLB clock line is shared by both flip-flops.
However, the clock is individually invertible for each flip-flop
(see CK path in Figure 3). Any inverter placed on the clock
line in the design is automatically absorbed into the CLB.
Clock Enable
The clock enable line (EC) is active High. The EC line is
shared by both flip-flops in a CLB. If either one is left disconnected, the clock enable for that flip-flop defaults to the
active state. EC is not invertible within the CLB. The clock
enable is synchronous to the clock and must satisfy the
setup and hold timing specified for the device.
CK
EC
SR
D
Q
X
X
X
X
SR
Set/Reset
X
__/
0
1
0
X
X
1*
X
1*
1*
0
1
0*
0*
0*
0*
0*
X
D
X
X
D
X
SR
D
Q
Q
D
Q
The set/reset line (SR) is an asynchronous active High control of the flip-flop. SR can be configured as either set or
reset at each flip-flop. This configuration option determines
the state in which each flip-flop becomes operational after
configuration. It also determines the effect of a GSR pulse
during normal operation, and the effect of a pulse on the
SR line of the CLB. The SR line is shared by both flip-flops.
If SR is not specified for a flip-flop the set/reset for that
flip-flop defaults to the inactive state. SR is not invertible
within the CLB.
Don’t care
Rising edge (clock not inverted)
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
CLB Signal Flow Control
Input/Output Blocks (IOBs)
In addition to the H-LUT input control multiplexers (shown
in box "A" of Figure 2 on page 3) there are signal flow control multiplexers (shown in box "B" of Figure 2) which select
the signals which drive the flip-flop inputs and the combinatorial CLB outputs (X and Y).
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be configured for input, output, or bidirectional signals. Figure 5 on
page 6 shows a simplified functional block diagram of the
Spartan/XL IOB.
Each flip-flop input is driven from a 4:1 multiplexer which
selects among the three LUT outputs and DIN as the data
source.
Each combinatorial output is driven from a 2:1 multiplexer
which selects between two of the LUT outputs. The X output can be driven from the F-LUT or H-LUT, the Y output
from G-LUT or H-LUT.
Control Signals
There are four signal control multiplexers on the input of the
CLB. These multiplexers allow the internal CLB control signals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be
driven from any of the four general control inputs (C1 - C4
in Figure 4) into the CLB. Any of these inputs can drive any
of the four internal control signals.
IOB Input Signal Path
The input signal to the IOB can be configured to either go
directly to the routing channels (via I1 and I2 in Figure 5) or
to the input register. The input register can be programmed
as either an edge-triggered flip-flop or a level-sensitive
latch. The functionality of this register is shown in Table 3,
and a simplified block diagram of the register can be seen
in Figure 6.
Table 3: Input Register Functionality
Mode
Power-Up or
GSR
Flip-Flop
CK
X
EC
X
D
X
Q
SR
__/
0
1
0
X
1*
X
1*
1*
0
D
X
X
D
X
D
Q
Q
D
Q
The four internal control signals are:
•
•
•
•
EC - Enable Clock
SR - Asynchronous Set/Reset or H function generator
Input 0
DIN - Direct In or H function generator Input 2
H1 - H function generator Input 1.
Latch
Both
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge (clock not inverted)
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
DIN
GSR
H1
SD
C1
D
D
Q
Q
C2
SR
C3
CK
RD
C4
EC
Vcc
EC
Rev 1.1
Multiplexer Controlled
by Configuration Program
Rev 1.1
Figure 4: CLB Control Signal Interface
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Multiplexer Controlled
by Configuration Program
Figure 6: IOB Flip-Flop/Latch Functional Block
Diagram
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
The register choice is made by placing the appropriate
library symbol. For example, IFD is the basic input flip-flop
(rising edge triggered), and ILD is the basic input latch
(transparent-High). Variations with inverted clocks are also
available. The clock signal inverter is also shown in
Figure 6 on the CK line.
The Spartan IOB data input path has a one-tap delay element: either the delay is inserted (default), or it is not. The
Spartan-XL IOB data input path has a two-tap delay element, with choices of a full delay, a partial delay, or no
delay. The added delay guarantees a zero hold time with
respect to clocks routed through the global clock buffers.
(See “Global Nets and Buffers” on page 11 for a description
of the global clock buffers in the Spartan/XL families.) For a
shorter input register setup time, with positive hold-time,
attach a NODELAY attribute or property to the flip-flop.
The output of the input register goes to the routing channels (via I1 and I2 in Figure 5). The I1 and I2 signals that
exit the IOB can each carry either the direct or registered
input signal.
The 5V Spartan input buffers can be globally configured for
either TTL (1.2V) or CMOS (VCC/2) thresholds, using an
option in the bitstream generation software. The Spartan
output levels are also configurable; the two global adjustments of input threshold and output level are independent.
The inputs of Spartan devices can be driven by the outputs
of any 3.3V device, if the Spartan inputs are in TTL mode.
Spartan-XL inputs are TTL compatible and 3.3V CMOS
compatible.
Supported sources for Spartan/XL device inputs are shown
in Table 4.
Spartan-XL I/Os are fully 5V tolerant even though the V CC
is 3.3V. This allows 5V signals to directly connect to the
Spartan-XL inputs without damage, as shown in Table 4. In
addition, the 3.3V VCC can be applied before or after 5V
signals are applied to the I/Os. This makes the Spartan-XL
devices immune to power supply sequencing problems.
GTS
T
O
D
Q
OUTPUT DRIVER
Programmable Slew Rate
Programmable TTL/CMOS Drive
CK
OK
EC
Package
Pad
I1
INPUT BUFFER
Delay
I2
D
IK
CK
EC
EC
Q
Programmable
Pull-Up/
Pull-Down
Network
Multiplexer Controlled
by Configuration Program
Rev 1.1
Figure 5: Simplified Spartan/XL IOB Block Diagram
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 4: Supported Sources for Spartan/XL Inputs
Spartan
Spartan-XL
Inputs
Inputs
5V,
5V,
3.3V
TTL CMOS
CMOS
Source
Any device, V CC = 3.3V,
CMOS outputs
Spartan family, V CC = 5V,
TTL outputs
Any device, V CC = 5V,
TTL outputs (V OH ≤ 3.7V)
Any device, V CC = 5V,
CMOS outputs
√
√
√
Unreliable
Data
√
√
√
√
√
√ (default
mode)
Spartan-XL VCC Clamping
Spartan-XL FPGAs have an optional clamping diode connected from each I/O to VCC. When enabled they clamp
ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. VCC clamping is a global option affecting all I/O pins.
Spartan-XL devices are fully 5V TTL I/O compatible if VCC
clamping is not enabled. With VCC clamping enabled, the
Spartan-XL devices will begin to clamp input voltages to
one diode voltage drop above VCC. If enabled, TTL I/O
compatibility is maintained but full 5V I/O tolerance is sacrificed. The user may select either 5V tolerance (default) or
3.3V PCI compatibility. In both cases negative voltage is
clamped to one diode voltage drop below ground.
Spartan-XL devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in Table 5.
Table 5: I/O Standards Supported by Spartan-XL FPGAs
Signaling
Standard
TTL
LVTTL
PCI5V
PCI3V
VCC
Clamping
Not allowed
OK
Not allowed
Required
Output Drive
12/24 mA
12/24 mA
24 mA
12 mA
VIH MAX
VIH MIN
VIL MAX
VOH MIN
VOL MAX
5.5
3.6
5.5
3.6
2.0
2.0
2.0
50% of VCC
0.8
0.8
0.8
30% of VCC
2.4
2.4
2.4
90% of VCC
0.4
0.4
0.4
10% of VCC
LVCMOS 3V
OK
12/24 mA
3.6
50% of VCC
30% of VCC
90% of VCC
10% of VCC
Additional Fast Capture Input Latch (Spartan-XL only)
The Spartan-XL IOB has an additional optional latch on the
input. This latch is clocked by the clock used for the output
flip-flop rather than the input clock. Therefore, two different
clocks can be used to clock the two input storage elements.
This additional latch allows the fast capture of input data,
which is then synchronized to the internal clock by the IOB
flip-flop or latch.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a transparent-Low Fast Capture latch followed by an active High
input flip-flop. ILFLX is a transparent-Low Fast Capture
latch followed by a transparent-High input latch. Any of the
clock inputs can be inverted before driving the library element, and the inverter is absorbed into the IOB.
IOB Output Signal Path
Output signals can be optionally inverted within the IOB,
and can pass directly to the output buffer or be stored in an
edge-triggered flip-flop and then to the output buffer. The
functionality of this flip-flop is shown in Table 6.
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Table 6: Output Flip-Flop Functionality
Mode
Power-Up
or GSR
Flip-Flop
Legend:
X
__/
SR
0*
1*
Z
Clock
X
Clock
Enable
X
T
0*
D
X
Q
SR
X
__/
X
0
0
1*
X
X
0*
0*
1
0*
X
D
X
X
Q
D
Z
Q
Don’t care
Rising edge (clock not inverted)
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
Output Multiplexer/2-Input Function Generator
(Spartan-XL only)
The output path in the Spartan-XL IOB contains an additional multiplexer not available in the Spartan IOB. The multiplexer can also be configured as a 2-input function
generator, implementing a pass gate, AND gate, OR gate,
or XOR gate, with 0, 1, or 2 inverted inputs.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
When configured as a multiplexer, this feature allows two
output signals to time-share the same output pad, effectively doubling the number of device outputs without requiring a larger, more expensive package. The select input is
the pin used for the output flip-flop clock, OK.
When the multiplexer is configured as a 2-input function
generator, logic can be implemented within the IOB itself.
Combined with a Global buffer, this arrangement allows
very high-speed gating of a single signal. For example, a
wide decoder can be implemented in CLBs, and its output
gated with a Read or Write Strobe driven by a global buffer.
The user can specify that the IOB function generator be
used by placing special library symbols beginning with the
letter "O." For example, a 2-input AND gate in the IOB function generator is called OAND2. Use the symbol input pin
labeled "F" for the signal on the critical path. This signal is
placed on the OK pin — the IOB input with the shortest
delay to the function generator. Two examples are shown in
Figure 7.
D0
F
OMUX2
O
D1
OAND2
X6598
S0
X6599
Figure 7: AND & MUX Symbols in Spartan-XL IOB
Output Buffer
An active High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control, the
output (O) and output 3-state (T) signals can be inverted.
The polarity of these signals is independently configured for
each IOB (see Figure 5 on page 6). An output can be configured as open-drain (open-collector) by tying the 3-state
pin (T) to the output signal, and the input pin (I) to Ground.
By default, a 5V Spartan device output buffer pull-up structure is configured as a TTL-like totem-pole. The High driver
is an n-channel pull-up transistor, pulling to a voltage one
transistor threshold below V CC. Alternatively, the outputs
can be globally configured as CMOS drivers, with additional p-channel pull-up transistors pulling to V CC. This
option, applied using the bitstream generation software,
applies to all outputs on the device. It is not individually programmable.
All Spartan-XL device outputs are configured as CMOS
drivers, therefore driving rail-to-rail. The Spartan-XL outputs are individually programmable for 12 mA or 24 mA output drive.
Any 5V Spartan device with its outputs configured in TTL
mode can drive the inputs of any typical 3.3V device. Supported destinations for Spartan/XL device outputs are
shown in Table 7.
Three-State Register (Spartan-XL Only)
Spartan-XL devices incorporate an optional register controlling the three-state enable in the IOBs. The use of the
three-state control register can significantly improve output
enable and disable time.
Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or
property to the output buffer or flip-flop.
Spartan/XL devices have a feature called "Soft Start-up,"
designed to reduce ground bounce when all outputs are
turned on simultaneously at the end of configuration.
When the configuration process is finished and the device
starts up, the first activation of the outputs is automatically
slew-rate limited. Immediately following the initial activation
of the I/O, the slew rate of the individual outputs is determined by the individual configuration option for each IOB.
Pull-up and Pull-down Network
Programmable pull-up and pull-down resistors are used for
tying unused pins to VCC or Ground to minimize power consumption and reduce noise sensitivity. The configurable
pull-up resistor is a p-channel transistor that pulls to VCC.
The configurable pull-down resistor is an n-channel transistor that pulls to Ground. The value of these resistors is typically 20 kΩ − 100 kΩ (See “Spartan DC Characteristics
Over Operating Conditions” on page 36.). This high value
makes them unsuitable as wired-AND pull-up resistors.
Table 7: Supported Destinations for Spartan/XL
Outputs
Destination
Any device, V CC = 3.3V,
CMOS-threshold inputs
Any device, VCC = 5V,
TTL-threshold inputs
Any device, VCC = 5V,
CMOS-threshold inputs
1.
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Spartan-XL
Outputs
3.3V,
CMOS
√
√
Spartan
Outputs
5V,
5V,
TTL
CMOS
√
Some1
√
Unreliable
Data
√
√
Only if destination device has 5V tolerant inputs
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal
pull-up, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
Set/Reset
As with the CLB registers, the GSR signal can be used to
set or clear the input and output registers, depending on the
value of the INIT attribute or property. The two flip-flops can
be individually configured to set or clear on reset and after
configuration. Other than the global GSR net, no user-controlled set/reset signal is available to the I/O flip-flops
(Figure 6). The choice of set or reset applies to both the initial state of the flip-flop and the response to the GSR pulse.
input or output flip-flop, or both. This clock enable operates
exactly like the EC signal on the Spartan/XL CLB. It cannot
be inverted within the IOB.
Routing Channel Description
All internal routing channels are composed of metal segments with programmable switching points and switching
matrices to implement the desired routing. A structured,
hierarchical matrix of routing channels is provided to
achieve efficient automated routing.
This section describes the routing channels available in
Spartan/XL devices. Figure 8 shows a general block diagram of the CLB routing channels. The implementation
software automatically assigns the appropriate resources
based on the density and timing requirements of the
design. The following description of the routing channels is
for information only and is simplified with some minor
details omitted. For an exact interconnect description the
designer should open a design in the FPGA Editor and
review the actual connections in this tool.
The routing channels will be discussed as follows;
Independent Clocks
Separate clock signals are provided for the input (IK) and
output (OK) flip-flops. The clock can be independently
inverted for each flip-flop within the IOB, generating either
falling-edge or rising-edge triggered flip-flops. The clock
inputs for each IOB are independent.
Common Clock Enables
The input and output flip-flops in each IOB have a common
clock enable input (see EC signal in Figure 6), which
through configuration, can be activated individually for the
PSM
•
•
•
CLB routing channels which run along each row and
column of the CLB array.
IOB routing channels which form a ring (called a
VersaRing) around the outside of the CLB array. It
connects the I/O with the CLB routing channels.
Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
PSM
PSM
8 Singles
2 Doubles
3 Longs
CLB
CLB
3 Longs
2 Doubles
PSM
2 Doubles
PSM
3 Longs
8 Singles
PSM
Rev 1.2
3 Longs
2 Doubles
Figure 8: Spartan/XL CLB Routing Channels and Interface Block Diagram
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
G4
C4
F4
The routing channels around the CLB are derived from
three types of interconnects; single-length, double-length,
and longlines. At the intersection of each vertical and horizontal routing channel is a signal steering matrix called a
Programmable Switch Matrix (PSM). Figure 8 shows the
basic routing channel configuration showing single-length
lines, double-length lines and longlines as well as the CLBs
and PSMs. The CLB to routing channel interface is shown
as well as how the PSMs interface at the channel intersections.
YQ
CLB Routing Channels
CIN
Y
COUT
G3
G1
C3
CLB
C1
K
CLB Interface
Programmable Switch Matrices
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each PSM consists of programmable pass transistors used to establish connections between the lines (see
Figure 10).
F3
F1
X
G2
C2
F2
Rev 1.1
XQ
A block diagram of the CLB interface signals is shown in
Figure 9. The input signals to the CLB are distributed
evenly on all four sides providing maximum routing flexibility. In general, the entire architecture is symmetrical and
regular. It is well suited to established placement and routing algorithms. Inputs, outputs, and function generators can
freely swap positions within a CLB to avoid routing congestion during the placement and routing operation. The
exceptions are the clock (K) input and CIN/COUT signals.
The K input is routed to dedicated global vertical lines as
well as four single-length lines and is on the left side of the
CLB. The CIN/COUT signals are routed through dedicated
interconnects which do not interfere with the general routing structure. The output signals from the CLB are available
to drive both vertical and horizontal channels.
Figure 9: CLB Interconnect Signals
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
Single-Length Lines
Single-length lines provide the greatest interconnect flexibility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switching matrices that are located in every row and column of
CLBs.
Six Pass Transistors Per
Switch Matrix Interconnect Point
Figure 10: Programmable Switch Matrix
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DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Single-length lines incur a delay whenever they go through
a PSM. Therefore, they are not suitable for routing signals
for long distances. They are normally used to conduct signals within a localized area and to provide the branching for
nets with fanout greater than one.
Double-Length Lines
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a PSM. Double-length lines are
grouped in pairs with the PSMs staggered, so that each line
goes through a PSM at every other row or column of CLBs
(see Figure 8).
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility.
Longlines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances.
Each Spartan/XL device longline has a programmable splitter switch at its center. This switch can separate the line
into two independent routing channels, each running half
the width or height of the array.
I/O Routing
Spartan/XL devices have additional routing around the IOB
ring. This routing is called a VersaRing. The VersaRing
facilitates pin-swapping and redesign without affecting
board layout. Included are eight double-length lines, and
four longlines.
Global Nets and Buffers
The Spartan/XL devices have dedicated global networks.
These networks are designed to distribute clocks and other
high fanout control signals throughout the devices with minimal skew.
Four vertical longlines in each CLB column are driven
exclusively by special global buffers. These longlines are in
addition to the vertical longlines used for standard interconnect. In the 5V Spartan devices, the four global lines can be
driven by either of two types of global buffers; Primary Global buffers (BUFGP) or Secondary Global buffers
(BUFGS). Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary
Global buffers, as shown in Figure 11. In the 3V
Spartan-XL devices, the four global lines can be driven by
any of the eight Global Low-Skew Buffers (BUFGLS). The
clock pins of every CLB and IOB can also be sourced from
local interconnect.
IOB
IOB
locals
IOB
locals
BUFGS
locals
IOB
Routing connectivity of the longlines is shown in Figure 8.
The longlines also interface to some 3-state buffers which
is described later in “3-State Long Line Drivers” on
page 17.
locals
Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 10. Routing connectivity is shown in Figure 8.
BUFGP
SGCK4
PGCK1
PGCK4
SGCK1
4
4
BUFGS
BUFGP
4
locals
4
locals
CLB
CLB
IOB
IOB
locals
X4
locals
Any BUFGS
X4
Any BUFGS
X4
One BUFGP
per Global Line
IOB
locals
X4
locals
One BUFGP
per Global Line
CLB
locals
CLB
IOB
locals
BUFGP
BUFGS
SGCK3
IOB
IOB
IOB
locals
locals
locals
BUFGP
locals
PGCK2
SGCK2
IOB
PGCK3
BUFGS
X6604
Figure 11: 5V Spartan Family Global Net Distribution
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
The four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to potentially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs. The eight Global Low-Skew
buffers in the Spartan-XL devices combine short delay,
negligible skew, and flexibility.
The Primary Global buffers must be driven by the
semi-dedicated pads (PGCK1-4). The Secondary Global
buffers can be sourced by either semi-dedicated pads
(SGCK1-4) or internal nets. Each corner of the device has
one Primary buffer and one Secondary buffer. The Spartan-XL family has eight global low-skew buffers, two in each
corner. All can be sourced by either semi-dedicated pads
(GCK1-8) or internal nets.
Using the library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the
timing requirements of the design. A global buffer should be
specified for all timing-sensitive global signal distribution.
To use a global buffer, place a BUFGP (primary buffer),
BUFGS (secondary buffer), BUFGLS (Spartan-XL global
low-skew buffer), or BUFG (any buffer type) element in a
schematic or in HDL code.
Advanced Features Description
Distributed RAM
Optional modes for each CLB allow the function generators
(F-LUT and G-LUT) to be used as Random Access Memory (RAM).
Read and write operations are significantly faster for this
on-chip RAM than for off-chip implementations. This speed
advantage is due to the relatively short signal propagation
delays within the FPGA.
Memory Configuration Overview
There are two available memory configuration modes: single-port RAM and dual-port RAM. For both these modes,
write operations are synchronous (edge-triggered), while
read operations are asynchronous. In the single-port mode,
a single CLB can be configured as either a 16 x 1, (16 x 1)
x 2, or 32 x 1 RAM array. In the dual-port mode, a single
CLB can be configured only as one 16 x 1 RAM array. The
different CLB memory configurations are summarized in
Table 8. Any of these possibilities can be individually programmed into a Spartan/XL CLB.
•
•
The 16 x 1 single-port configuration contains a RAM
array with 16 locations, each one-bit wide. One 4-bit
address decoder determines the RAM location for write
and read operations. There is one input for writing data
and one output for reading data, all at the selected
address.
The (16 x 1) x 2 single-port configuration combines two
16 x 1 single-port configurations (each according to the
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•
•
preceding description). There is one data input, one
data output and one address decoder for each array.
These arrays can be addressed independently.
The 32 x 1 single-port configuration contains a RAM
array with 32 locations, each one-bit wide. There is one
data input, one data output, and one 5-bit address
decoder.
The dual-port mode 16 x 1 configuration contains a
RAM array with 16 locations, each one-bit wide. There
are two 4-bit address decoders, one for each port. One
port consists of an input for writing and an output for
reading, all at a selected address. The other port
consists of one output for reading from an
independently selected address.
Table 8: CLB Memory Configurations
Mode
Single-Port
Dual-Port
16 x 1
√
√
(16 x 1) x 2
√
32 x 1
√
The appropriate choice of RAM configuration mode for a
given design should be based on timing and resource
requirements, desired functionality, and the simplicity of the
design process. Selection criteria include the following:
Whereas the 32 x 1 single-port, the (16 x 1) x 2 single-port,
and the 16 x 1 dual-port configurations each use one entire
CLB, the 16 x 1 single-port configuration uses only one half
of a CLB. Due to its simultaneous read/write capability, the
dual-port RAM can transfer twice as much data as the single-port RAM, which permits only one data operation at any
given time.
CLB memory configuration options are selected by using
the appropriate library symbol in the design entry.
Single-Port Mode
There are three CLB memory configurations for the single-port RAM: 16 x 1, (16 x 1) x 2, and 32 x 1, the functional
organization of which is shown in Figure 12.
The single-port RAM signals and the CLB signals (Figure 2
on page 3) from which they are originally derived are shown
in Table 9.
Table 9: Single-Port RAM Signals
RAM Signal
D
A[3:0]
A4 (32 x 1 only)
WE
WCLK
SPO
Function
Data In
Address
Address
Write Enable
Clock
Single Port Out
(Data Out)
CLB Signal
DIN or H1
F1-F4 or G1-G4
H1
SR
K
FOUT or GOUT
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
INPUT REGISTER
A[n-1:0]
n
WE
D0 or D1
●
●
16 x 1
32 x 1
RAM ARRAY
●
●
WRITE
CONTROL
READ
OUT
READ ROW
SELECT
WRITE ROW
SELECT
n
SPO
●
WCLK
Figure 12: Logic Diagram for the Single-Port RAM
NOTE: 1. The (16 x 1) x 2 configuration combines two 16 x 1 single-port RAMs, each with its own independent address bus and
data input. The same WE and WCLK signals are connected to both RAMs.
2. n = 4 for the 16 x 1 and (16 x 1) x 2 configurations. n = 5 for the 32 x 1 configuration.
Writing data to the single-port RAM is essentially the same
as writing to a data register. It is an edge-triggered (synchronous) operation performed by applying an address to
the A inputs and data to the D input during the active edge
of WCLK while WE is High.
The timing relationships are shown in Figure 13. The High
logic level on WE enables the input data register for writing.
The active edge of WCLK latches the address, input data,
and WE signals. Then, an internal write pulse is generated
that loads the data into the memory cell.
WCLK (K)
TWHS
WE
TDHS
TDSS
The WE input is active High and cannot be inverted within
the CLB.
Allowing for settling time, the data on the SPO output
reflects the contents of the RAM location currently
addressed. When the address changes, following the asynchronous delay TILO, the data stored at the new address
location will appear on SPO. If the data at a particular RAM
address is overwritten, after the delay TWOS, the new data
will appear on SPO.
TWPS
TWSS
WCLK can be configured as active on either the rising edge
(default) or the falling edge. While the WCLK input to the
RAM accepts the same signal as the clock input to the
associated CLB’s flip-flops, the sense of this WCLK input
can be inverted with respect to the sense of the flip-flop
clock inputs. Consequently, within the same CLB, data at
the RAM’s SPO line can be stored in a flip-flop with either
the same or the inverse clock polarity used to write data to
the RAM.
Dual-Port Mode
DATA IN
TASS
In dual-port mode, the function generators (F-LUT and
G-LUT) are used to create a 16 x 1 dual-port memory. Of
the two data ports available, one permits read and write
operations at the address specified by A[3:0] while the second provides only for read operations at the address specified independently by DPRA[3:0]. As a result,
simultaneous read/write operations at different addresses
(or even at the same address) are supported.
TAHS
ADDRESS
TILO
DATA OUT
TWOS
OLD
TILO
NEW
X6461
The functional organization of the 16 x 1 dual-port RAM is
shown in Figure 14.
Figure 13: Data Write and Access Timing for RAM
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
4
WE
D
4
●
16 x 1
RAM
●
●
WRITE
CONTROL
●
READ
OUT
SPO
●
●
●
READ ROW
SELECT
●
WRITE ROW
SELECT
WCLK
INPUT REGISTER
A[3:0]
●
●
READ ROW
SELECT
WRITE ROW
SELECT
4
16 x 1
RAM
●
●
WRITE
CONTROL
READ
OUT
DPRA[3:0]
4
DPO
Figure 14: Logic Diagram for the Dual-Port RAM
The dual-port RAM signals and the CLB signals from which
they are originally derived are shown in Table 10.
Table 10: Dual-Port RAM Signals
RAM Signal
D
A[3:0]
DPRA[3:0]
WE
WCLK
SPO
DPO
Function
Data In
Read Address for Single-Port.
Write Address for Single-Port
and Dual-Port.
Read Address for Dual-Port
Write Enable
Clock
Single Port Out
(addressed by A[3:0])
Dual Port Out
(addressed by DPRA[3:0])
CLB
Signal
DIN
F1-F4
G1-G4
SR
K
FOUT
GOUT
The RAM16X1D primitive used to instantiate the dual-port
RAM consists of an upper and a lower 16 x 1 memory array.
The address port labeled A[3:0] supplies both the read and
write addresses for the lower memory array, which behaves
the same as the 16 x 1 single-port RAM array described
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previously. Single Port Out (SPO) serves as the data output
for the lower memory. Therefore, SPO reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the upper
memory. The write address for this memory, however,
comes from the address A[3:0]. Dual Port Out (DPO)
serves as the data output for the upper memory. Therefore,
DPO reflects the data at address DPRA[3:0].
By using A[3:0] for the write address and DPRA[3:0] for the
read address, and reading only the DPO output, a FIFO
that can read and write simultaneously is easily generated.
The simultaneous read/write capability possible with the
dual-port RAM can provide twice the effective data throughput of a single-port RAM alternating read and write operations.
The timing relationships for the dual-port RAM mode are
shown in Figure 13.
Note that write operations to RAM are synchronous
(edge-triggered); however, data access is asynchronous.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Initializing RAM at FPGA Configuration
Both RAM and ROM implementations in the Spartan/XL
families are initialized during device configuration. The initial contents are defined via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents
are initialized to zeros, by default.
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
RAM initialization occurs only during device configuration.
The RAM content is not affected by GSR.
More Information on using RAM inside CLBs
Three application notes are available from Xilinx that discuss synchronous (edge-triggered) RAM: "Xilinx Edge-Triggered and Dual-Port RAM Capability," "Implementing
FIFOs in Xilinx RAM," and "Synchronous and Asynchronous FIFO Designs." All three application notes apply to
both the Spartan and the Spartan-XL families.
Fast Carry Logic
Each CLB F-LUT and G-LUT contains dedicated arithmetic
logic for the fast generation of carry and borrow signals.
This extra output is passed on to the function generator in
the adjacent CLB. The carry chain is independent of normal
routing resources. (See Figure 15.)
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level. This fast
carry logic is one of the more significant features of the
Spartan and Spartan-XL families, speeding up arithmetic
and counting functions.
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X6610
Figure 15: Available Spartan/XL Carry Propagation
Paths
The carry chain in 5V Spartan devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above and below, the carry is propagated to
the right. The default is always to propagate up the column,
as shown in the figures. The carry chain in Spartan-XL
devices can only run up the column, providing even higher
speed.
Figure 16 on page 16 shows a Spartan/XL CLB with dedicated fast carry logic. The carry logic shares operand and
control inputs with the function generators. The carry outputs connect to the function generators, where they are
combined with the operands to form the sums.
Figure 17 on page 17 shows the details of the Spartan/XL
carry logic. This diagram shows the contents of the box
labeled "CARRY LOGIC" in Figure 16.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
CARRY
LOGIC
D IN
C OUT
G
Y
H
G
CARRY
G4
G3
G
DIN
G2
S/R
H
D
G
F
Q
YQ
Q
XQ
G1
EC
COUT0
H
H1
DIN
S/R
H
F
CARRY
D
G
F
EC
F4
F3
F
F2
H
F1
X
F
CIN
K
S/R
EC
S6699_01
Figure 16: Fast Carry Logic in Spartan/XL CLB
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
C OUT
M
G1
M
1
0
I
1
G2
0
G4
G3
C OUT0
TO
FUNCTION
GENERATORS
M
F2
M
1
0
F1
M
M
0
1
0
F4
1
3
M
1
F3
M
0
M
C IN
M
S2000_01
Figure 17: Detail of Spartan/XL Dedicated Carry Logic
3-State Long Line Drivers
Three-State Buffer Example
A pair of 3-state buffers is associated with each CLB in the
array. These 3-state buffers (BUFT) can be used to drive
signals onto the nearest horizontal longlines above and
below the CLB. They can therefore be used to implement
multiplexed or bidirectional buses on the horizontal longlines, saving logic resources.
Figure 18 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active High 3-state (T) is
identical to an active Low output enable, as shown in
Table 11.
There is a weak keeper at each end of these two horizontal
longlines. This circuit prevents undefined floating levels.
However, it is overridden by any driver.
Table 11: Three-State Buffer Functionality
IN
X
IN
The buffer enable is an active High 3-state (i.e., an active
Low enable), as shown in Table 11.
T
1
0
OUT
Z
IN
Z = DA • A + D B • B + D C • C + D N • N
~100 kΩ
DA
DB
BUFT
A
DC
BUFT
B
DN
BUFT
C
BUFT
N
X6466
"Weak Keeper"
Figure 18: 3-state Buffers Implement a Multiplexer
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
On-Chip Oscillator
Global 3-State
Spartan/XL devices include an internal oscillator. This
oscillator is used to clock the power-on time-out, for configuration memory clearing, and as the source of CCLK in
Master configuration mode. The oscillator runs at a nominal
8 MHz frequency that varies with process, VCC, and temperature. The output frequency falls between 4 MHz and
10 MHz.
A separate Global 3-state line (GTS) as shown in Figure 5
on page 6 forces all FPGA outputs to the high-impedance
state, unless boundary scan is enabled and is executing an
EXTEST instruction. GTS does not compete with other
routing resources; it uses a dedicated distribution network.
The oscillator output is optionally available after configuration. Any two of four resynchronized taps of a built-in divider
are also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. Therefore, if the
primary oscillator output is running at the nominal 8 MHz,
the user has access to an 8-MHz clock, plus any two of
500 kHz, 16 kHz, 490 Hz and 15 Hz. These frequencies
can vary by as much as -50% or +25%.
These signals can be accessed by placing the OSC4
library element in a schematic or in HDL code. The oscillator is automatically disabled after configuration if the OSC4
symbol is not used in the design.
Global Signals: GSR and GTS
Global Set/Reset
A separate Global Set/Reset line, as shown in Figure 3 on
page 4 for the CLB and Figure 6 on page 5 for the IOB, sets
or clears each flip-flop during power-up, reconfiguration, or
when a dedicated Reset net is driven active. This global net
(GSR) does not compete with other routing resources; it
uses a dedicated distribution network.
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, if in reset mode, it is reset by both SR and GSR.
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GSR pin of the STARTUP symbol. (See Figure 19.) A specific pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the GSR signal. Alternatively, GSR can be driven from any internal node.
STARTUP
PAD
IBUF
GSR
GTS
Q2
Q3
Q1Q4
CLK DONEIN
X5260
Figure 19: Schematic Symbols for Global Set/Reset
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GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. This is similar to what
is shown in Figure 19 for GSR except the IBUF would be
connected to GTS. A specific pin location can be assigned
to this input using a LOC attribute or property, just as with
any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of
the Global 3-state signal. Alternatively, GTS can be driven
from any internal node.
Boundary Scan
The "bed of nails" has been the traditional method of testing
electronic assemblies. This approach has become less
appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology
and multi-layer boards. The IEEE Boundary Scan Standard
1149.1 was developed to facilitate board-level testing of
electronic assemblies. Design and test engineers can
embed a standard test logic structure in their device to
achieve high fault coverage for I/O and internal logic. This
structure is easily implemented with a four-pin interface on
any boundary scan compatible device. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two.
The Spartan and Spartan-XL families implement IEEE
1149.1-compatible BYPASS, PRELOAD/SAMPLE and
EXTEST boundary scan instructions. When the boundary
scan configuration option is selected, three normal user I/O
pins become dedicated inputs for these functions. Another
user output pin becomes the dedicated boundary scan output. The details of how to enable this circuitry are covered
later in this section.
By exercising these input signals, the user can serially load
commands and data into these devices to control the driving of their outputs and to examine their inputs. This
method is an improvement over bed-of-nails testing. It
avoids the need to over-drive device outputs, and it reduces
the user interface to four pins. An optional fifth pin, a reset
for the control logic, is described in the standard but is not
implemented in the Spartan/XL devices.
The dedicated on-chip logic implementing the IEEE 1149.1
functions includes a 16-state machine, an instruction register and a number of data registers. The functional details
can be found in the IEEE 1149.1 specification and are also
discussed in the Xilinx application note: "Boundary Scan in
FPGA Devices."
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Figure 20 is a diagram of the Spartan/XL boundary scan
logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
Spartan/XL devices can also be configured through the
boundary scan logic. See “Configuration Through the
Boundary Scan Pins” on page 31.
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
two
corresponding
pins
(BSCAN.TDO1
and
BSCAN.TDO2) allow user scan data to be shifted out on
TDO. The data register clock (BSCAN.DRCK) is available
for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE
is also provided (BSCAN.IDLE).
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-state Control. Non-IOB pins have
appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
Instruction Set
The Spartan/XL boundary scan instruction set also
includes instructions to configure the device and read back
the configuration data. The instruction set is coded as
shown in Table 12.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals.
DATA IN
IOB.T
0
1
0
IOB
IOB
IOB
IOB
sd
D
Q
D
Q
1
LE
IOB
IOB
IOB
IOB
IOB
1
sd
D
Q
D
Q
0
LE
IOB
IOB
IOB
IOB
1
IOB.I
0
1
IOB
IOB
IOB
IOB
IOB
IOB
BYPASS
REGISTER
0
sd
D
Q
D
Q
LE
1
0
IOB.Q
IOB.T
TDI
INSTRUCTION REGISTER
M TDO
U
X
0
1
0
sd
D
Q
D
Q
1
LE
1
0
sd
D
Q
D
Q
LE
1
IOB.I
0
DATAOUT
SHIFT/
CLOCK DATA
CAPTURE
REGISTER
UPDATE
EXTEST
X9016
Figure 20: Spartan/XL Boundary Scan Logic
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4-19
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 12: Boundary Scan Instructions
Instruction
I2 I1 I0
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
0
0
1
0
1
0
1
1
1
Test
Selected
TDO Source
I/O Data
Source
DR
DR
DR
Pin/Logic
EXTEST
SAMPLE/
PRELOAD
USER 1
BSCAN.
User Logic
TDO1
USER 2
BSCAN.
User Logic
TDO2
READBACK Readback Data Pin/Logic
CONFIGURE
DOUT
Disabled
IDCODE
IDCODE
—
(Spartan-XL
Register
only)
BYPASS Bypass Register
—
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-state. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes all three bits.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal signals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 21.
The device-specific pinout tables for the Spartan/XL
devices include the boundary scan locations for each IOB
pin.
Bit 0 ( TDO end)
Bit 1
Bit 2
BSDL (Boundary Scan Description Language) files for
Spartan/XL devices are available on the Xilinx website in
the File Download area. Note that the 5V Spartan devices
and 3V Spartan-XL devices have different BSDL files.
Including Boundary Scan in a Design
If boundary scan is only to be used during configuration, no
special schematic elements need be included in the schematic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user functions after configuration.
To indicate that boundary scan remain enabled after configuration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 22.
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep TMS
High, and then apply whatever signal is desired to TDI and
TCK.
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant during configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configuration, do either of the following:
•
•
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
TMS: Tie High to put the Test Access Port controller
in a benign RESET state
TCK: Tie High or Low—do not toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note, "Boundary Scan in FPGA Devices."
Optional
To User
Logic
Left-edge IOBs (Top to Bottom)
IBUF
BSCAN
MODE.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
(TDI end)
TDI
TDI
TMS
TMS
TCK
TCK
IDLE
TDO1
SEL1
TDO2
SEL2
From
User Logic
TDO
TDO
DRCK
To User
Logic
X2675
BSCANT.UPD
Figure 22: Boundary Scan Schematic Example
S6075_02
Figure 21:
Boundary Scan Bit Sequence
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Boundary Scan Enhancements (Spartan-XL
only)
Spartan-XL devices have improved boundary scan functionality and performance in the following areas:
IDCODE: The IDCODE register is supported. By using the
IDCODE, the device connected to the JTAG port can be
determined. The use of the IDCODE enables selective configuration dependent on the FPGA found.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
c = the company code (49h for Xilinx)
a = the array dimension in CLBs (ranges from 0Ah for
XCS05XL to 1Ch for XCS40XL)
f = the family code (02h for Spartan-XL family)
v = the die version number (currently 0h)
Table 13: IDCODEs Assigned to Spartan-XL FPGAs
FPGA
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
IDCODE
0040A093h
0040E093h
00414093h
00418093h
0041C093h
Configuration State: The configuration state is available to
JTAG controllers.
Configuration Disable: The JTAG port can be prevented
from configuring the FPGA.
TCK Startup: TCK can now be used to clock the start-up
block in addition to other user clocks.
CCLK Holdoff: Changed the requirement for Boundary
Scan Configure or EXTEST to be issued prior to the
release of INIT pin and CCLK cycling.
Reissue Configure: The Boundary Scan Configure can be
reissued to recover from an unfinished attempt to configure
the device.
Bypass FF: Bypass FF and IOB is modified to provide
DRCLOCK only during BYPASS for the bypass flip-flop,
and during EXTEST or SAMPLE/PRELOAD for the IOB
register.
Power Down (Spartan-XL Only)
All Spartan/XL devices use a combination of efficient segmented routing and advanced process technology to provide low power consumption under all conditions. The 3.3V
Spartan-XL family adds a dedicated active Low Power
Down pin (PWRDWN) to reduce supply current to 100 µA
typical. The PWRDWN pin takes advantage of one of the
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unused No Connect locations on the 5V Spartan device.
The user must de-select the "5V Tolerant I/Os" option in the
Configuration Options to achieve the specified Power Down
current. The PWRDWN pin has a default internal pull-up
resistor, allowing it to be left unconnected if unused.
V CC must continue to be supplied during Power-down, and
configuration data is maintained. When the PWRDWN pin
is pulled Low, the input and output buffers are disabled. The
inputs are internally forced to a logic Low level, including
the MODE pins, DONE, CCLK, and TDO, and all internal
pull-up resistors are turned off. The PROGRAM pin is not
affected by Power Down. The GSR net is asserted during
Power Down, initializing all the flip-flops to their start-up
state.
PWRDWN has a minimum pulse width of 50 ns (Figure 23).
On entering the Power-down state, the inputs will be disabled and the flip-flops set/reset, and then the outputs are
disabled about 10 ns later. The user may prefer to assert
the GTS or GSR signals before PWRDWN to affect the
order of events. When the PWRDWN signal is returned
High, the inputs will be enabled first, followed immediately
by the release of the GSR signal initializing the flip-flops.
About 10 ns later, the outputs will be enabled. Allow 50 ns
after the release of PWRDWN before using the device.
Power Down retains the configuration, but loses all data
stored in the device flip-flops. All inputs are interpreted as
Low, but the internal combinatorial logic is fully functional.
Make sure that the combination of all inputs Low and all
flip-flops set or reset in your design will not generate internal oscillations, or create permanent bus contention by activating internal bus drivers with conflicting data onto the
same long line.
During configuration, the PWRDWN pin must be High. If
the Power Down state is entered before or during configuration, the device will restart configuration once the
PWRDWN signal is removed. Note that the configuration
pins are affected by Power Down and may not reflect their
normal function. If there is an external pull-up resistor on
the DONE pin, it will be High during Power Down even if the
device is not yet configured. Similarly, if PWRDWN is
asserted before configuration is completed, the INIT pin will
not indicate status information.
TPWDW
PWRDWN
50ns
50ns
Power Down Mode
Outputs
Description
Symbol
Min
Max
Power Down Time
T PWD
T PWDW
50ns
-
50ns
-
Power Down Pulse Width
xap124_1
Figure 23: PWRDWN Pulse Timing
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Note that the PWRDWN pin is not part of the Boundary
Scan chain. Therefore, the Spartan-XL family has a separate set of BSDL files than the 5V Spartan family. Boundary
scan logic is not usable during Power Down.
Configuration and Test
Configuration is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. Spartan/XL devices use several hundred bits of configuration
data per CLB and its associated interconnects. Each configuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The Xilinx development system translates the design into a netlist file. It
automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Table 14: Pin Functions During Configuration (Spartan
family only)
CONFIGURATION MODE
<MODE Pin>
SLAVE
MASTER
SERIAL
SERIAL
<High>
<Low>
MODE (I)
MODE (I)
HDC (HIGH)
HDC (HIGH)
LDC (LOW)
LDC (LOW)
INIT
INIT
DONE
DONE
PROGRAM (I)
PROGRAM (I)
CCLK (I)
CCLK (O)
DIN (I)
DIN (I)
DOUT
DOUT
TDI
TDI
TCK
TCK
TMS
TMS
TDO
TDO
Configuration Mode Control
Notes
5V Spartan devices have two configuration modes.
•
•
MODE = 1 sets Slave Serial mode
MODE = 0 sets Master Serial mode
3V Spartan-XL devices have three configuration modes.
•
•
•
M1/M0 = 11 sets Slave Serial mode
M1/M0 = 10 sets Master Serial mode
M1/M0 = 0X sets Express mode
In addition to these modes, the device can be configured
through the Boundary Scan logic (See “Configuration
Through the Boundary Scan Pins” on page 31.).
The Mode pins are sampled prior to starting configuration
to determine the configuration mode. After configuration,
these pin are unused. The Mode pins have a weak pull-up
resistor of 20 kΩ to 100 kΩ turned on during configuration.
With the Mode pins High, Slave Serial mode is selected,
which is the most popular configuration mode. Therefore,
for the most common configuration mode, the Mode pins
can be left unconnected. If the Master Serial mode is
desired, the MODE/M0 pin should be connected directly to
GND, or through a pull-down resistor of 1 KΩ or less.
During configuration, some of the I/O pins are used temporarily for the configuration process. All pins used during
configuration are shown in Table 14 and Table 15.
4-22
MODE
I/O
I/O
I/O
DONE
PROGRAM
CCLK (I)
I/O
SGCK4-I/O
TDI-I/O
TCK-I/O
TMS-I/O
TDO-(O)
ALL OTHERS
1. A shaded table cell represents the internal pull-up
used before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
Table 15: Pin Functions During Configuration
(Spartan-XL family only)
CONFIGURATION MODE <M1:M0>
SLAVE
MASTER
SERIAL
SERIAL
EXPRESS
<1:1>
<1:0>
<0:X>
M1(HIGH) (I)
M1(HIGH) (I)
M1(LOW) (I)
M0(HIGH) (I)
M0(LOW) (I)
M0 (I)
HDC (HIGH)
HDC (HIGH)
HDC (HIGH)
LDC (LOW)
LDC (LOW)
LDC (LOW)
INIT
INIT
INIT
DONE
DONE
DONE
PROGRAM (I) PROGRAM (I) PROGRAM (I)
CCLK (I)
CCLK (O)
CCLK (I)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DIN (I)
DIN (I)
DATA 0 (I)
DOUT
DOUT
DOUT
TDI
TDI
TDI
TCK
TCK
TCK
TMS
TMS
TMS
TDO
TDO
TDO
CS1
Notes
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USER
OPERATION
USER
OPERATION
M1
M0
I/O
I/O
I/O
DONE
PROGRAM
CCLK (I)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GCK6-I/O
TDI-I/O
TCK-I/O
TMS-I/O
TDO-(O)
I/O
ALL OTHERS
1. A shaded table cell represents the internal pull-up
used before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Master Serial Mode
falling CCLK edge, and the next FPGA in the daisy chain
accepts data on the subsequent rising CCLK edge. See the
timing diagram in Figure 24.
The Master serial mode uses an internal oscillator to generate a Configuration Clock (CCLK) for driving potential
slave devices and the Xilinx serial-configuration PROM
(SPROM). The CCLK speed is selectable as either 1 MHz
(default) or 8 MHz. Configuration always starts at the
default slow frequency, then can switch to the higher frequency during the first frame. Frequency tolerance is -50%
to +25%.
In the bitstream generation software, the user can specify
Fast Configuration Rate, which, starting several bits into the
first frame, increases the CCLK frequency by a factor of
eight. For actual timing values please refer to the specification section. Be sure that the serial PROM and slaves are
fast enough to support this data rate. Devices such as
XC3000A and XC3100A do not support the Fast Configuration Rate option.
In Master Serial mode, the CCLK output of the device
drives a Xilinx SPROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The FPGA accepts this data on the subsequent rising
CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user I/O, but LDC is then
restricted to be a permanently High user output after configuration. Using DONE can also avoid contention on DIN,
provided the Early DONE option is invoked.
When used in a daisy-chain configuration the Master Serial
FPGA is placed as the first device in the chain and is
referred to as the lead FPGA. The lead FPGA presents the
preamble data, and all data that overflows the lead device,
on its DOUT pin. There is an internal pipeline delay of 1.5
CCLK periods, which means that DOUT changes on the
Figure 25 shows a full master/slave system. The leftmost
device is in Master Serial mode, all other devices in the
chain are in Slave Serial mode.
CCLK
(Output)
2 TCKDS
1
Serial Data In
Serial DOUT
(Output)
TDSCK
n
n–3
n+1
n–2
n+2
n–1
n
X3223
CCLK
Description
DIN setup
DIN hold
1
2
Symbol
TDSCK
TCKDS
Min
20
0
Max
Units
ns
ns
Notes: 1. At power-up, VCC must rise from 2.0V to VCC min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until VCC is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 24: Master Serial Mode Programming Switching Characteristics
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4-23
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Slave Serial Mode
Serial Daisy Chain
In Slave Serial mode, the FPGA receives serial configuration data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
Multiple devices with different configurations can be connected together in a "daisy chain," and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in Figure 25. Connect
the DOUT of each device to the DIN of the next. The lead or
master FPGA and following slaves each passes resynchronized configuration data coming from a single source. The
header data, including the length count, is passed through
and is captured by each FPGA when it recognizes the 0010
preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames.
In this mode, an external signal drives the CCLK input of
the FPGA (most often from a Master Serial device). The
serial configuration bitstream must be available at the DIN
input of the lead FPGA a short setup time before each rising CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge.
After an FPGA has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the FPGAs begin the start-up
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last configuration bit is received.
Figure 25 shows a full master/slave system. A Spartan/XL
device in Slave Serial mode should be connected as shown
in the third device from the left.
Slave Serial is the default mode if the Mode pins are left
unconnected, as they have weak pull-up resistors during
configuration.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM File Formatter must
be used to combine the bitstreams for a daisy-chained configuration.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
NOTE:
M2, M1, M0 can be shorted
to VCC if not used as I/O
VCC
3.3K
MODE
N/C
DOUT
MASTER
SERIAL
DOUT
CCLK
XC17S00
+5V
3.3K
CCLK
M0 M1
M2
MODE
DIN
VCC
Spartan
CLK
DIN
DATA
PROGRAM
LDC
CE
DONE
INIT
RESET/OE
3.3K
3.3K
PWRDN
DIN
DOUT
CCLK
Spartan
FPGA
SLAVE
SLAVE
VPP
CEO
PROGRAM
DONE
RESET
INIT
D/P
INIT
(Low Reset Option Used)
PROGRAM
S9025_02
Figure 25: Master/Slave Serial Mode Circuit Diagram
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DIN
Bit n
1 TDCC
Bit n + 1
2 TCCD
5 TCCL
CCLK
4 TCCH
DOUT
(Output)
3 TCCO
Bit n - 1
Bit n
X5379
CCLK
Description
DIN setup
DIN hold
DIN to DOUT
High time
Low time
Frequency
1
2
3
4
5
Symbol
TDCC
TCCD
TCCO
TCCH
TCCL
FCC
Min
20
0
Max
30
45
45
10
Units
ns
ns
ns
ns
ns
MHz
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 26: Slave Serial Mode Programming Switching Characteristics
Express Mode (Spartan-XL only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the configuration data shift registers (Figure 27). A CCLK frequency of 1 MHz is equivalent to a 8 MHz serial rate,
because eight bits of configuration data are loaded per
CCLK cycle. Express mode does not support CRC error
checking, but does support constant-field error checking. A
length count is not used in Express mode.
Express mode must be specified as an option to the development system. The Express mode bitstream is not compatible with the other configuration modes (see Table 16 on
page 28.) Express mode is selected by a <0X> on the
Mode pins (M1, M0).
The first byte of parallel configuration data must be available at the D inputs of the FPGA a short setup time before
the second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge
(Figure 28).
Pseudo Daisy Chain
Multiple devices with different configurations can be configured in a pseudo daisy chain provided that all of the devices
are in Express mode. A single combined bitstream is used
to configure the chain of Express mode devices. CCLK pins
are tied together and D0-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain.
Frame data is accepted only when CS1 is High and the
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device’s configuration memory is not already full. The lead
device in the chain has its CS1 input tied High (or floating,
since there is an internal pull-up). The status pin DOUT is
pulled Low after the header is received by all devices, and
remains Low until the device’s configuration memory is full.
DOUT is then pulled High to signal the next device in the
chain to accept the configuration data on the D0-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a large
number of devices are included in the chain, deactivate
some of the internal pull-ups, since the Low-driving DONE
pin of the last device in the chain must sink the current from
all pull-ups in the chain. The DONE pull-up is activated by
default. It can be deactivated using a development system
option.
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All Spartan-XL devices in Express mode are synchronized
to the DONE pin. User I/Os for each device become active
after the DONE pin for that device goes High. (The exact
timing is determined by development system options.)
Since the DONE pin is open-drain and does not drive a
High value, tying the DONE pins of all devices together prevents all devices in the chain from going High until the last
device in the chain has completed its configuration cycle. If
the DONE pin of a device is left unconnected, the device
becomes active as soon as that device has been configured. Because only Spartan-XL, XC4000XLA/XV, and
XC5200 devices support Express mode, only these
devices can be used to form an Express mode daisy chain.
4-25
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
V CC
8
M0
M1
CS1
DATA BUS
8
M0
CS1
DOUT
8
D0-D7
M1
To Additional
Optional
Daisy-Chained
Devices
DOUT
D0-D7
Optional
Daisy-Chained
Spartan-XL
VCC
Spartan-XL
3.3K
PROGRAM
INIT
PROGRAM
PROGRAM
INIT
DONE
CCLK
CCLK
INIT
DONE
CCLK
To Additional
Optional
Daisy-Chained
Devices
X6611_b
Figure 27: Express Mode Circuit Diagram
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DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
CCLK
Description
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency
Symbol
TIC
TDC
TCD
TCCH
TCCL
FCC
1
2
3
Min
5
20
0
45
45
Max
Units
µs
ns
ns
ns
ns
MHz
10
CCLK
1
TIC
INIT
TCD 3
2 T
DC
D0-D7
BYTE
0
BYTE
1
BYTE
6
DOUT
Header Received
FPGA Filled
X6710_m
Note: If not driven by the preceding DOUT, CS1 must remain High until the device is fully configured.
Figure 28: Express Mode Programming Switching Characteristics
Setting CCLK Frequency
In Master mode, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency
ranges from 0.5 MHz to 1.25 MHz for Spartan/XL devices.
In fast CCLK mode, the frequency ranges from 4 MHz to
10 MHz for Spartan/XL devices. The frequency is changed
to fast by an option when running the bitstream generation
software.
Data Stream Format
The data stream ("bitstream") format is identical for both
serial configuration modes, but different for the Spartan-XL
Express mode. In Express mode, the device becomes
active when DONE goes High, therefore no length count is
required. Additionally, CRC error checking is not supported
in Express mode. The data stream format is shown in
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Table 16. Bit-serial data is read from left to right. Express
mode data is shown with D0 at the left and D7 at the right.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Spartan-XL
Express mode). This header is followed by the actual configuration data in frames. The length and number of frames
depends on the device type (see Table 17). Each frame
begins with a start field and ends with an error check. In
serial modes, a postamble code is required to signal the
end of data for a single device. In all cases, additional
start-up bytes of data are required to provide four clocks for
the startup sequence at the end of configuration. Long
daisy chains require additional startup bytes to shift the last
data through the chain. All start-up bytes are "don’t cares".
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 16: Spartan/XL Data Stream Formats
Data Type
Serial Modes
(D0...)
Fill Byte
Preamble Code
Length Count
Fill Bits
Field Check Code
Start Field
Data Frame
CRC or Constant
Field Check
Extend Write Cycle
Postamble
11111111b
0010b
COUNT(23:0)
1111b
—
0b
DATA(n-1:0)
xxxx (CRC)
or 0110b
—
01111111b
Start-Up Bytes
FFh
Express Mode
(D0-D7)
(Spartan-XL only)
FFFFh
11110010b
COUNT(23:0)1
—
11010010b
11111110b
DATA(n-1:0)
11010010b
FFFFFFFFFFh
—
FFFFFFFFFFFFFFh2
LEGEND:
Unshaded
Once per bitstream
Light
Once per data frame
Dark
Once per device
Note 1: Not used by configuration logic.
Note 2: Development system may add more start-up
bytes.
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A selection of CRC or non-CRC error checking is allowed
by the bitstream generation software. The Spartan-XL
Express mode only supports non-CRC error checking. The
non-CRC error checking tests for a designated
end-of-frame field for each frame. For CRC error checking,
the software calculates a running CRC and inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an FPGA includes the last
seven data bits.
Detection of an error results in the suspension of data loading before DONE goes High, and the pulling down of the
INIT pin. In Master serial mode, CCLK continues to operate
externally. The user must detect INIT and initialize a new
configuration by pulsing the PROGRAM pin Low or cycling
VCC.
Cyclic Redundancy Check (CRC) for Configuration and Readback
The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and compares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 16. If a frame data
error is detected during the loading of the FPGA, the configuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 17: Spartan/XL Program Data
Device
Max System
Gates
CLBs
(Row x Col.)
IOBs
Part Number
Supply Voltage
Bits per Frame
Frames
Program Data
PROM Size
(bits)
Serial PROM
Express Mode
PROM Size
(bits)
XCS05
5,000
XCS10
10,000
XCS20
20,000
XCS30
30,000
XCS40
40,000
100
(10 x 10)
80
196
(14 x 14)
112
400
(20 x 20)
160
576
(24 x 24)
192
784
(28 x 28)
224
XCS05
XCS05XL
XCS10
XCS10XL
XCS20
XCS20XL
5V
126
428
53,936
53,984
3.3V
127
429
54,491
54,536
5V
166
572
94,960
95,008
3.3V
167
573
95,699
95,744
5V
226
788
178,096
178,144
3.3V
227
789
179,111
179,160
17S05
17S05XL
79,064
17S10
17S10XL
128,480
17S20
17S20XL
221,048
XCS30
XCS30XL
5V
3.3V
266
267
932
933
247,920 249,119
247,968 249,168
17S30
XCS40
XCS40XL
5V
306
1,076
329,264
329,312
3.3V
307
1,077
330,647
330,696
17S40
17S40XL
387,848
17S30XL
298,688
Notes: 1.Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits (+ 1 for
Spartan-XL device)
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 (+ 1 for Spartan-XL device)
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8, rounded up to the nearest byte
2.The user can add more "1" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any
frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra "one" bits,
even for extra leading ones at the beginning of the header.
3. Express mode adds 57 (XCS05XL, XCS10XL), or 53 (XCS20XL, XCS30XL, XCS40XL) bits per frame, + 24 additional bits.
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 29. The checksum consists of the 11 most significant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparison
to a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB outputs should not be included (Readback Capture option not
used), and if RAM is present, the RAM content must be
unchanged.
When VCC reaches an operational level, and the circuit
passes the write and read test of a sample pair of configuration bits, a time delay is started. This time delay is nominally 16 ms. The delay is four times as long when in Master
Serial Mode to allow ample time for all slaves to reach a
stable VCC. When all INIT pins are tied together, as recommended, the longest delay takes precedence. Therefore,
devices with different time delays can easily be mixed and
matched in a daisy chain.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
Statistically, one error out of 2048 might go undetected.
Configuration Sequence
X2
X15
X16
0 1
2
3
4
5
6
7
8
15
9 10 11 12 13 14
There are four major steps in the Spartan/XL power-up
configuration sequence.
SERIAL DATA IN
Polynomial: X16 + X15 + X2 + 1
Configuration Memory Clear
Initialization
Configuration
Start-up
The full process is illustrated in Figure 30.
1
1
1
1
LAST DATA FRAME
1
0 15 14 13 12 11 10 9
START BIT
•
•
•
•
8
7
6
5
CRC – CHECKSUM
Readback Data Stream
X1789
Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
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Figure 29: Circuit for Generating CRC-16
4-29
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
VCC
Valid
Boundary Scan
Instructions
Available:
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Configuration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscillator.
No
Yes
Test MODE, Generate
One Time-Out Pulse
of 16 or 64 ms
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configuration frames and then tests the INIT input.
PROGRAM
= Low
Yes
Keep Clearing
Configuration Memory
Initialization
EXTEST*
SAMPLE/PRELOAD
Completely Clear
BYPASS
Configuration Memory
CONFIGURE*
Once More
(* if PROGRAM = High)
INIT
High? if
Master
Yes
During initialization and configuration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
~1.3 µs per Frame
The open drain INIT pin is released after the final initialization pass through the frame addresses. There is a deliberate delay before a Master-mode device recognizes an
inactive INIT. Two internal clocks after the INIT pin is recognized as High, the device samples the MODE pin to determine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.
No
Master Delays Before
Sampling Mode Line
Sample
Mode Line
Load One
Configuration
Data Frame
Frame
Error
Yes
Pull INIT Low
and Stop
No
SAMPLE/PRELOAD
BYPASS
Configuration
memory
Full
LDC Output = L, HDC Output = H
Master CCLK
Goes Active
No
Yes
Pass
Configuration
Data to DOUT
CCLK
Count Equals
Length
Count
Start-Up
Sequence
I/O Active
F
Operational
The 0010 preamble code indicates that the following 24 bits
represent the length count for serial modes. The length
count is the total number of configuration clocks needed to
load the complete configuration data. (Four additional configuration clocks are required to complete the configuration
process, as discussed below.) After the preamble and the
length count have been passed through to any device in the
daisy chain, its DOUT is held High to prevent frame start
bits from reaching any daisy-chained devices. In Spartan-XL Express mode, the length count bits are ignored,
and DOUT is held Low, to disable the next device in the
pseudo daisy chain.
A specific configuration bit, early in the first frame of a master device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configuration clock is selected by the bitstream, the slower clock rate
is used until this configuration bit is detected.
No
Yes
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
Configuration
If Boundary Scan
is Selected
s6076_01
Figure 30: Power-up Configuration Sequence
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Each frame has a start field followed by the frame-configuration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an FPGA using a serial
mode, DOUT again follows the input data so that the
remaining data is passed on to the next device. In
Spartan-XL Express mode, when the first device is fully
programmed, DOUT goes High to enable the next device in
the chain.
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 30 on page 30.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
rise time is excessive or poorly defined. As long as PROGRAM is Low, the FPGA keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the beginning of configuration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The Spartan/XL PROGRAM pin has a permanent weak pull-up.
Avoid holding PROGRAM Low for more than 500 µs.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the
FPGA to wait after completing the configuration memory
clear operation. When INIT is no longer held Low externally,
the device determines its configuration mode by capturing
the state of the Mode pins, and is ready to start the configuration process. A master device waits up to an additional
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300 µs to make sure that any slaves in the optional daisy
chain have seen that INIT is High.
Configuration Through the Boundary Scan
Pins
Spartan/XL devices can be configured through the boundary scan pins. The basic procedure is as follows:
•
•
•
•
•
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
Issue the CONFIG command to the TMS input
Wait for INIT to go High
Sequence the boundary scan Test Access Port to the
SHIFT-DR state
Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note, "Boundary Scan in FPGA Devices." This application
note applies to Spartan and Spartan-XL devices.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
IF UNCONNECTED,
DEFAULT IS CCLK
DATA
CLK
READ_TRIGGER
TRIG
READBACK
RIP
READ_DATA
OBUF
IBUF
s1786_01
Figure 31: Readback Schematic Example
Readback
The user can read back the content of configuration memory and the level of certain internal nodes without interfering with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function generators used as RAMs.
Readback of Spartan-XL Express mode bitstreams results
in data that does not resemble the original bitstream,
because the bitstream format differs from other modes.
Spartan/XL Readback does not use any dedicated pins, but
uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, instantiate the
READBACK library symbol and attach the appropriate pad
symbols, as shown in Figure 31.
After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
Readback Options
Readback options are: Readback Capture, Readback
Abort, and Clock Select. They are set with the bitstream
generation software.
Readback Capture
When the Readback Capture option is selected, the \ data
stream includes sampled values of CLB and IOB signals.
The rising edge of RDBK.TRIG latches the inverted values
of the four CLB outputs, the IOB output flip-flops and the
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input signals I1 and I2. Note that while the bits describing
configuration (interconnect, function generators, and RAM
content) are not inverted, the CLB and IOB output signals
are inverted. RDBK.TRIG is located in the lower-left corner
of the device.
When the Readback Capture option is not selected, the values of the capture bits reflect the configuration data originally written to those memory locations. If the RAM
capability of the CLBs is used, RAM data are available in
Readback, since they directly overwrite the F and G function-table configuration of the CLB.
Readback Abort
When the Readback Abort option is selected, a
High-to-Low transition on RDBK.TRIG terminates the
Readback operation and prepares the logic to accept
another trigger.
After an aborted Readback, additional clocks (up to one
Readback clock per configuration frame) may be required
to re-initialize the control logic. The status of Readback is
indicated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If Readback
must be inhibited for security reasons, the Readback control nets are simply not connected. RDBK.CLK is located in
the lower right chip corner.
Violating the Maximum High and Low Time
Specification for the Readback Clock
The Readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling Readback,
an interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the
source of the maximum High and Low time requirements.
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the Readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
cation. It can also display selected internal signals on the
computer screen, acting as a low-cost in-circuit emulator.
Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
not measured directly. They are derived from benchmark
timing patterns that are taken at device introduction, prior to
any process improvements.
The user must precisely calculate the location of the Readback data relative to the frame. The system must keep track
of the position within a data frame, and disable interrupts
before frame boundaries. Frame lengths and data formats
are listed in Table 16 and Table 17.
The following guidelines reflect worst-case values over the
recommended operating conditions.
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the readback feature for bitstream verifi-
Finished
Internal Net
rdbk.TRIG
1 TRTRC
TRCRT
1 TRTRC
2
TRCRT
2
rdclk.I
4 TRCL
TRCH 5
rdbk.RIP
TRCRR
rdbk.DATA
6
DUMMY
TRCRD
DUMMY
VALID
7
Spartan and Spartan-XL Readback
Description
rdbk.TRIG
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdclk.1
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
Note 1:
Note 2:
VALID
X1790
1
2
7
6
5
4
Symbol
TRTRC
TRCRT
TRCRD
TRCRR
TRCH
TRCL
Min
200
50
250
250
Max
250
250
500
500
Units
ns
ns
ns
ns
ns
ns
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
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Configuration Switching Characteristics
Vcc
TPOR
RE-PROGRAM
>300 ns
PROGRAM
TPI
INIT
TICCK
TCCLK
CCLK OUTPUT or INPUT
<300 ns
Mode Pins
(Required)
DONE RESPONSE
VALID
x1532_01
<300 ns
I/O
Master Mode
Description
Power-on Reset
Program Latency
CCLK (output) Delay
CCLK (output) Period, slow
CCLK (output) Period, fast
Symbol
TPOR
TPI
Min
40
30
Max
130
200
TICCK
TCCLK
TCCLK
40
640
80
250
2000
250
Symbol
TPOR
TPI
Min
10
30
Max
33
200
TICCK
TCCLK
4
80
Units
ms
µ s per
CLB column
µs
ns
ns
Slave Mode
Description
Power-on Reset
Program Latency
CCLK (input) Delay (required)
CCLK (input) Period (required)
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Units
ms
µ s per
CLB column
µs
ns
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan Detailed Specifications
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families.
Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked:
Specifications not identified as either Advance or Preliminary are to be considered Final.
Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications.
Spartan Absolute Maximum Ratings1
Symbol
Value
Units
–0.5 to +7.0
V
Input voltage relative to GND (Note 2, 3)
–0.5 to VCC +0.5
V
Voltage applied to 3-state output (Note 2, 3)
–0.5 to VCC +0.5
V
Supply voltage relative to GND
VIN
VTS
TSTG
Storage temperature (ambient)
–65 to +150
°C
TSOL
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
+260
°C
Junction temperature
+125
°C
TJ
Note
Description
VCC
Plastic packages
1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
2: Maximum DC overshoot (above VCC) or undershoot (below GND) must be limited to either 0.5V or 10 mA, whichever is
easier to achieve.
3: Maximum AC (during transitions) conditions are as follows; the device pins may undershoot to –2.0V or overshoot to + 7.0V,
provided this overshoot or undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
Spartan Recommended Operating Conditions
Symbol
VCC
VIH
Description
Supply voltage relative to GND, TJ = 0°C to +85°C
Supply voltage relative to GND, TJ = –40°C to +100°C
High-level input voltage
VIL
Low-level input voltage
TIN
Input signal transition time
Commercial
Industrial
TTL inputs
CMOS inputs
TTL inputs
CMOS inputs
Min
4.75
4.5
2.0
70%
0
0
Max
5.25
5.5
VCC
100%
0.8
20%
250
Units
V
V
V
VCC
V
VCC
ns
Note 1: At junction temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35%
per °C.
Note 2: Input and output measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan DC Characteristics Over Operating Conditions
Symbol
VOH
VOL
Description
High-level output voltage @ IOH = –4.0 mA, VCC min
High-level output voltage @ IOH = –1.0 mA, VCC min
Low-level output voltage @ IOL = 12.0 mA, VCC min
(Note 1)
Min
2.4
VCC – 0.5
TTL outputs
CMOS outputs
TTL outputs
CMOS outputs
Commercial
Industrial
ICCO
Quiescent FPGA supply current (Note 2)
IL
CIN
IRPU
IRPD
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ V IN = 0V (sample tested)
Pad pull-down (when selected) @ VIN = 5V (sample tested)
Max
0.4
0.4
3.0
6.0
+10
10
0.25
–10
0.02
0.02
Units
V
V
V
V
mA
mA
µA
pF
mA
mA
Note 1: With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
Note 2: With no output current loads, no active input pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a
Tie option.
Spartan Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are
clocked by the global clock net.
When fewer vertical clock lines are connected, the clock
distribution is faster; when multiple clock lines per column
Description
are driven from the same global clock, the delay is longer.
For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the
values provided by the static timing analyzer (TRCE in the
Xilinx Development System) and back-annotated to the
simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer
report. All timing parameters assume worst-case operating
conditions (supply voltage and junction temperature).
Symbol
Speed Grade
-4
-3
Device
Max
Max
Units
From pad through Primary buffer, to any clock K
TPG
XCS05
XCS10
XCS20
XCS30
XCS40
2.0
2.4
2.8
3.2
3.5
4.0
4.3
5.4
5.8
6.4
ns
ns
ns
ns
ns
From pad through Secondary buffer, to any clock K
TSG
XCS05
XCS10
XCS20
XCS30
XCS40
2.5
2.9
3.3
3.6
3.9
4.4
4.7
5.8
6.2
6.7
ns
ns
ns
ns
ns
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan
devices and expressed in nanoseconds unless otherwise noted.
Description
Speed Grade
Symbol
Clocks
Clock High time
Clock Low time
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to C OUT
C IN through function generators to X/Y outputs
C IN to COUT, bypass function generators
Sequential Delays
Clock K to Flip-Flop outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H1 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
Hold Time after Clock K
All Hold times, all devices
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Q
Toggle Frequency (MHz)
(for export control purposes)
TCH
TCL
-4
Min
-3
Max
3.0
3.0
Min
Max
4.0
4.0
Units
ns
ns
TILO
TIHO
THH1O
1.2
2.0
1.7
1.6
2.7
2.2
ns
ns
ns
TOPCY
TASCY
TINCY
TSUM
TBYP
1.7
2.8
1.2
2.0
0.5
2.1
3.7
1.4
2.6
0.6
ns
ns
ns
ns
ns
TCKO
2.1
2.8
ns
TICK
TIHCK
THH1CK
TDICK
TECCK
TRCK
TRPW
TRIO
TMRW
TMRQ
FTOG
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1.8
2.9
2.3
1.3
2.0
2.5
2.4
3.9
3.3
2.0
2.6
4.0
ns
ns
ns
ns
ns
ns
0.0
0.0
ns
3.0
4.0
3.0
4.0
11.5
13.5
See page 42 for TRRI values per device.
166
125
ns
ns
ns
MHz
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan
devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM
Speed Grade
-4
-3
Units
Size
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
TWCS
TWCTS
8.0
8.0
11.6
11.6
ns
ns
Clock K pulse width (active edge)
16x2
32x1
TWPS
TWPTS
4.0
4.0
5.8
5.8
ns
ns
Address setup time before clock K
16x2
32x1
TASS
TASTS
1.5
1.5
2.0
2.0
ns
ns
Address hold time after clock K
16x2
32x1
TAHS
TAHTS
0.0
0.0
0.0
0.0
ns
ns
DIN setup time before clock K
16x2
32x1
TDSS
TDSTS
1.5
1.5
2.7
1.7
ns
ns
DIN hold time after clock K
16x2
32x1
TDHS
TDHTS
0.0
0.0
0.0
0.0
ns
ns
WE setup time before clock K
16x2
32x1
TWSS
TWSTS
1.5
1.5
1.6
1.6
ns
ns
WE hold time after clock K
16x2
32x1
TWHS
TWHTS
0.0
0.0
0.0
0.0
ns
ns
Data valid after clock K
16x2
32x1
TWOS
TWOTS
Address read cycle time
16x2
32x1
TRC
TRCT
Data Valid after address change (no Write
Enable)
16x2
32x1
TILO
TIHO
Address setup time before clock K
16x2
32x1
TICK
TIHCK
6.5
7.0
7.9
9.3
ns
ns
Read Operation
2.6
3.8
2.6
3.8
1.2
2.0
1.8
2.9
ns
ns
1.6
2.7
2.4
3.9
ns
ns
ns
ns
Note: Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan
devices and are expressed in nanoseconds unless otherwise noted.
Speed Grade
Dual Port RAM
-4
-3
Units
Size
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
TWCDS
TWPDS
TASDS
TAHDS
TDSDS
TDHDS
TWSDS
TWHDS
TWODS
8.0
4.0
1.5
0.0
1.5
0.0
1.5
0.0
11.6
5.8
2.1
0.0
1.6
0.0
1.6
0.0
6.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.0
Note 1: Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing.
Spartan CLB RAM Synchronous (Edge-Triggered) Write Timing
TWPS
TWPDS
WCLK (K)
WCLK (K)
TWHS
TWSS
WE
TWSDS
TWHDS
TDSDS
TDHDS
TASDS
TAHDS
WE
TDHS
TDSS
DATA IN
DATA IN
TASS
TAHS
ADDRESS
ADDRESS
TILO
DATA OUT
TWOS
OLD
TILO
TILO
TILO
TWODS
DATA OUT
NEW
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NEW
X6474
X6461
Single Port
OLD
Dual Port
4-39
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report.
Spartan Output Flip-Flop, Clock-to-Out
Description
Speed Grade
-4
-3
Device
Max
Max
Symbol
Units
Global Primary Clock to TTL Output using OFF
Fast
TICKOF
XCS05
XCS10
XCS20
XCS30
XCS40
5.3
5.7
6.1
6.5
6.8
8.7
9.1
9.3
9.4
10.2
ns
ns
ns
ns
ns
Slew-rate limited
TICKO
XCS05
XCS10
XCS20
XCS30
XCS40
9.0
9.4
9.8
10.2
10.5
11.5
12.0
12.2
12.8
12.8
ns
ns
ns
ns
ns
Fast
TICKSOF
XCS05
XCS10
XCS20
XCS30
XCS40
5.8
6.2
6.6
7.0
7.3
9.2
9.6
9.8
9.9
10.7
ns
ns
ns
ns
ns
Slew-rate limited
TICKSO
XCS05
XCS10
XCS20
XCS30
XCS40
9.5
9.9
10.3
10.7
11.0
12.0
12.5
12.7
13.2
14.3
ns
ns
ns
ns
ns
Global Secondary Clock to TTL Output using OFF
Delay Adder for CMOS Outputs Option
Fast
TCMOSOF
All devices
0.8
1.0
ns
Slew-rate Limited
TCMOSO
All devices
1.5
2.0
ns
OFF = Output Flip-Flop
Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 32.
Figure 32 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specified output
delay. Figure 32 is usable over the specified operating conditions of voltage and temperature and is independent of
the output slew rate control.
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Figure 32: Delay Factor at Various Capacitive Loads
3
Delta Delay (ns)
Capacitive Load Factor
2
1
0
-1
-2
0
20
40
60
80 100 120 140
Capacitance (pF)
X8257
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading.
Spartan Primary and Secondary Setup and Hold
Description
Input Setup/Hold Times Using Primary Clock and IFF
No Delay
With Delay
Input Setup/Hold Times Using Secondary Clock and IFF
No Delay
With Delay
Symbol
Speed Grade
Device
TPSUF/TPHF
TPSU /TPH
TSSUF/TSHF
TSSU /TSH
-4
Min
-3
Min
Units
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
1.2 / 1.7
1.0 / 2.3
0.8 / 2.7
0.6 / 3.0
0.4 / 3.5
4.3 / 0.0
4.3 / 0.0
4.3 / 0.0
4.3 / 0.0
5.3 / 0.0
1.8 / 2.5
1.5 / 3.4
1.2 / 4.0
0.9 / 4.5
0.6 / 5.2
6.0 / 0.0
6.0 / 0.0
6.0 / 0.0
6.0 / 0.0
6.8 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
0.9 / 2.2
0.7 / 2.8
0.5 / 3.2
0.3 / 3.5
0.1 / 4.0
4.0 / 0.0
4.0 / 0.0
4.0 / 0.5
4.0 / 0.5
5.0 / 0.0
1.5 / 3.0
1.2 / 3.9
0.9 / 4.5
0.6 / 5.0
0.3 / 5.7
5.7 / 0.0
5.7 / 0.0
5.7 / 0.5
5.7 / 0.5
6.5 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IFF = Input Flip-flop or Latch
Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a
reference load of one clock pin per IOB/CLB.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
Description
Setup Times - TTL Inputs (Note 1)
Clock Enable (EC) to Clock (IK), no delay
Pad to Clock (IK), no delay
Hold Times
Clock Enable (EC) to Clock (IK), no delay
All Other Hold Times
Propagation Delays - TTL Inputs (Note 1)
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
Delay Adder for Input with Delay Option
TECIKD = TECIK + TDelay
TPICKD = TPICK + TDelay
TPDLI = TPLI + TDelay
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Q
Speed Grade
Symbol
Device
-4
Min
-3
Max
Min
Max
Units
TECIK
TPICK
All devices
All devices
1.6
1.5
2.1
2.0
ns
ns
TIKEC
All devices
All devices
0.0
0.0
0.9
0.0
ns
ns
TPID
TPLI
TIKRI
TIKLI
All devices
All devices
All devices
All devices
TDelay
XCS05
XCS10
XCS20
XCS30
XCS40
3.6
3.7
3.8
4.5
5.5
TMRW
TRRI
All devices
XCS05
XCS10
XCS20
XCS30
XCS40
11.5
1.5
2.8
2.7
3.2
2.0
3.6
2.8
3.9
4.0
4.1
4.2
5.0
5.5
ns
ns
ns
ns
ns
13.5
9.0
9.5
10.0
10.5
11.0
ns
ns
ns
ns
11.3
11.9
12.5
13.1
13.8
ns
ns
ns
ns
ns
ns
Note 1: Delay adder for CMOS Inputs option: for -3 speed grade, add 0.4 ns; for -4 speed grade, add 0.2 ns.
Note 2: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the
clock input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
Note 3: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless
otherwise noted.
Speed Grade
Description
Symbol
-4
Device
Min
TCH
TCL
All devices
All devices
3.0
3.0
TOKPOF
TOKPOS
TOPF
TOPS
TTSHZ
TTSONF
TTSONS
All devices
All devices
All devices
All devices
All devices
All devices
All devices
TOOK
TOKO
TECOK
TOKEC
All devices
All devices
All devices
All devices
2.5
0.0
2.0
0.0
Minimum GSR pulse width
TMRW
All devices
11.5
Delay from GSR input to any Pad
TRPO
XCS05
XCS10
XCS20
XCS30
XCS40
-3
Max
Min
Max
Units
Clocks
Clock High
Clock Low
4.0
4.0
ns
ns
Propagation Delays - TTL Outputs (Notes 1, 2)
Clock (OK) to Pad, fast
Clock (OK to Pad, slew-rate limited
Output (O) to Pad, fast
Output (O) to Pad, slew-rate limited
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid, fast
3-state to Pad active and valid, slew-rate limited
3.3
6.9
3.6
7.2
3.0
6.0
9.6
4.5
7.0
4.8
7.3
3.8
7.3
9.8
ns
ns
ns
ns
ns
ns
ns
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
3.8
0.0
2.7
0.5
ns
ns
ns
ns
Global Set/Reset
13.5
12.0
12.5
13.0
13.5
14.0
ns
15.0
15.7
16.2
16.9
17.5
ns
ns
ns
ns
ns
Note 1: Delay adder for CMOS Outputs option (with fast slew rate option): for -3 speed grade, add 1.0 ns; for -4 speed grade, add 0.8 ns.
Note 2: Delay adder for CMOS Outputs option (with slow slew rate option): for -3 speed grade, add 2.0 ns; for -4 speed grade, add 1.5 ns.
Note 3: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited
output rise/fall times are approximately two times longer than fast output rise/fall times.
Note 4: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL Detailed Specifications
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications.
Spartan-XL Absolute Maximum Ratings1
Symbol
VCC
Description
Supply voltage relative to GND
VIN
Input voltage relative to GND (Note 2, 3, 4,
5)
5V Tolerant I/O Checked2, 3
VTS
Voltage applied to 3-state output (Note 2,
3, 4, 5)
5V Tolerant I/O Checked2, 3
Not 5V Tolerant I/Os4, 5
Not 5V Tolerant I/Os4, 5
VCCt
Longest supply voltage rise time from 1V to 3V
TSTG
Storage temperature (ambient)
TSOL
TJ
Note
Value
Units
–0.5 to 4.0
V
–0.5 to 5.5
V
–0.5 to VCC + 0.5
V
–0.5 to 5.5
V
–0.5 to VCC + 0.5
V
50
ms
–65 to +150
°C
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
+260
°C
Junction temperature
+125
°C
Plastic packages
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
2: With 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either +5.5 V or 10 mA and undershoot (below
GND) must be limited to either 0.5 V or 10 mA, whichever is easier to achieve.
3: With 5V Tolerant I/Os selected, the Maximum AC (during transitions) conditions are as follows; the device pins may
undershoot to –2.0 V or overshoot to + 7.0 V, provided this overshoot or undershoot lasts no more than 11 ns with a forcing
current no greater than 100 mA.
4: Without 5V Tolerant I/Os selected, the Maximum DC overshoot or undershoot must be limited to either 0.5 V or 10 mA,
whichever is easier to achieve.
5: Without 5V Tolerant I/Os selected, the Maximum AC conditions are as follows; the device pins may undershoot to –2.0 V or
overshoot to VCC + 2.0 V, provided this overshoot or undershoot lasts no more than 11 ns with a forcing current no greater
than 100 mA.
Spartan-XL Recommended Operating Conditions
Symbol
Description
Min
Max
Units
Supply voltage relative to GND, TJ = 0°C to +85°C
Commercial
3.0
3.6
V
VCC
Supply voltage relative to GND, TJ = –40°C to
+100°C
Industrial
3.0
3.6
V
VIH
High-level input voltage
50% of V CC
5.5
V
VIL
Low-level input voltage
0
30% of VCC
V
TIN
Input signal transition time
250
ns
Notes: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
Input and output measurement threshold is ~50% of VCC.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL DC Characteristics Over Operating Conditions
Symbol
VOH
VOL
Description
Min
High-level output voltage @ IOH = –4.0 mA, VCC min (LVTTL)
2.4
High-level output voltage @ IOH = –500 µA, (LVCMOS)
Typ.
Max
Units
V
90% VCC
V
Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL)
(Note 1)
0.4
V
Low-level output voltage @ IOL = 24.0 mA, VCC min (LVTTL)
(Note 2)
0.4
V
10% VCC
V
Low-level output voltage @ IOL = 1500 µA, (LVCMOS)
VDR
Data retention supply voltage (below which configuration data
may be lost)
ICCO
Quiescent FPGA supply current (Notes 3,4)
0.1
5
mA
ICCPD
Power Down FPGA supply current (Notes 3,5)
0.1
5
mA
+10
µA
10
pF
0.25
mA
IL
Input or output leakage current
2.5
–10
CIN
Input capacitance (sample tested)
IRPU
Pad pull-up (when selected) @ V IN = 0V (sample tested)
0.02
IRPD
Pad pull-down (when selected) @ VIN = 3.3V (sample tested)
0.02
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
V
mA
With up to 64 pins simultaneously sinking 12 mA (default mode).
With up to 64 pins simultaneously sinking 24 mA (with 24 mA option selected).
With 5V tolerance not selected, no internal oscillators, and the FPGA configured with the Tie option.
With no output current loads, no active input resistors, and all package pins at VCC or GND.
With PWRDWN active.
Power-on Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the required
power supply voltage of the device from 0V. The current is highest at the fastest suggested ramp rate (2 ms) and is lowest
at the slowest allowed ramp rate (50 ms).
Product
Spartan-XL Family
Note 1:
Note 2:
Note 3:
Description
Minimum required current supply
Ramp-up Time
Fast (2 ms)
Slow (50 ms)
100 mA
100 mA
Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may
result in larger initialization current.
This specification applies to Commercial and Industrial grade products only. Advance information based on initial
characterization.
Ramp-up Time is measured at 0V to 3.0V. Peak current required lasts less than 3 ms and occurs near the internal power-on
reset threshold voltage.
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4-45
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
Description
From pad through buffer, to any clock K
Symbol
TGLS
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Speed Grade
-5
-4
Device
Max
Max
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
1.4
1.7
2.0
2.3
2.6
1.5
1.8
2.1
2.5
2.8
Units
ns
ns
ns
ns
ns
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Spartan-XL devices and expressed in nanoseconds unless otherwise noted.
Description
Clocks
Clock High time
Clock Low time
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via H1 via H to X/Y outputs
Sequential Delays
Clock K to Flip-Flop or latch outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H
Hold Time after Clock K
All Hold times, all devices
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Global Set/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q
Toggle Frequency (MHz)
(for export control purposes)
Speed Grade
Symbol
Min
-5
TCH
TCL
2.0
2.0
-4
Max
Min
Max
2.3
2.3
Units
ns
ns
TILO
TIHO
TITO
THH1O
1.0
1.7
1.5
1.5
1.1
2.0
1.8
1.8
ns
ns
ns
ns
TCKO
1.2
1.4
ns
TICK
TIHCK
TRPW
TRIO
TMRW
TMRQ
FTOG
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0.6
1.3
0.7
1.6
ns
ns
0.0
0.0
ns
2.5
2.8
2.3
2.7
10.5
11.5
See page 51 for TRRI values per device.
250
217
ns
ns
ns
MHz
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Spartan-XL devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM
Speed Grade
1
Size
-5
-4
Units
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
TWCS
TWCTS
7.7
7.7
8.4
8.4
ns
ns
Clock K pulse width (active edge)
16x2
32x1
TWPS
TWPTS
3.1
3.1
3.6
3.6
ns
ns
Address setup time before clock K
16x2
32x1
TASS
TASTS
1.3
1.5
1.5
1.7
ns
ns
DIN setup time before clock K
16x2
32x1
TDSS
TDSTS
1.5
1.8
1.7
2.1
ns
ns
WE setup time before clock K
16x2
32x1
TWSS
TWSTS
1.4
1.3
1.6
1.5
ns
ns
16x2
32x1
TWOS
TWOTS
Address read cycle time
16x2
32x1
TRC
TRCT
Data Valid after address change (no Write
Enable)
16x2
32x1
TILO
TIHO
Address setup time before clock K
16x2
32x1
TICK
TIHCK
All hold times after clock K
Data valid after clock K
0.0
0.0
4.5
5.4
ns
5.3
6.3
ns
ns
Read Operation
2.6
3.8
3.1
5.5
1.0
1.7
0.6
1.3
ns
ns
1.1
2.0
0.7
1.6
ns
ns
ns
ns
Note 1: Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Spartan-XL devices and are expressed in nanoseconds unless otherwise noted.
Speed Grade
Dual Port RAM
-5
-4
Units
Size1
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
WE setup time before clock K
All hold times after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
TWCDS
TWPDS
TASDS
TDSDS
TWSDS
7.7
3.1
1.3
1.7
1.4
0.0
TWODS
8.4
3.6
1.5
2.0
1.6
0.0
5.2
ns
ns
ns
ns
ns
ns
ns
6.1
Note 1: Read Operation Timing for 16x1 dual-port RAM option is identical to 16x2 single-port RAM timing.
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Timing
TWPS
TWPDS
WCLK (K)
WCLK (K)
TWHS
TWSS
WE
TWSDS
TWHDS
TDSDS
TDHDS
TASDS
TAHDS
WE
TDHS
TDSS
DATA IN
DATA IN
TASS
TAHS
ADDRESS
ADDRESS
TILO
DATA OUT
TWOS
OLD
TILO
TILO
TILO
TWODS
DATA OUT
NEW
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NEW
X6474
X6461
Single Port
OLD
Dual Port
4-49
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading.
Spartan-XL Output Flip-Flop, Clock-to-Out
Description
Speed Grade
-5
-4
Device
Max
Max
TICKOF
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
4.6
4.9
5.2
5.5
5.8
5.2
5.5
5.8
6.2
6.5
ns
ns
ns
ns
ns
TSLOW
All Devices
1.5
1.7
ns
Symbol
Units
Global Clock to Output using OFF
Fast
Slew Rate Adjustment
For Output SLOW option add
OFF = Output Flip Flop
Note 1: Output delays are representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load.
Spartan-XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading.
Spartan-XL Setup and Hold
Description
Input Setup/Hold Times Using Global Clock and IFF
No Delay
Full Delay
Symbol
TSUF /THF
TSU/TH
Speed Grade
Device
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
-5
Min
-4
Min
Units
1.1/2.0
1.0/2.2
0.9/2.4
0.8/2.6
0.7/2.8
3.9/0.0
4.1/0.0
4.3/0.0
4.5/0.0
4.7/0.0
1.6/2.6
1.5/2.8
1.4/3.0
1.3/3.2
1.2/3.4
5.1/0.0
5.3/0.0
5.5/0.0
5.7/0.0
5.9/0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IFF = Input Flip-Flop or Latch
Note 3: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a
reference load of one clock pin per IOB/CLB.
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Capacitive Load Factor
3
Delta Delay (ns)
Figure 33 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specified output
delay. Figure 33 is usable over the specified operating conditions of voltage and temperature and is independent of
the output slew rate control.
2
1
0
-1
-2
0
20
40 60 80 100 120 140
Capacitance (pF)
X8257
Figure 33: Delay Factor at Various Capacitive Loads
Spartan-XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
Description
Setup Times
Clock Enable (EC) to Clock (IK)
Pad to Clock (IK), no delay
Pad to Fast Capture Latch Enable (OK), no delay
Hold Times
All Hold Times
Propagation Delays
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
Delay Adder for Input with Full Delay Option
TPICKD = TPICK + TDelay
TPDLI = TPLI + TDelay
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Q
Speed Grade
Symbol
Device
TECIK
TPICK
TPOCK
-5
Min
-4
Max
Min
Max
Units
All devices
All devices
All devices
0.0
1.0
0.7
0.0
1.2
0.8
ns
ns
ns
All devices
0.0
0.0
ns
TPID
TPLI
TIKRI
TIKLI
All devices
All devices
All devices
All devices
0.9
2.1
1.0
1.1
TDelay
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
4.0
4.8
5.0
5.5
6.5
TMRW
TRRI
All devices
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
10.5
1.1
2.5
1.1
1.2
4.7
5.6
5.9
6.5
7.6
ns
ns
ns
ns
ns
11.5
9.0
9.5
10.0
11.0
12.0
ns
ns
ns
ns
10.5
11.0
11.5
12.5
13.5
ns
ns
ns
ns
ns
ns
Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the
clock input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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4-51
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless
otherwise noted.
Speed Grade
Description
Symbol
Device
-5
Min
-4
Max
Min
Max
Units
Propagation Delays
Clock (OK) to Pad, fast
Output (O) to Pad, fast
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid, fast
Output (O) to Pad via Output Mux, fast
Select (OK) to Pad via Output Mux, fast
For Output SLOW option add
TOKPOF
TOPF
TTSHZ
TTSONF
TOFPF
TOKFPF
TSLOW
All devices
All devices
All devices
All devices
All devices
All devices
All devices
TOOK
TOKO
TECOK
TOKEC
All devices
All devices
All devices
All devices
0.5
0.0
0.0
0.1
0.5
0.0
0.0
0.2
ns
ns
ns
ns
Minimum GSR pulse width
TMRW
All devices
10.5
11.5
ns
Delay from GSR input to any Pad
TRPO
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
3.2
2.5
2.8
2.6
3.7
3.3
1.5
3.7
2.9
3.3
3.0
4.4
3.9
1.7
ns
ns
ns
ns
ns
ns
ns
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
Global Set/Reset
11.9
12.4
12.9
13.9
14.9
14.0
14.5
15.0
16.0
17.0
ns
ns
ns
ns
ns
Note 1: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited
output rise/fall times are approximately two times longer than fast output rise/fall times.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Pin Descriptions
There are three types of pins in the Spartan/XL devices:
•
•
•
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with the I/O pull-up
resistor network activated. After configuration, if an IOB is
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unused it is configured as an input with the I/O pull-up
resistor network remaining activated.
Any user I/O can be configured to drive the Global
Set/Reset net GSR or the global three-state net GTS. See
“Global Signals: GSR and GTS” on page 18 for more information.
Device pins for Spartan/XL devices are described in
Table 18.
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 18: Pin Descriptions
I/O
I/O
During
After
Pin Name
Config. Config.
Permanently Dedicated Pins
Pin Description
Eight or more (depending on package) connections to the nominal +5V supply voltage
(+3.3V for Spartan-XL devices). All must be connected, and each must be decoupled
with a 0.01 –0.1 µF capacitor to Ground.
Eight or more (depending on package type) connections to Ground. All must be conGND
X
X
nected.
During configuration, Configuration Clock (CCLK) is an output in Master mode and is an
input in Slave mode. After configuration, CCLK has a weak pull-up resistor and can be
selected as the Readback Clock. There is no CCLK High or Low time restriction on
CCLK
I or O
I
Spartan/XL devices, except during Readback. See “Violating the Maximum High and
Low Time Specification for the Readback Clock” on page 32 for an explanation of this
exception.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on DONE
DONE
I/O
O
can be configured to delay the global logic initialization and the enabling of outputs.
The optional pull-up resistor is selected as an option in the program that creates the configuration bitstream. The resistor is included by default.
PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
I
I
PROGRAM
goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to VCC.
The Mode input(s) are sampled after INIT goes High to determine the configuration
MODE
mode to be used.
(Spartan)
During configuration, these pins have a weak pull-up resistor. For the most popular conI
X
M0, M1
figuration mode, Slave Serial, the mode pins can be left unconnected. For Master Serial
(Spartan-XL)
mode, connect the Mode/M0 pin directly to system ground.
PWRDWN is an active Low input that forces the FPGA into the Power Down state and
reduces power consumption. When PWRDWN is Low, the FPGA disables all I/O and
initializes all flip-flops. All inputs are interpreted as Low independent of their actual level.
VCC must be maintained, and the configuration data is maintained. PWRDWN halts
I
I
PWRDWN
configuration if asserted before or during configuration, and re-starts configuration when
removed. When PWRDWN returns High, the FPGA becomes operational by first enabling the inputs and flip-flops and then enabling the outputs. PWRDWN has a default
internal pull-up resistor.
User I/O Pins That Can Have Special Functions
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
TDO
O
O
To use this pin, place the library component TDO instead of the usual pad symbol. An
output buffer must still be used.
VCC
X
X
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 18: Pin Descriptions (Continued)
Pin Name
I/O
I/O
During
After
Config. Config.
TDI, TCK,
TMS
I
I/O
or I
(JTAG)
HDC
O
I/O
LDC
O
I/O
INIT
I/O
I/O
PGCK1 PGCK4
(Spartan)
Weak
Pull-up
I or I/O
SGCK1 SGCK4
(Spartan)
Weak
Pull-up
I or I/O
GCK1 - GCK8
(Spartan-XL)
Weak
Pull-up
I or I/O
I
I/O
I
I/O
I
I/O
CS1
(Spartan-XL)
D0-D7
(Spartan-XL)
DIN
Pin Description
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are inhibited once configuration is completed, and these pins become user-programmable I/O.
In this case, they must be called out by special library elements. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used.
High During Configuration (HDC) is driven High until the I/O go active. It is available as
a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
control output indicating that configuration is not yet completed. After configuration, LDC
is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ external
pull-up resistor is recommended.
As an active Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active Low input, it can be used
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 30 to 300 µs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
Four Primary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. If not used to drive a global buffer, any of these pins is a user-programmable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol
connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
Four Secondary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins.
Eight Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used
to drive a global net, any of these pins is a user-programmable I/O pin.
The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew Buffers.
Any input pad symbol connected directly to the input of a BUFGLS symbol is automatically placed on one of these pins.
During Express configuration, CS1 is used as a serial-enable signal for daisy-chaining.
During Express configuration, these eight input pins receive configuration data. After
configuration, they are user-programmable I/O pins.
During Slave Serial or Master Serial configuration, DIN is the serial configuration data
input receiving data on the rising edge of CCLK. After configuration, DIN is a user-programmable I/O pin.
4-54
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 18: Pin Descriptions (Continued)
Pin Name
I/O
I/O
During
After
Config. Config.
Pin Description
During Slave Serial or Master Serial configuration, DOUT is the serial configuration data
output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on
the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the DIN
DOUT
O
I/O
input.
In Spartan-XL Express mode, DOUT is the status output that can drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O Pins
These pins can be configured to be input and/or output after configuration is completed.
Weak
I/O
I/O
Before configuration is completed, these pins have an internal high-value pull-up resisPull-up
tor network that defines the logic level as High.
Device-Specific Pinout Tables
Device-specific tables include all packages for each Spartan and Spartan-XL device. They follow the pad locations around
the die, and include boundary scan register locations.
XCS05 & XCS05XL Device Pinouts
XCS05/XL
Pad Name
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK1 †, GCK8 ††
VCC
GND
I/O, PGCK1 †, GCK1 ††
I/O
I/O, TDI
I/O, TCK
I/O, TMS
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK2 †, GCK2 ††
Not Connected †, M1 ††
GND
MODE †, M0 ††
VCC
Not Connected †,
PWRDWN ††
I/O, PGCK2 †, GCK3 ††
I/O (HDC)
PC84
VQ100
Bndry Scan
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
32
35
38
41
44
47
50
53
56
59
62
65
68
71
74
77
83
86
89
92
95
98
104
107
110
113
116
119
122
125
126 †
P35
P36
P27
P28
127 ‡
130 ‡
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XCS05/XL
Pad Name
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK3 †, GCK4 ††
GND
DONE
VCC
PROGRAM
I/O (D7 ††)
I/O, PGCK3 †, GCK5 ††
I/O (D6 ††)
I/O
I/O (D5 ††)
I/O
I/O
I/O
I/O (D4 ††)
I/O
VCC
GND
I/O (D3 ††)
I/O
I/O
I/O (D2 ††)
I/O
PC84
VQ100
Bndry Scan
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
133 ‡
136 ‡
139 ‡
142 ‡
145 ‡
148 ‡
151 ‡
154 ‡
157 ‡
160 ‡
163 ‡
166 ‡
169 ‡
172 ‡
175 ‡
178 ‡
181 ‡
184 ‡
187 ‡
190 ‡
193 ‡
196 ‡
199 ‡
202 ‡
205 ‡
208 ‡
211 ‡
214 ‡
217 ‡
220 ‡
223 ‡
229 ‡
232 ‡
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05/XL
Pad Name
I/O (D1 ††)
I/O
I/O (D0 ††, DIN)
I/O, SGCK4 †, GCK6 ††
(DOUT)
CCLK
VCC
O, TDO
GND
I/O
I/O, PGCK4 †, GCK7 ††
I/O (CS1 ††)
I/O
I/O
PC84
VQ100
Bndry Scan
P69
P70
P71
P72
P70
P71
P72
P73
235 ‡
238 ‡
241 ‡
244 ‡
P73
P74
P75
P76
P77
P78
P79
P80
P81
P74
P75
P76
P77
P78
P79
P80
P81
P82
0
2
5
8
11
14
XCS05/XL
Pad Name
I/O
I/O
I/O
I/O
I/O
GND
2/8/00
PC84
VQ100
Bndry Scan
P82
P83
P84
P1
P83
P84
P85
P86
P87
P88
17
20
23
26
29
-
† = 5V Spartan only
†† = 3V Spartan-XL only
‡ The “PWRDWN ” on the XCS05XL is not part of the Boundary
Scan chain. For the XCS05XL, subtract 1 from all Boundary Scan
numbers from GCK3 on (127 and higher).
XCS10 & XCS10XL Device Pinouts
XCS10/XL
Pad Name
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O, SGCK1 †,
GCK8 ††
VCC
GND
I/O, PGCK1 †,
GCK1 ††
I/O
I/O
I/O
I/O, TDI
I/O, TCK
GND
I/O
I/O
I/O, TMS
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
PC84
VQ100
CS144††
TQ144
Bndry
Scan
P2
P3
P4
P5
P6
P7
P8
P9
P10
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
D7
A6
B6
C6
D6
A5
B5
C5
D5
A4
B4
C4
A3
B3
C3
A2
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
44
47
50
53
56
59
62
65
68
71
74
77
80
83
P11
P12
P13
P100
P1
P2
B2
A1
B1
P144
P1
P2
86
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
-
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
-
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
G2
G1
G3
G4
H1
H2
H3
H4
J1
J2
J3
J4
K1
K2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
89
92
95
98
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143
146
149
152
155
158
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XCS10/XL
Pad Name
I/O
I/O
I/O, SGCK2 †,
GCK2 ††
Not Connected †,
M1 ††
GND
MODE †, M0 ††
VCC
Not Connected †,
PWRDWN ††
I/O, PGCK2 †,
GCK3 ††
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O, SGCK3 †,
GCK4 ††
GND
DONE
VCC
PROGRAM
PC84
VQ100
CS144††
TQ144
Bndry
Scan
P28
P29
P20
P21
K3
L1
L2
P31
P32
P33
161
164
167
P30
P22
L3
P34
170
P31
P32
P33
P34
P23
P24
P25
P26
M1
M2
N1
N2
P35
P36
P37
P38
173
174 †
P35
P27
M3
P39
175 ‡
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
N3
K4
L4
M4
N4
K5
L5
M5
N5
K6
L6
M6
N6
M7
N7
L7
K7
N8
M8
L8
K8
N9
M9
L9
K9
N10
M10
L10
N11
M11
L11
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
178 ‡
181 ‡
184 ‡
187 ‡
190 ‡
193 ‡
196 ‡
199 ‡
202 ‡
205 ‡
208 ‡
211 ‡
214 ‡
217 ‡
220 ‡
223 ‡
226 ‡
229 ‡
232 ‡
235 ‡
238 ‡
241 ‡
244 ‡
247 ‡
250 ‡
253 ‡
256 ‡
P52
P53
P54
P55
P49
P50
P51
P52
N12
M12
N13
M13
P71
P72
P73
P74
-
DS060 (v1.5) March 2, 2000
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS10/XL
Pad Name
I/O (D7 ††)
I/O, PGCK3 †,
GCK5 ††
I/O
I/O
I/O (D6 ††)
I/O
GND
I/O
I/O
I/O (D5 ††)
I/O
I/O
I/O
I/O (D4 ††)
I/O
VCC
GND
I/O (D3 ††)
I/O
I/O
I/O
I/O (D2 ††)
I/O
I/O
I/O
GND
I/O (D1 ††)
I/O
I/O
I/O
I/O (D0 ††, DIN)
I/O, SGCK4 †,
GCK6 †† (DOUT)
CCLK
VCC
O, TDO
GND
I/O
PC84
VQ100
CS144††
TQ144
Bndry
Scan
P56
P57
P53
P54
L12
L13
P75
P76
259 ‡
262 ‡
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
K10
K11
K12
K13
J10
J11
J12
J13
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
F10
E13
E12
E11
E10
D13
D12
D11
C13
C12
C11
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
P106
265 ‡
268 ‡
271 ‡
274 ‡
277 ‡
280 ‡
283 ‡
286 ‡
289 ‡
292 ‡
295 ‡
298 ‡
301 ‡
304 ‡
307 ‡
310 ‡
313 ‡
316 ‡
319 ‡
322 ‡
325 ‡
328 ‡
331 ‡
334 ‡
337 ‡
340 ‡
P73
P74
P75
P76
P77
P74
P75
P76
P77
P78
B13
B12
A13
A12
B11
P107
P108
P109
P110
P111
0
2
XCS10/XL
Pad Name
I/O, PGCK4 †,
GCK7 ††
I/O
I/O
I/O (CS1 ††)
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
2/8/00
PC84
VQ100
CS144††
TQ144
Bndry
Scan
P78
P79
A11
P112
5
P79
P80
P81
P82
P83
P84
P1
P80
P81
P82
P83
P84
P85
P86
P87
P88
D10
C10
B10
A10
C9
B9
A9
D8
C8
B8
A8
B7
A7
C7
P113
P114
P115
P116
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
8
11
14
17
20
23
26
29
32
35
38
41
-
† = 5V Spartan only
†† = 3V Spartan-XL only
‡ The “PWRDWN” on the XCS10XL is not part of the Boundary
Scan chain. For the XCS10XL, subtract 1 from all Boundary Scan
numbers from GCK3 on (175 and higher).
Additional XCS10/XL Package Pins
TQ144
P117
-
Not Connected Pins
-
-
-
-
Not Connected Pins
-
-
-
5/5/97
CS144
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20 & XCS20XL Device Pinouts
XCS20/XL
Pad Name
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC ††
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK1 †,
GCK8 ††
VCC
GND
I/O, PGCK1 †,
GCK1 ††
I/O
I/O
I/O
I/O, TDI
I/O, TCK
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O, TMS
I/O
VCC ††
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC ††
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VQ100
CS144 ††
TQ144
PQ208
Bndry
Scan
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
D7
A6
B6
C6
D6
A5
B5
C5
D5
A4
B4
C4
A3
B3
C3
A2
P128
P129
P130
P131
D6P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P204
P205
P206
P207
62
65
68
71
74
77
80
83
86
89
92
95
98
101
104
107
110
113
116
119
P100
P1
P2
B2
A1
B1
P144
P1
P2
P208
P1
P2
122
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
G2
G1
G3
G4
H1
H2
H3
H4
J1
J2
J3
J4
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P3
P4
P5
P6
P7
P8
P9
P10
P11
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P40
P41
P42
P43
P44
125
128
131
134
137
140
143
146
149
152
155
158
161
164
167
170
173
176
179
182
185
188
191
194
197
200
203
206
209
212
215
218
221
224
4-58
Powered by ICminer.com Electronic-Library Service CopyRight 2003
XCS20/XL
Pad Name
I/O
I/O
I/O
I/O
I/O, SGCK2 †,
GCK2 ††
Not Connected †,
M1 ††
GND
MODE †, M0 ††
VCC
Not Connected †,
PWRDWN ††
I/O, PGCK2 †,
GCK3 ††
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC ††
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC ††
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK3 †,
GCK4 ††
GND
DONE
VCC
PROGRAM
I/O (D7 ††)
I/O, PGCK3 †,
GCK5 ††
VQ100
CS144††
TQ144
PQ208
Bndry
Scan
P19
P20
P21
K1
K2
K3
L1
L2
P29
P30
P31
P32
P33
P45
P46
P47
P48
P49
227
230
233
236
239
P22
L3
P34
P50
242
P23
P24
P25
P26
M1
M2
N1
N2
P35
P36
P37
P38
P51
P52
P53
P54
245
246 †
P27
M3
P39
P55
247 ‡
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
N3
K4
L4
M4
N4
K5
L5
M5
N5
K6
L6
M6
N6
M7
N7
L7
K7
N8
M8
L8
K8
N9
M9
L9
K9
N10
M10
L10
N11
M11
L11
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P56
P57
P58
P59
P60
P61
P62
P63
P64
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
250 ‡
253 ‡
256 ‡
259 ‡
262 ‡
265 ‡
268 ‡
271 ‡
274 ‡
277 ‡
280 ‡
283 ‡
286 ‡
289 ‡
292 ‡
295 ‡
298 ‡
301 ‡
304 ‡
307 ‡
310 ‡
313 ‡
316 ‡
319 ‡
322 ‡
325 ‡
328 ‡
331 ‡
334 ‡
337 ‡
340 ‡
343 ‡
346 ‡
349 ‡
352 ‡
355 ‡
358 ‡
361 ‡
364 ‡
P49
P50
P51
P52
P53
P54
N12
M12
N13
M13
L12
L13
P71
P72
P73
P74
P75
P76
P103
P104
P105
P106
P107
P108
367 ‡
370 ‡
DS060 (v1.5) March 2, 2000
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20/XL
Pad Name
I/O
I/O
I/O (D6 ††)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC ††
I/O (D5 ††)
I/O
I/O
I/O
I/O
I/O
I/O (D4 ††)
I/O
VCC
GND
I/O (D3 ††)
I/O
I/O
I/O
I/O
I/O
I/O (D2 ††)
I/O
VCC ††
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (D1 ††)
I/O
I/O
I/O
I/O (D0 ††, DIN)
I/O, SGCK4 †,
GCK6 †† (DOUT)
VQ100
CS144 ††
TQ144
PQ208
Bndry
Scan
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
K10
K11
K12
K13
J10
J11
J12
J13
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
F10
E13
E12
E11
E10
D13
D12
D11
C13
C12
C11
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
P106
P109
P110
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
373 ‡
376 ‡
379 ‡
382 ‡
385 ‡
388 ‡
391 ‡
394 ‡
397 ‡
400 ‡
403 ‡
406 ‡
409 ‡
412 ‡
415 ‡
418 ‡
421 ‡
424 ‡
427 ‡
430 ‡
433 ‡
436 ‡
439 ‡
442 ‡
445 ‡
448 ‡
451 ‡
454 ‡
457 ‡
460 ‡
463 ‡
466 ‡
469 ‡
472 ‡
475 ‡
478 ‡
481 ‡
484 ‡
CS280††
Bndry
Scan
XCS20/XL
Pad Name
CCLK
VCC
O, TDO
GND
I/O
I/O, PGCK4 †,
GCK7 ††
I/O
I/O
I/O (CS1 ††)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC ††
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
2/8/00
VQ100
CS144††
TQ144
PQ208
Bndry
Scan
P74
P75
P76
P77
P78
P79
B13
B12
A13
A12
B11
A11
P107
P108
P109
P110
P111
P112
P155
P156
P157
P158
P159
P160
0
2
5
P80
P81
P82
P83
P84
P85
P86
P87
P88
D10
C10
B10
A10
D9
C9
B9
A9
D8
C8
B8
A8
B7
A7
C7
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P161
P162
P163
P164
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
-
Additional XCS20/XL Package Pins
PQ208
P12
P86 †
P165
P18 †
P92
P173 †
Not Connected Pins
P33 †
P39
P111
P121 †
P192 †
P202
P65
P140 †
P203
P71 †
P144
-
9/16/98
† = 5V Spartan only
†† = 3V Spartan-XL only
‡ The “PWRDWN” on the XCS20XL is not part of the Boundary
Scan chain. For the XCS20XL, subtract 1 from all Boundary Scan
numbers from GCK3 on (247 and higher).
XCS30 & XCS30XL Device Pinouts
XCS30/XL
Pad Name
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VQ100 TQ144 PQ208 PQ240 BG256
P89
P90
P91
P92
P93
P94
P95
-
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
-
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P212
P213
P214
P215
P216
P217
P218
P220
P221
P222
P223
P224
P225
P226
P227
P228
P229
P230
VCC*
C10
D10
A9
B9
C9
D9
A8
B8
VCC*
A6
C7
B6
A5
GND*
C6
B5
A4
VCC*
D10
E10
A9
B9
C9
D9
A8
B8
VCC*
B7
C7
D7
A6
GND*
B6
C6
D6
74
77
80
83
86
89
92
95
98
101
104
107
110
113
116
DS060 (v1.5) March 2, 2000
Powered by ICminer.com Electronic-Library Service CopyRight 2003
XCS30/XL
Pad Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK1 †,
GCK8 ††
VCC
GND
I/O, PGCK1 †,
GCK1 ††
I/O
I/O
I/O
I/O, TDI
CS280††
Bndry
Scan
P96
P97
P98
P99
P138
P139
P140
P141
P142
P143
P199
P200
P201
P202
P203
P204
P205
P206
P207
P231
P232
P233
P234
P235
P236
P237
P238
P239
C5
B4
A3
D5
C4
B3
B2
A2
C3
E6
A5
C5
B4
C4
A3
A2
B3
B2
119
122
125
128
131
134
137
140
143
P100
P1
P2
P144
P1
P2
P208
P1
P2
P240
P1
P2
VCC*
GND*
B1
VCC*
GND*
C3
146
P3
P4
P3
P4
P5
P6
P3
P4
P5
P6
P3
P4
P5
P6
C2
D2
D3
E4
C2
B1
C1
D4
149
152
155
158
VQ100 TQ144 PQ208 PQ240 BG256
4-59
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS30/XL
VQ100 TQ144 PQ208 PQ240 BG256
Pad Name
I/O, TCK
P5
P7
P7
P7
C1
I/O
P8
P8
D1
I/O
P9
P9
E3
I/O
P10
P10
E2
I/O
P11
P11
E1
I/O
P12
P12
F3
I/O
P13
F2
GND
P8
P13
P14
GND*
I/O
P9
P14
P15
G3
I/O
P10
P15
P16
G2
I/O, TMS
P6
P11
P16
P17
G1
I/O
P7
P12
P17
P18
H3
VCC
P18
P19
VCC*
I/O
P20
H2
I/O
P21
H1
I/O
P19
P23
J2
I/O
P20
P24
J1
I/O
P13
P21
P25
K2
I/O
P8
P14
P22
P26
K3
I/O
P9
P15
P23
P27
K1
I/O
P10
P16
P24
P28
L1
GND
P11
P17
P25
P29
GND*
VCC
P12
P18
P26
P30
VCC*
I/O
P13
P19
P27
P31
L2
I/O
P14
P20
P28
P32
L3
I/O
P15
P21
P29
P33
L4
I/O
P22
P30
P34
M1
I/O
P31
P35
M2
I/O
P32
P36
M3
I/O
P38
N1
I/O
P39
N2
VCC
P33
P40
VCC*
I/O
P16
P23
P34
P41
P1
I/O
P17
P24
P35
P42
P2
I/O
P25
P36
P43
R1
I/O
P26
P37
P44
P3
GND
P27
P38
P45
GND*
I/O
P46
T1
I/O
P39
P47
R3
I/O
P40
P48
T2
I/O
P41
P49
U1
I/O
P42
P50
T3
I/O
P43
P51
U2
I/O
P18
P28
P44
P52
V1
I/O
P19
P29
P45
P53
T4
I/O
P30
P46
P54
U3
I/O
P31
P47
P55
V2
I/O
P20
P32
P48
P56
W1
I/O, SGCK2 †,
P21
P33
P49
P57
V3
GCK2 ††
Not Connected
P22
P34
P50
P58
W2
†, M1 ††
GND
P23
P35
P51
P59
GND*
MODE †, M0 †† P24
P36
P52
P60
Y1
VCC
P25
P37
P53
P61
VCC*
P26
P38
P54
P62
W3
Not Connected
†,
PWRDWN ††
I/O, PGCK2 †,
P27
P39
P55
P63
Y2
GCK3 ††
I/O (HDC)
P28
P40
P56
P64
W4
I/O
P41
P57
P65
V4
I/O
P42
P58
P66
U5
I/O
P29
P43
P59
P67
Y3
I/O (LDC)
P30
P44
P60
P68
Y4
I/O
P61
P69
V5
I/O
P62
P70
W5
I/O
P63
P71
Y5
I/O
P64
P72
V6
I/O
P65
P73
W6
CS280††
Bndry
Scan
D3
E2
E4
E1
F5
F3
F2
GND*
F4
F1
G3
G2
VCC*
G4
H1
H4
J1
J2
J3
J4
K1
GND*
VCC*
K3
K4
K5
L1
L2
L3
M2
M3
VCC*
N1
N2
N3
N4
GND*
P1
P2
P3
P4
P5
R1
T1
T2
T3
U1
V1
U2
161
164
167
170
173
176
179
182
185
188
191
194
197
200
203
206
209
212
215
218
221
224
227
230
233
236
239
242
245
248
251
254
257
260
263
266
269
272
275
278
281
284
287
V2
290
GND*
W1
VCC*
V3
293
294 †
W2
295 ‡
W3
T4
U4
V4
W4
T5
W5
R6
U6
V6
298 ‡
301 ‡
304 ‡
307 ‡
310 ‡
313 ‡
316 ‡
319 ‡
322 ‡
325 ‡
4-60
Powered by ICminer.com Electronic-Library Service CopyRight 2003
XCS30/XL
Pad Name
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK3 †,
GCK4 ††
GND
DONE
VCC
PROGRAM
I/O (D7 ††)
I/O, PGCK3 †,
GCK5 ††
I/O
I/O
I/O
I/O
I/O (D6 ††)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5 ††)
I/O
I/O
VQ100 TQ144 PQ208 PQ240 BG256
CS280††
Bndry
Scan
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P74
P75
P76
P77
P78
P79
P80
P81
P82
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P99
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
Y6
GND*
W7
Y7
V8
W8
VCC*
Y8
U9
Y9
W10
V10
Y10
Y11
W11
VCC*
GND*
V11
U11
Y12
W12
V12
U12
V13
Y14
VCC*
Y15
V14
W15
Y16
GND*
V15
W16
Y17
V16
W17
Y18
U16
V17
W18
Y19
V18
W19
T6
GND*
W6
U7
V7
W7
VCC*
W8
U8
W9
V9
U9
T9
W10
V10
VCC*
GND*
T10
R10
W11
V11
U11
T11
U12
T12
VCC*
V13
U13
T13
W14
GND*
V14
U14
T14
R14
W15
U15
V16
U16
W17
W18
V17
V18
328 ‡
331 ‡
334 ‡
337 ‡
340 ‡
343 ‡
346 ‡
349 ‡
352 ‡
355 ‡
358 ‡
361 ‡
364 ‡
367 ‡
370 ‡
373 ‡
376 ‡
379 ‡
382 ‡
385 ‡
388 ‡
391 ‡
394 ‡
397 ‡
400 ‡
403 ‡
406 ‡
409 ‡
412 ‡
415 ‡
418 ‡
421 ‡
424 ‡
427 ‡
430 ‡
433 ‡
436 ‡
P49
P50
P51
P52
P53
P54
P71
P72
P73
P74
P75
P76
P103
P104
P105
P106
P107
P108
P119
P120
P121
P122
P123
P124
GND*
Y20
VCC*
V19
U19
U18
GND*
W19
VCC*
U18
V19
U19
439 ‡
442 ‡
P55
P56
P57
P58
-
P77
P78
P79
P80
P81
P82
P83
P84
P85
-
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P144
T17
V20
U20
T18
T19
T20
R18
R19
R20
P18
GND*
P20
N18
N19
N20
VCC*
M17
M18
M20
T16
T17
T18
T19
R16
R19
P15
P17
P18
P16
GND*
P19
N17
N18
N19
VCC*
M19
M17
L19
445 ‡
448 ‡
451 ‡
454 ‡
457 ‡
460 ‡
463 ‡
466 ‡
469 ‡
472 ‡
475 ‡
478 ‡
481 ‡
484 ‡
487 ‡
490 ‡
493 ‡
DS060 (v1.5) March 2, 2000
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS30/XL
VQ100 TQ144 PQ208 PQ240 BG256
Pad Name
I/O
P125
P145
L19
I/O
P59
P86
P126
P146
L18
I/O
P60
P87
P127
P147
L20
I/O (D4 ††)
P61
P88
P128
P148
K20
I/O
P62
P89
P129
P149
K19
VCC
P63
P90
P130
P150 VCC*
GND
P64
P91
P131
P151 GND*
I/O (D3 ††)
P65
P92
P132
P152
K18
I/O
P66
P93
P133
P153
K17
I/O
P67
P94
P134
P154
J20
I/O
P95
P135
P155
J19
I/O
P136
P156
J18
I/O
P137
P157
J17
I/O (D2 ††)
P68
P96
P138
P159
H19
I/O
P69
P97
P139
P160
H18
VCC
P140
P161 VCC*
I/O
P98
P141
P162
G19
I/O
P99
P142
P163
F20
I/O
P164
G18
I/O
P165
F19
GND
P100
P143
P166 GND*
I/O
P167
F18
I/O
P144
P168
E19
I/O
P145
P169
D20
I/O
P146
P170
E18
I/O
P147
P171
D19
I/O
P148
P172
C20
I/O (D1 ††)
P70
P101
P149
P173
E17
I/O
P71
P102
P150
P174
D18
I/O
P103
P151
P175
C19
I/O
P104
P152
P176
B20
I/O (D0 ††, DIN) P72
P105
P153
P177
C18
I/O, SGCK4 †,
P73
P106
P154
P178
B19
GCK6 ††
(DOUT)
CCLK
P74
P107
P155
P179
A20
VCC
P75
P108
P156
P180 VCC*
O, TDO
P76
P109
P157
P181
A19
GND
P77
P110
P158
P182 GND*
I/O
P78
P111
P159
P183
B18
I/O, PGCK4 †,
P79
P112
P160
P184
B17
GCK7 ††
I/O
P113
P161
P185
C17
I/O
P114
P162
P186
D16
I/O (CS1) ††
P80
P115
P163
P187
A18
I/O
P81
P116
P164
P188
A17
I/O
P165
P189
C16
I/O
P190
B16
I/O
P117
P166
P191
A16
I/O
P167
P192
C15
I/O
P168
P193
B15
I/O
P169
P194
A15
GND
P118
P170
P196 GND*
I/O
P119
P171
P197
B14
I/O
P120
P172
P198
A14
I/O
P199
C13
I/O
P200
B13
VCC
P173
P201 VCC*
I/O
P82
P121
P174
P202
C12
I/O
P83
P122
P175
P203
B12
I/O
P176
P205
A12
I/O
P177
P206
B11
I/O
P84
P123
P178
P207
C11
I/O
P85
P124
P179
P208
A11
I/O
P86
P125
P180
P209
A10
I/O
P87
P126
P181
P210
B10
CS280††
Bndry
Scan
L18
L17
L16
K19
K18
VCC*
GND*
K16
K15
J19
J18
J17
J16
H17
H16
VCC*
G18
G17
G16
F19
GND*
F18
F17
F16
F15
E19
E17
E16
D19
C19
B19
C18
B18
496 ‡
499 ‡
502 ‡
505 ‡
508 ‡
511 ‡
514 ‡
517 ‡
520 ‡
523 ‡
526 ‡
529 ‡
532 ‡
535 ‡
538 ‡
541 ‡
544 ‡
547 ‡
550 ‡
553 ‡
556 ‡
559 ‡
562 ‡
565 ‡
568 ‡
571 ‡
574 ‡
577 ‡
580 ‡
A19
VCC*
B17
GND*
A18
A17
0
2
5
D16
C16
B16
A16
D15
A15
E14
C14
B14
D14
GND*
A14
C13
B13
A13
VCC*
B12
D12
A11
B11
C11
D11
A10
B10
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
DS060 (v1.5) March 2, 2000
Powered by ICminer.com Electronic-Library Service CopyRight 2003
XCS30/XL
Pad Name
GND
2/8/00
VQ100 TQ144 PQ208 PQ240 BG256
P88
P127
P182
P211
GND*
CS280††
Bndry
Scan
GND*
-
* Pads labeled GND* or VCC* are internally bonded to Ground or
VCC planes within the package.
† = 5V Spartan only
†† = 3V Spartan-XL only
‡ The “PWRDWN” on the XCS30XL is not part of the Boundary
Scan chain. For the XCS30XL, subtract 1 from all Boundary Scan
numbers from GCK3 on (295 and higher).
Additional XCS30/XL Package Pins
PQ240
P22
P204
P37
P219
P195
-
GND Pins
P83
P98
Not Connected Pins
-
P143
-
P158
-
-
-
D14
G4
P19
U10
-
D15
G17
R2
U14
-
D13
N4
W14
D17
N17
-
H20
W9
-
J3
W13
-
2/12/98
BG256
C14
E20
K4
R4
U15
D6
F1
L17
R17
V7
A1
G20
U4
B7
H4
U8
A7
J4
Y13
A13
M4
-
VCC Pins
D7
D11
F4
F17
P4
P17
U6
U7
W20
GND Pins
D4
D8
H17
N3
U13
U17
Not Connected Pins
C8
D12
M19
V9
-
6/4/97
CS280
VCC Pins
A1
A7
B5
B15
C10
D13
E3
E18
G1
G19
C17
K2
K17
M4
N16
R3
R18
T7
U3
U10
U17
V5
V15
W13
E12
GND Pins
E5
E7
E8
E9
E11
E13
G5
G15
H5
H15
J5
J15
L5
L15
M5
M15
N5
N15
R7
R8
R9
R11
R12
R13
-
-
-
-
-
Not Connected Pins
A4
A12
C8
C12
C15
D1
D2
D5
D8
D17
D18
E15
H2
H3
H18
H19
L4
M1
M16
M18
R2
R4
R5
R15
R17
T8
T15
U5
V8
V12
W12
W16
-
-
-
-
5/19/99
4-61
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS40 & XCS40XL Device Pinouts
XCS40/XL
Pad Name
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK1 †,
GCK8 ††
VCC
GND
I/O, PGCK1 †,
GCK1 ††
I/O
I/O
I/O
I/O, TDI
I/O, TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O, TMS
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PQ208
PQ240
BG256
CS280††
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P202
P203
P204
P205
P206
P207
P212
P213
P214
P215
P216
P217
P218
P220
P221
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
P238
P239
VCC*
C10
D10
A9
B9
C9
D9
A8
B8
C8
A7
VCC*
A6
C7
B6
A5
GND*
C6
B5
A4
C5
B4
A3
D5
C4
B3
B2
A2
C3
VCC*
D10
E10
A9
B9
C9
D9
A8
B8
C8
D8
VCC*
B7
C7
D7
A6
GND*
B6
C6
D6
E6
A5
C5
D5
A4
B4
C4
A3
A2
B3
B2
Bndry
Scan
86
89
92
95
98
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143
146
149
152
155
158
161
164
167
P208
P1
P2
P240
P1
P2
VCC*
GND*
B1
VCC*
GND*
C3
170
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P23
P24
P25
P26
P27
P28
P29
P30
P31
C2
D2
D3
E4
C1
D1
E3
E2
E1
F3
F2
GND*
G3
G2
G1
H3
VCC*
H2
H1
J4
J3
J2
J1
K2
K3
K1
L1
GND*
VCC*
L2
C2
B1
C1
D4
D3
D2
D1
E2
E4
E1
F5
F3
F2
GND*
F4
F1
G3
G2
VCC*
G4
H1
H3
H2
H4
J1
J2
J3
J4
K1
GND*
VCC*
K3
173
176
179
182
185
188
191
194
197
200
203
206
209
212
215
218
221
224
227
230
233
236
239
242
245
248
251
254
4-62
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XCS40/XL
Pad Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK2 †,
GCK2 ††
Not Connected
†, M1 ††
GND
MODE †, M0 ††
VCC
Not Connected
†,
PWRDWN ††
I/O, PGCK2 †,
GCK3 ††
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PQ208
PQ240
BG256
CS280††
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P32
P33
P34
P35
P36
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
L3
L4
M1
M2
M3
M4
N1
N2
VCC*
P1
P2
R1
P3
GND*
T1
R3
T2
U1
T3
U2
V1
T4
U3
V2
W1
V3
K4
K5
L1
L2
L3
L4
M1
M2
M3
VCC*
N1
N2
N3
N4
GND*
P1
P2
P3
P4
P5
R1
R2
R4
T1
T2
T3
U1
V1
U2
Bndry
Scan
257
260
263
266
269
272
275
278
281
284
287
290
293
296
299
302
305
308
311
314
317
320
323
326
329
332
335
P50
P58
W2
V2
338
P51
P52
P53
P54
P59
P60
P61
P62
GND*
Y1
VCC*
W3
GND*
W1
VCC*
V3
341
342†
P55
P63
Y2
W2
343 ‡
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P84
P85
P86
P87
P88
W4
V4
U5
Y3
Y4
V5
W5
Y5
V6
W6
Y6
GND*
W7
Y7
V8
W8
VCC*
Y8
U9
V9
W9
Y9
W10
V10
Y10
Y11
W3
T4
U4
V4
W4
R5
U5
T5
W5
R6
U6
V6
T6
GND*
W6
U7
V7
W7
VCC*
W8
U8
V8
T8
W9
V9
U9
T9
W10
346 ‡
349 ‡
352 ‡
355 ‡
358 ‡
361 ‡
364 ‡
367 ‡
370 ‡
373 ‡
376 ‡
379 ‡
382 ‡
385 ‡
388 ‡
391 ‡
394 ‡
397 ‡
400 ‡
403 ‡
406 ‡
409 ‡
412 ‡
415 ‡
418 ‡
421 ‡
DS060 (v1.5) March 2, 2000
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS40/XL
Pad Name
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK3 †,
GCK4 ††
GND
DONE
VCC
PROGRAM
I/O (D7 ††)
I/O, PGCK3 †,
GCK5 ††
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D6 ††)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5 ††)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D4 ††)
I/O
VCC
PQ208
PQ240
BG256
CS280††
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P89
P90
P91
P92
P93
P94
P95
P96
P97
P99
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
W11
VCC*
GND*
V11
U11
Y12
W12
V12
U12
Y13
W13
V13
Y14
VCC*
Y15
V14
W15
Y16
GND*
V15
W16
Y17
V16
W17
Y18
U16
V17
W18
Y19
V18
W19
V10
VCC*
GND*
T10
R10
W11
V11
U11
T11
W12
V12
U12
T12
VCC*
V13
U13
T13
W14
GND*
V14
U14
T14
R14
W15
U15
T15
W16
V16
U16
W17
W18
V17
V18
Bndry
Scan
424 ‡
427 ‡
430 ‡
433 ‡
436 ‡
439 ‡
442 ‡
445 ‡
448 ‡
451 ‡
454 ‡
457 ‡
460 ‡
463 ‡
466 ‡
469 ‡
472 ‡
475 ‡
478 ‡
481 ‡
484 ‡
487 ‡
490 ‡
493 ‡
496 ‡
499 ‡
502 ‡
505 ‡
508 ‡
P103
P104
P105
P106
P107
P108
P119
P120
P121
P122
P123
P124
GND*
Y20
VCC*
V19
U19
U18
GND*
W19
VCC*
U18
V19
U19
511 ‡
514 ‡
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P144
P145
P146
P147
P148
P149
P150
T17
V20
U20
T18
T19
T20
R18
R19
R20
P18
GND*
P20
N18
N19
N20
VCC*
M17
M18
M19
M20
L19
L18
L20
K20
K19
VCC*
T16
T17
T18
T19
R15
R17
R16
R19
P15
P17
P18
P16
GND*
P19
N17
N18
N19
VCC*
M19
M17
M18
M16
L19
L18
L17
L16
K19
K18
VCC*
517 ‡
520 ‡
523 ‡
526 ‡
529 ‡
523 ‡
535 ‡
538 ‡
541 ‡
544 ‡
547 ‡
550 ‡
553 ‡
556 ‡
559 ‡
562 ‡
565 ‡
568 ‡
571 ‡
574 ‡
577 ‡
580 ‡
583 ‡
586 ‡
589 ‡
592 ‡
-
DS060 (v1.5) March 2, 2000
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XCS40/XL
Pad Name
GND
I/O (D3 ††)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D2 ††)
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D1 ††)
I/O
I/O
I/O
I/O
I/O
I/O (D0 ††, DIN)
I/O, SGCK4 †,
GCK6 ††
(DOUT)
CCLK
VCC
O, TDO
GND
I/O
I/O, PGCK4 †,
GCK7 ††
I/O
I/O
I/O (CS1 ††)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
2/8/00
PQ208
PQ240
BG256
CS280††
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P151
P152
P153
P154
P155
P156
P157
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
GND*
K18
K17
J20
J19
J18
J17
H20
H19
H18
VCC*
G19
F20
G18
F19
GND*
F18
E19
D20
E18
D19
C20
E17
D18
C19
B20
C18
B19
GND*
K16
K15
J19
J18
J17
J16
H19
H18
H17
H16
VCC*
G18
G17
G16
F19
GND*
F18
F17
F16
F15
E19
E17
E16
D19
D18
D17
C19
B19
C18
B18
Bndry
Scan
595 ‡
598 ‡
601 ‡
604 ‡
607 ‡
610 ‡
613 ‡
616 ‡
619 ‡
622 ‡
625 ‡
628 ‡
631 ‡
634 ‡
637 ‡
640 ‡
643 ‡
646 ‡
649 ‡
652 ‡
655 ‡
658 ‡
661 ‡
664 ‡
667 ‡
670 ‡
673 ‡
676 ‡
P155
P156
P157
P158
P159
P160
P179
P180
P181
P182
P183
P184
A20
VCC*
A19
GND*
B18
B17
A19
VCC*
B17
GND*
A18
A17
0
2
5
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P196
P197
P198
P199
P200
P201
P202
P203
P205
P206
P207
P208
P209
P210
P211
C17
D16
A18
A17
C16
B16
A16
C15
B15
A15
GND*
B14
A14
C13
B13
VCC*
A13
D12
C12
B12
A12
B11
C11
A11
A10
B10
GND*
D16
C16
B16
A16
E15
C15
D15
A15
E14
C14
B14
D14
GND*
A14
C13
B13
A13
VCC*
A12
C12
B12
D12
A11
B11
C11
D11
A10
B10
GND*
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
74
77
80
83
-
4-63
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
* Pads labeled GND* or VCC* are internally bonded to Ground or
VCC planes within the package.
Additional XCS40/XL Package Pins
PQ240
† = 5V Spartan only
†† = 3V Spartan-XL only
‡ The “PWRDWN” on the XCS40XL is not part of the Boundary
Scan chain. For the XCS40XL, subtract 1 from all Boundary Scan
numbers from GCK3 on (343 and higher).
P22
P204
P37
P219
P195
-
GND Pins
P83
P98
Not Connected Pins
-
P143
-
P158
-
-
-
D14
G4
P19
U10
-
D15
G17
R2
U14
-
D13
N4
W14
D17
N17
-
C10
G19
R18
V15
C17
K2
T7
W13
E11
H15
M15
R11
-
E12
J5
N5
R12
-
2/12/98
BG256
C14
E20
K4
R4
U15
D6
F1
L17
R17
V7
A1
G20
U4
B7
H4
U8
VCC Pins
D7
D11
F4
F17
P4
P17
U6
U7
W20
GND Pins
D4
D8
H17
N3
U13
U17
6/17/97
CS280
A1
D13
K17
U3
A7
E3
M4
U10
E5
E13
J15
N15
R13
E7
G5
L5
R7
-
VCC Pins
B5
B15
E18
G1
N16
R3
U17
V5
GND Pins
E8
E9
G15
H5
L15
M5
R8
R9
-
5/19/99
4-64
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R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Product Availability
Table 19 shows the packages and speed grades for Spartan/XL devices. Table 20 shows the number of user I/Os available
for each device/package combination.
Table 19: Component Availability Chart for Spartan/XL FPGAs
PINS
TYPE
Device
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
CODE
-3
-4
-3
-4
-3
-4
-3
-4
-3
-4
-4
-5
-4
-5
-4
-5
-4
-5
-4
-5
84
Plastic
PLCC
PC84
C
C
C
C
C
C
C
C
100
Plastic
VQFP
VQ100
C, I
C
C, I
C
C
C
C
C
C, I
C
C, I
C
C
C
C
C
144
Chip
Scale
CS144
144
Plastic
TQFP
TQ144
C
C
C, I
C
C, I
C
C
C
C
C
C
C
C, I
C
C, I
C
208
Plastic
PQFP
PQ208
240
Plastic
PQFP
PQ240
256
Plastic
BGA
BG256
280
Chip
Scale
CS280
C, I
C
C, I
C
C, I
C
C
C
C
C
C
C
C
C
C, I
C
C, I
C
C, I
C
C
C
C
C
C
C
C
C
C
C
C
C
PQ240
BG256
CS280
160
169
169
192
192
192
205
160
169
169
192
192
192
205
5/19/99
C = Commercial TJ = 0 ° to +85°C
I = Industrial TJ = –40°C to +100°C
Table 20: User I/O Chart for Spartan/XL FPGAs
Device
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
Max
I/O
80
112
160
192
224
80
112
160
192
224
PC84
61
61
61
61
VQ100
77
77
77
77
77
77
77
77
CS144
Package Type
TQ144
PQ208
112
113
113
112
113
112
113
113
192
224
5/19/99
DS060 (v1.5) March 2, 2000
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4-65
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Ordering Information
Example:
XCS20XL-4 PQ208C
Device Type
Temperature Range
C = Commercial (TJ = 0 to +85oC)
I = Industrial (TJ = –40oC to +100oC)
Speed Grade
-3
-4
-5
Number of Pins
Package Type
BG = Ball Grid Array
VQ = Very Thin Quad Flat Pack
PC = Plastic Lead Chip Carrier
TQ = Thin Quad Flat Pack
PQ = Plastic Quad Flat Pack
CS = Chip Scale
Date
11/20/98
1/6/99
3/2/00
Version
1.3
1.4
1.5
Description
Added Spartan-XL specs and Power Down
All Spartan-XL -4 specs designated Preliminary with no changes
Added CS package, updated Spartan-XL specs to Final
4-66
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DS060 (v1.5) March 2, 2000