DP8303A 8-Bit TRI-STATEÉ Bidirectional Transceiver (Inverting) General Description Features This family of high speed Schottky 8-bit TRI-STATE bidirectional transceivers are designed to provide bidirectional drive for bus oriented microprocessor and digital communications systems. They are all capable of sinking 16 mA on the A ports and 48 mA on the B ports (bus ports). PNP inputs for low input current and an increased output high (VOH) level allow compatibility with MOS, CMOS, and other technologies that have a higher threshold and less drive capabilities. In addition, they all feature glitch-free power up/down on the B port preventing erroneous glitches on the system bus in power up or down. DP8303A and DP7304B/DP8304B are featured with Transmit/Receive (T/R) and Chip Disable (CD) inputs to simplify control logic. For greater design flexibility, DP8307A and DP7308/DP8308 are featured with Transmit (T) and Receive (R) control inputs. Y Y Y Y Y Y Y Y Y 8-bit directional data flow reduces system package count Bidirectional TRI-STATE inputs/outputs interface with bus oriented systems PNP inputs reduce input loading Output high voltage interfaces with TTL, MOS, and CMOS 48 mA/300 pF bus drive capability Pinouts simplify system interconnections Transmit/Receive and chip disable simplify control logic Compact 20-pin dual-in-line package Bus port glitch free power up/down Logic and Connection Diagrams Dual-In-Line Package TL/F/5856 – 1 TL/F/5856 – 2 Top View Order Number DP8303AN See NS Package Number N20A Logic Table Inputs Resulting Conditions Chip Disable Transmit/Receive A Port 0 0 OUT B Port IN 0 1 IN OUT 1 X TRI-STATE TRI-STATE X e Don’t care TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1996 National Semiconductor Corporation TL/F/5856 RRD-B30M36/Printed in U. S. A. http://www.national.com DP8303A 8-Bit TRI-STATE Bidirectional Transceiver (Inverting) February 1996 Absolute Maximum Ratings (Note 1) Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Output Voltage Maximum Power Dissipation* at 25§ C Cavity Package Molded Package b 65§ C to a 150§ C Lead Temperature (soldering, 4 seconds) 260§ C Recommended Operating Conditions 7V 5.5V 5.5V Supply Voltage (VCC) DP8303A Temperature (TA) DP8303A 1667 mW 1832 mW *Derate cavity package 11.1 mW/§ C above 25§ C; derate molded package 14.7 mW/§ C. Min Max Units 4.75 5.25 V 0 70 §C DC Electrical Characteristics (Notes 2 and 3) Symbol Parameter Conditions Min Typ Max Units 0.7 V A PORT (A0 – A7) VIH Logical ‘‘1’’ Input Voltage VIL Logical ‘‘0’’ Input Voltage VOH Logical ‘‘1’’ Output Voltage VOL Logical ‘‘0’’ Output Voltage CD e VIL, T/R e 2.0V CD e VIL, T/R e 2.0V 2.0 V CD e T/R e VIL VIL e 0.5V IOH e b0.4 mA CD e T/R e VIL VIL e 0.5V IOL e 16 mA 0.35 0.5 V IOL e 8 mA 0.3 0.4 V b 38 b 75 mA 0.1 80 mA 1 mA mA IOH e b3 mA VCC b 1.15 VCC b 0.7 2.7 3.95 V V IOS Output Short Circuit Current CD e VIL, T/R e VIL, VO e 0V, VCC e Max, (Note 4) IIH Logical ‘‘1’’ Input Current CD e VIL, T/R e 2.0V, VIH e 2.7V II Input Current at Maximum Input Voltage CD e 2.0V, VCC e Max, VIH e 5.25V IIL Logical ‘‘0’’ Input Current CD e VIL, T/R e 2.0V, VIN e 0.4V b 70 b 200 VCLAMP Input Clamp Voltage CD e 2.0V, IIN e b12 mA b 0.7 b 1.5 V IOD Output/Input TRI-STATE Current CD e 2.0V VIN e 0.4V b 200 mA VIN e 4.0V 80 mA 0.7 V b 10 B PORT (B0 – B7) VIH Logical ‘‘1’’ Input Voltage CD e VIL, T/R e VIL VIL Logical ‘‘0’’ Input Voltage CD e VIL, T/R e VIL VOH Logical ‘‘1’’ Output Voltage CD e VIL, T/R e 2.0V VIL e 0.5V VOL Logical ‘‘0’’ Output Voltage 2.0 CD e VIL, T/R e 2.0V V IOH e b0.4 mA VCC b 1.15 VCC b0.8 V IOH e b5 mA IOH e b10 mA 2.7 3.9 V 2.4 3.6 V IOL e 20 mA 0.3 0.4 V IOL e 48 mA 0.4 0.5 V b 50 b 150 mA 0.1 80 mA 1 mA mA IOS Output Short Circuit Current CD e VIL, T/R e 2.0V, VO e 0V, VCC e Max, (Note 4) IIH Logical ‘‘1’’ Input Current CD e VIL, T/R e VIL, VIH e 2.7V II Input Current at Maximum Input Voltage CD e 2.0V, VCC e Max, VIH e 5.25V IIL Logical ‘‘0’’ Input Current CD e VIL, T/R e VIL, VIN e 0.4V b 70 b 200 VCLAMP Input Clamp Voltage CD e 2.0V, IIN e b12 mA b 0.7 b 1.5 V IOD Output/Input TRI-STATE Current CD e 2.0V VIN e 0.4V b 200 mA VIN e 0.4V a 200 mA http://www.national.com 2 b 25 DC Electrical Characteristics (Notes 2 and 3) (Continued) Symbol Parameter Conditions Min Typ Max Units 0.7 V CONTROL INPUTS CD, T/R VIH Logical ‘‘1’’ Input Voltage VIL Logical ‘‘0’’ Input Voltage IIH Logical ‘‘1’’ Input Current VIH e 2.7V II Maximum Input Current VCC e Max, VIH e 5.25V IIL Logical ‘‘0’’ Input Current VIL e 0.4V VCLAMP Input Clamp Voltage 2.0 V 0.5 20 mA 1.0 mA T/R b 0.1 b 0.25 mA CD b 0.25 b 0.5 mA b 0.8 b 1.5 V CD e 2.0V, VIN, VCC e Max 70 100 mA CD e 0.4V, VINA e T/R e 2V, VCC e Max 100 150 mA IIN e b12 mA POWER SUPPLY CURRENT ICC Power Supply Current AC Electrical Characteristics VCC e 5V, TA e 25§ C Symbol Parameter Conditions Min Typ Max Units A PORT DATA/MODE SPECIFICATIONS tPDHLA Propagation Delay to a Logical ‘‘0’’ from B Port to A Port CD e 0.4V, T/R e 0.4V (Figure A) R1 e 1k, R2 e 5k, C1 e 30 pF 8 12 ns tPDLHA Propagation Delay to a Logical ‘‘1’’ from B Port to A Port CD e 0.4V, T/R e 0.4V (Figure A) R1 e 1k, R2 e 5k, C1 e 30 pF 11 16 ns tPLZA Propagation Delay from a Logical ‘‘0’’ to TRI-STATE from CD to A Port B0 to B7 e 2.4V, T/R e 0.4V (Figure C) S3 e 1, R5 e 1k, C4 e 15 pF 10 15 ns tPHZA Propagation Delay from a Logical ‘‘1’’ to TRI-STATE from CD to A Port B0 to B7 e 0.4V, T/R e 0.4V (Figure C) S3 e 0, R5 e 1k, C4 e 15 pF 8 15 ns tPZLA Propagation Delay from TRI-STATE to a Logical ‘‘0’’ from CD to A Port B0 to B7 e 2.4V, T/R e 0.4V (Figure C) S3 e 1, R5 e 1k, C4 e 30 pF 20 30 ns tPZHA Propagation Delay from TRI-STATE to a Logical ‘‘1’’ from CD to A Port B0 to B7 e 0.4V, T/R e 0.4V (Figure C) S3 e 0, R5 e 5k, C4 e 30 pF 19 30 ns B PORT DATA/MODE SPECIFICATIONS tPDHLB Propagation Delay to a Logical ‘‘0’’ from A Port to B Port CD e 0.4V, T/R e 2.4V (Figure A) R1 e 100X, R2 e 1k, C1 e 300 pF R1 e 667X, R2 e 5k, C1 e 45 pF 12 7 18 12 ns ns tPDLHB Propagation Delay to a Logical ‘‘1’’ from A Port to B Port CD e 0.4V, T/R e 2.4V (Figure A) R1 e 100X, R2 e 1k, C1 e 300 pF R1 e 667X, R2 e 5k, C1 e 45 pF 15 9 20 14 ns ns tPLZB Propagation Delay from a Logical ‘‘0’’ to TRI-STATE from CD to B Port A0 to A7 e 2.4V, T/R e 2.4V (Figure C) S3 e 1, R5 e 1k, C4 e 15 pF 13 18 ns tPHZB Propagation Delay from a Logical ‘‘1’’ to TRI-STATE from CD to B Port A0 to A7 e 0.4V, T/R e 2.4V (Figure C) S3 e 0, R5 e 1k, C4 e 15 pF 8 15 ns tPLZB Propagation Delay from TRI-STATE to a Logical ‘‘0’’ from CD to B Port A0 to A7 e 2.4V, T/R e 2.4V (Figure C) S3 e 1, R5 e 100X, C4 e 300 pF S3 e 1, R5 e 667X, C4 e 45 pF 25 16 35 25 ns ns tPZHB Propagation Delay from TRI-STATE to a Logical ‘‘1’’ from CD to B Port A0 to A7 e 0.4V, T/R e 2.4V (Figure C) S3 e 0, R5 e 1k, C4 e 300 pF S3 e 0, R5 e 5kX, C4 e 45 pF 22 14 35 25 ns ns 3 http://www.national.com AC Electrical Characteristics VCC e 5V, TA e 25§ C (Continued) Symbol Parameter Conditions Min Typ Max Units TRANSMIT/RECEIVE MODE SPECIFICATIONS tTRL tTRH tRTL tRTH Propagation Delay from Transmit Mode to Receive a Logical ‘‘0’’, T/R to A Port CD e 0.4V (Figure B) S1 e 1, R4 e 100X, C3 e 5 pF S2 e 1, R3 e 1k, C2 e 30 pF 23 35 ns Propagation Delay from Transmit Mode to Receive a Logical ‘‘1’’, T/R to A Port CD e 0.4V (Figure B) S1 e 0, R4 e 100X, C3 e 5 pF S2 e 0, R3 e 5k, C2 e 30 pF 23 35 ns Propagation Delay from Receive Mode to Transmit a Logical ‘‘0’’, T/R to B Port CD e 0.4V (Figure B) S1 e 1, R4 e 100X, C3 e 300 pF S2 e 1, R3 e 300X, C2 e 5 pF 23 35 ns Propagation Delay from Receive Mode to Transmit a Logical ‘‘1’’, T/R to B Port CD e 0.4V (Figure B ) S1 e 0, R4 e 1k, C3 e 300 pF S2 e 0, R3 e 300X, C2 e 5 pF 27 35 ns Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: Unless otherwise specified, min/max limits apply across the supply and temperature range listed in the table of Recommended Operating Conditions. All typical values given are for VCC e 5V and TA e 25§ C. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 4: Only one output at a time should be shorted. Switching Time Waveforms and AC Test Circuits TL/F/5856 – 3 TL/F/5856 – 4 Note: C1 includes test fixture capacitance. FIGURE A. Propagation Delay from A Port to B Port or from B Port to A Port http://www.national.com 4 Switching Time Waveforms and AC Test Circuits (Continued) TL/F/5856 – 5 TL/F/5856 – 6 Note: C2 ad C3 include test fixture capacitance. FIGURE B. Propagation Delay from T/R to A Port or B Port TL/F/5856 – 7 TL/F/5856 – 8 Note: C4 includes test fixture capacitance. Port input is in a fixed logical condition. See AC table. FIGURE C. Propagation Delay to/from TRI-STATE from CD to A Port or B Port 5 http://www.national.com DP8303A 8-Bit TRI-STATE Bidirectional Transceiver (Inverting) Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number DP8303AN NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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