DACs for Electronic Adjustment High-precision 10bit 8ch/10ch D/A Converters BU2506FV,BU2505FV No.11052EBT03 ●Description BU2506FV and BU2505FV ICs are high performance 10bit R-2R type DACs with 8ch and 10ch outputs, respectively. Cascade connection is possible, ensuring suitability with multi-channel applications. Each channel incorporates a full swing output-type buffer amplifier with high speed output response characteristics, resulting in a greatly shortened wait time. The ICs also utilize the TTL level input method, and with the RESET pin the output voltage can be kept in the lower reference voltage range. ●Features 1) High performance, multi-channel R-2R-type 10bit D/A converter built-in (BU2506FV: 8 channels, BU2505FV: 10 channels) 2) Full swing output type buffer amplifier incorporated at each output channel 3) The RESET terminal can keep the output voltage at all channels within the lower reference voltage range 4) Digital input compatible with TTL levels 5) 14bit 3-line serial data + RESET signal input (address 4bit + data 10bit) 6) Cascade connection available 7) LSB first / MSB first of 10bit data can be changed by the REVERSE terminal 8) Compact package: 0.65mm pitch, 20 pins (SSOP-B20) ●Applications DVDs, CD-Rs, CD-RWs, Digital cameras ●Lineup Parameter BU2505FV BU2506FV 4.5 to 5.5V 4.5 to 5.5V 10ch 8ch Differential non linearity error ±1.0LSB ±1.0LSB Integral non linearity error ±3.5LSB ±3.5LSB 10MHz 10MHz SSOP-B20 SSOP-B20 Power source voltage range Number of channels Data transfer frequency Package ●Absolute Maximum Ratings(Ta=25℃) Parameter Symbol Ratings Unit Power source voltage VCC -0.3 to 6.0 V D/A converter upper standard voltage VDD -0.3 to 6.0 V Input voltage Output voltage Storage temperature range Power dissipation VIN -0.3 to 6.0 V VOUT -0.3 to 6.0 V Tstg -55 to 125 ℃ * Pd 400 mW * Derated at 4mW/℃ at Ta>25℃, mounted on a 70x70x1.6mm FR4 glass epoxy board (copper foil area less than 3%) Note: These products are not robust against radiation ●Recommended Operating Conditions(Ta=25℃) Parameter Symbol Limits Unit Power supply voltage range VCC 4.5 to 5.5 V Operating temperature range Topr -30 to 85 ℃ www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 1/10 2011.04 - Rev.B Technical Note BU2506FV,BU2505FV ●Electrical Characteristics(Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃) Limits Parameter Symbol Unit MIN. TYP. MAX. Conditions <Digital unit> Power source current ICC - 0.85 2.8 mA At CLK=10MHz, IAO=0μA Input leak current IILK -5 - 5 μA VIN=0 to VCC Input voltage L VIL - - 0.8 V - Input voltage H VIH 2.0 - - V - Output voltage L VOL 0 - 0.4 V IOL=2.5mA Output voltage H VOH 4.6 - 5 V IOH=-2.5mA - 4.5 7.5 mA <Analog unit> Consumption current D/A converter upper standard voltage setting range D/A converter lower standard voltage setting range Buffer amplifier output voltage range Buffer amplifier output drive range Precision IrefH (*1) - 3.7 6.2 VrefH 3.0 - 5 V VrefL 0 - 1.5 V 0.1 - 4.9 0.2 - 4.75 VO IO -2 - 2 Differential non-linearity error DNL -1.0 - 1.0 Integral non-linearity error INL -3.5 - 3.5 mA V mA LSB Zero point error SZERO -25 - 25 Full scale error SFULL -25 - 25 Buffer amplifier output impedance RO - 5 15 Ω Pull-up I/O internal resistance value Rup 12.5 25 37.5 kΩ mV Data condition : at maximum current Outputs are not necessarily within the standard voltage setting range, but ARE within the buffer amplifier output voltage range (VO). IO=±100μA IO=±1.0mA Upper side saturation voltage =0.35V (on full scale setting, current sourcing) Lower side saturation voltage =0.23V (on zero scale setting, current sinking) VrefH =4.796V VrefL=0.7V VCC=5.5V (4mV/LSB) At no load (IO=+0mA ) Input voltage 0V (Resistance value changes according to voltage supplied) *1 Value in the case where CH1 ~ CH8 are set to maximum current after reset www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 2/10 2011.04 - Rev.B Technical Note BU2506FV,BU2505FV ●Timing Characteristics(Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃) Limits Conditions Parameter Symbol Unit MIN. TYP. MAX. Judgment level is 80% / 20% of VCC. Reset L pulse width tRTL 50 - - - Clock L pulse width tCKL 50 - - - Clock H pulse width tCKH 50 - - - Clock rise time tcr - - 50 - Clock fall time tcf - - 50 - Data setup time tDCH 20 - - Data hold time tCHD 40 - - - Load setup time tCHL 50 - - - Load hold time tLDC 50 - - - Load H pulse width tLDH 50 - - - Data output delay time tDO - - 90 DA output settling time tLDD - 7 20 nS - CL=100pF CL≦100pF, VO: 0.5V⇔4.5V. Until output value deference from final value becomes 1/2LSB. μS RESET tRTL tcr tCKH tcf CLK tCKL tLDC DI tLDH LD tDCH tCHD tCHL tLDD DA OUTPUT tDo DO OUTPUT (note) LD signal is level triggered. When LD input is on H level, internal shift-register state is loaded to DAC control latch. Clock transition during LD=H is inhibited. www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 3/10 2011.04 - Rev.B Technical Note BU2506FV,BU2505FV ●Cascade Connection A data output terminal for cascade connection (DO) is available for reducing the number of parts when it is increased. The DO terminal can be connected to a data input terminal (DI) of the next IC. However, DO transition is synchronized with rising edge of clock signal, DO signal should be delayed, to keep a limit of data hold time. For example RC passive filter can be used. Also in some cases, an operation frequency of logic signal have to be decreased to ensure a margin of data setup time. DO LD CLK DI BU2505 FV BU2506 FV (#2) DO LD CLK LD CLK DI DI CPU BU2505 FV BU2506 FV (#1) Therefore, it is better to control LD port of each LSI separately, if extra CPU ports are available. In this case, more ports to control LD signals are needed, but a consideration described above doesn’t have do be done. LD1 LD CLK DI LD CLK BU2505FV BU2506FV (#1) DI BU2505FV BU2506FV (#2) LD2 DI CLK www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 4/10 2011.04 - Rev.B Technical Note BU2506FV,BU2505FV 10 VDD (VrefH) AO8 9 8 AO7 AO6 7 6 Reset D/A D/A 5 Reverse D/A L 8 L 7 L 6 ・・・ D13 D10 11 12 D9 8 7 6 2 DA converter lower standard voltage (VrefL) input terminal AO5 4 3 2 AO3 1 VSS (VrefL) Equivalent Circuit 6 Description - AO4 L D/A Buffer operation amplifier 10bit R-2R DA converter 10bit Latch Ch3 ・・・ 10bit Latch 4 1 L D/A Ch2 19 20 10bit R-2R DA converter AO2 GND AO1 I/O 18 5 L D/A D0 1 DI 17 4 3 2 AO3 1 VSS (VrefL) Buffer operation amplifier 10bit R-2R DA converter 4 10bit Latch Ch3 10bit Latch ・・・ Analog / Digital Analog AO4 D/A L L 1 Ch2 ●Terminal Descriptions Terminal No. Name 1 VSS AO5 5 L D/A D0 D/A 10bit R-2R DA converter 5 3 4 14bit Shift register 15 LD CLK 16 Reset 6 5 Reverse 1 DI 17 18 19 20 AO1 AO2 GND Address decoder VCC 11 12 TEST1 TEST2 13 14 DO 10 VDD (VrefH) AO8 9 8 7 AO7 D/A D/A AO6 D/A L 8 L L 6 ・・・ Address decoder D13 D10 11 12 D9 8 7 6 5 2 3 4 14bit Shift register LD 15 16 CLK 7 L D/A 9 L D/A 11 10 AO9 12 13 AO10 DO BU2506FV 14 VCC BU2505FV 2 AO3 Analog O 10bit D/A output(CH3) 4 3 AO4 Analog O 10bit D/A output(CH4) 4 4 AO5 Analog O 10bit D/A output(CH5) 4 5 Reverse Digital I The reverse LSB and MSB of data designation 10bit in 14bit. 2 6 Reset Digital I All ch analog output L fixed 2 7 AO6 Analog O 10bit D/A output(CH6) 4 8 AO7 Analog O 10bit D/A output(CH7) 4 9 AO8 Analog O 10bit D/A output(CH8) 4 10 VDD Analog - DA converter upper standard voltage (VrefH) input terminal 5 11 VCC - - Power source terminal - 12 AO9(TEST1) Analog O 10bit D/A output(CH9) (BU2506FV : test terminal) 4 13 AO10(TEST2) Analog O 10bit D/A output(CH10) (BU2506FV : test terminal) 4 14 DO Digital O This outputs bit data of LSB of 14bit shift register. 3 LD terminal. When High level is input, the value of 14bit shift register is loaded to decoder and D/A output register. Shift clock input terminal. At rise of shift clock, the signal from DI terminal is input to 14bit shift register. 15 LD Digital I 16 CLK Digital I 17 DI Digital I Serial data input terminal. Serial data whose data length is 14bit (address 4bit + data 10bit) is input. 1 18 AO1 Analog O 10bit D/A output(CH1) 4 19 AO2 Analog O 10bit D/A output(CH2) 4 20 GND - - GND terminal - 1 1 *In the case of BU2506FV, be sure to leave the TEST1 and TEST2 terminals open www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 5/10 2011.04 - Rev.B Technical Note BU2506FV,BU2505FV ●Command Transmission 1) Reverse = open (or VCC short-circuit) setting (1) Data format For D/A converter output setting For address selection (2) Data timing diagram ADDRESS LSB DI D0 ADDRESS MSB D1 D2 DATA LSB D3 DATA MSB D4 D11 D12 D13 CLK LD DACOUT D13 D12 D11 0 0 0 0 0 0 0 0 0 0 0 0 : : : 1 1 1 1 1 1 2) Reverse = L setting (1) Data format D10 0 0 0 0 : 1 1 D9 0 0 0 0 : 1 1 D8 0 0 0 0 : 1 1 For D/A converter output setting D7 0 0 0 0 : 1 1 D6 0 0 0 0 : 1 1 For address selection (2) Data timing diagram ADDRESS LSB DI D0 ADDRESS MSB D1 D2 DATA MSB D3 DATA LSB D13 D6 D5 D4 CLK LD DACOUT D4 0 1 0 1 : 0 1 D5 0 0 1 1 : 1 1 D6 0 0 0 0 : 1 1 D7 0 0 0 0 : 1 1 D8 0 0 0 0 : 1 1 D9 0 0 0 0 : 1 1 D10 0 0 0 0 : 1 1 D11 0 0 0 0 : 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 : 1 1 D4 0 1 0 1 : 0 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D12 0 0 0 0 : 1 1 D13 0 0 0 0 : 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Selection Inconsequential AO1 selection AO2 selection AO3 selection AO4 selection AO5 selection AO6 selection AO7 selection AO8 selection AO9 selection*1 AO10 selection*1 Inconsequential Inconsequential Inconsequential Inconsequential Inconsequential D/A output (VrefH=VDD, VrefL=VSS) VrefL (VrefH-VrefL)/1024×1+VrefL (VrefH-VrefL)/1024×2+VrefL (VrefH-VrefL)/1024×3+VrefL : (VrefH-VrefL)/1024×1022+VrefL (VrefH-VrefL)/1024×1023+VrefL D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address selection Inconsequential AO1 selection AO2 selection AO3 selection AO4 selection AO5 selection AO6 selection AO7 selection AO8 selection AO9 selection*1 AO10 selection*1 Inconsequential Inconsequential Inconsequential Inconsequential Inconsequential D/A output (VrefH=VDD, VrefL=VSS) VrefL (VrefH-VrefL)/1024×1+VrefL (VrefH-VrefL)/1024×2+VrefL (VrefH-VrefL)/1024×3+VrefL : (VrefH-VrefL)/1024×1022+VrefL (VrefH-VrefL)/1024×1023+VrefL *1 In the BU2506FV, this channel is for testing, therefore, do not designate. www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 6/10 2011.04 - Rev.B Technical Note BU2506FV,BU2505FV 6 6 5 5 5 4 4 4 3 2 1 0 VOUT [V] 6 VOUT [V] VOUT [V] ●Electrical Characteristics Curves 3 2 2 1 1 0 0 0 200 400 600 800 1000 1200 0 200 Input Code [decimal] 600 1000 0 1200 1 35 1 0.5 30 0.5 -0.5 DNL [LSB] 1.5 0 25 20 400 600 800 1000 1200 4 4.2 4.4 4.6 4.8 Input Code [decimal] 5 5.2 5.4 5.6 5.8 0 6 1 1 0.5 0.5 0.5 INL [LSB] 1 INL [LSB] 1.5 0 -0.5 -0.5 -1 -1 -1 -1.5 400 600 800 1000 1200 200 400 600 800 1000 1200 0 200 Input Code [decimal] 1000 1200 400 600 800 1000 1200 Input Code [decimal] Fig.8 Integral linearity error (25℃) Fig.9 Integral linearity error (85℃) 2.52 40 6 35 5 2.51 VOUT [V] 3 Ta=85℃ Ta=25℃ Ta=-30℃ 30 Rup [kΩ] code=1FFh 4 2.5 Ta=85℃ Ta=25℃ 25 20 2 800 -1.5 0 Input Code [decimal] Fig.7 Integral linearity error (-30℃) 600 0 -0.5 200 400 Fig.6 Differential linearity error (85℃) 1.5 0 200 Input Code [decimal] Fig.5 Differential linearity error (25℃) -1.5 1200 -0.5 1.5 0 1000 0 Vin [V] Fig.4 Differential linearity error (-30℃) 800 -1.5 10 200 600 -1 15 -1.5 400 Fig.3 Output voltage linearity (85℃) 40 0 200 Input Code [decimal] 1.5 -1 INL [LSB] 800 Fig.2 Output voltage linearity (25℃) Rup [kΩ] DNL [LSB] 400 Input Code [decimal] Fig.1 Output voltage linearity (-30℃) ICC [mA] 3 code=000h Ta=-30℃ 2.49 15 1 code=3FFh 0 -40 10 2.48 -2.5 10 60 -1.5 -0.5 0.5 1.5 2.5 IOUT [mA] 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 Vin [V] Temp. [ ℃ ] Fig.10 Circuit current temperature characteristic www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. Fig.11 Output load fluctuation characteristic (input code: 1FFh) 7/10 Fig.12 Pull-up built in resistance characteristic 2011.04 - Rev.B Technical Note BU2506FV,BU2505FV ●Equivalent Circuits *1 1 3 to inside 2 from inside 4 ・ 5 ・ 6 to inside 5 4 6 *1 25kΩ at Vcc = 5.0V (changes according to voltage supplied) ●Standard Example Application Circuit VrefH VCC VrefL AO1 CH1 AO2 CH2 AO3 CH3 AO10 CH10 Reverse Reset Controller www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. LD CLK DI GND 8/10 2011.04 - Rev.B Technical Note BU2506FV,BU2505FV ●Operation Notes (1) The electrical characteristic and data on graphs for this datasheet, are typically evaluated value, and not guaranteed. (2) We suppose that application circuits are recommendable, but please make sufficient check for characteristics with the actual application. In case that value of external component for this LSI is changed, please check characteristic, not only static but also transient. (3) About absolute maximum ratings If operation condition is over the absolute maximum ratings, supply voltage or other operation range, LSI will be broken. Please don't apply any voltage or temperature over the absolute maximum ratings. If application have possibilities of become over the absolute maximum ratings, please take safety measures by using fuse and so on. Not to over absolute maximum ratings of LSI. (4) GND voltage Please keep GND voltage lowest of any other terminal of this LSI. Please confirm that other terminal voltages are not lower than GND. (5) Thermal design Please making a thermal design that allows for a sufficient margin in light of the power dissipation in actual operating condition. (6) About terminals short and wrong mounting Please pay full attention to the LSI direction and displacement when mounting LSI on PCB. If you assemble them by mistake and electrify it, LSI might be destroyed. And it is happen to short among LSI terminals or terminals and power supply, by foreign substance. (7) About operation in strong electromagnetic field If you use it in strong electromagnetic field, please evaluate fully as there is a possibility of malfunction. (8) Place a bypass capacitor as close as possible between each power supply terminal and ground in order to prevent deterioration of the D/A conversion accuracy due to ripple and noise signals from power supply or GND. (9) A capacitor should be placed between the analog output and ground in order to eliminate noise. A capacitance up to 100pF is recommended (including the capacitance of the wire). (10) This IC is selectable to decode the 10bit DI data pattern using either LSB first or MSB first, depending on the conditions of the REVERSE terminal. Therefore the reverse terminal should be open or VDD voltage (LSB first) or GND voltage (MSB first) www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 9/10 2011.04 - Rev.B Technical Note BU2506FV,BU2505FV ●Ordering part number B U 2 Part No. 5 0 6 F Part No. 2506 2505 V - Package FV: SSOP-B20 E 2 Packaging and forming specification E2: Embossed tape and reel SSOP-B20 <Tape and Reel information> 6.5 ± 0.2 11 0.3Min. 4.4 ± 0.2 6.4 ± 0.3 20 1 Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 10 0.1± 0.1 1.15 ± 0.1 0.15 ± 0.1 0.1 0.65 0.22 ± 0.1 1pin Reel (Unit : mm) www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 10/10 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2011.04 - Rev.B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. 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