PRO-LINX ™ GS7025 Serial Digital Receiver PRELIMINARY DATA SHEET DESCRIPTION • SMPTE 259M-C compliant (270Mb/s) The GS7025 provides automatic cable equalization and high performance clock and data recovery for serial digital signals. The GS7025 receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at PECL levels (800mV). The onboard cable equalizer provides up to 35dB of gain at 135MHz which typically results in equalization of greater than 350m of high quality cable at 270Mb/s. • automatic cable equalization (typically greater than 350m of high quality cable) • serial data outputs muted and serial clock remains active when input data is lost • operation independent of SAV/EAV sync signals • signal strength indicator output • carrier detect with programmable threshold level The GS7025 requires only one external resistor to set the VCO centre frequency and provides adjustment free operation. • power savings mode (output serial clock disable) • large IJT, typically 0.56UI beyond loop bandwidth • robust lock detect APPLICATIONS Cable equalization plus clock and data recovery for all high speed serial digital interface applications involving SMPTE 259M-C. The GS7025 has dedicated pins to indicate signal strength, carrier detect, and LOCK. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. In addition, the GS7025 provides an 'Output Eye Monitor Test' (OEM_TEST) for diagnostic testing of signal integrity after equalization, prior to reslicing. The serial clock outputs can also be disabled to reduce power. The GS7025 operates from a single +5 or -5 volt supply. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE GS7025-CQM 44 pin MQFP Tray 0°C to 70°C GS7025-CTM 44 pin MQFP Tape 0°C to 70°C A/D DDI COSC ANALOG DIGITAL MUX DDI LOCK CARRIER DETECT PHASELOCK HARMONIC LOGIC MUTE SDO SDI + SDI -- FREQUENCY ACQUISITION VARIABLE GAIN EQ STAGE SDO CLK_EN PHASE DETECTOR SCO SCO OEM_TEST EYE MONITOR AUTO EQ CONTROL + AGC CAP CD_ADJ SSI/CD CHARGE PUMP LF+ LFS LF- VCO CBG RVCO BLOCK DIAGRAM Revision Date: November 2000 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected] www.gennum.com Document No. 522 - 80 - 00 GS7025 FEATURES ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage (VS) 5.5V Input Voltage Range (any input) VCC + 0.5 to VEE - 0.5V 0°C ≤ TA ≤ 70°C Operating Temperature Range GS7025 -65°C ≤ TS ≤ 150°C Storage Temperature Range Lead Temperature (soldering, 10 sec) 260°C DC ELECTRICAL CHARACTERISTICS VCC = 5.0V, TA = 25°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER CONDITION MIN TYPICAL 4.75 5 CLK_EN = 0 - 115 CLK_EN = 1 - 125 - 2.5 DDI Common Mode Input Voltage Range VEE+(VDIFF/2) DDI Differential Input Drive 1 MAX UNITS 5.25 V 1 mA 1 - V 1 0.4 to 4.6 VCC-(VDIFF/2) V 200 800 2000 mV 1 - - 18 µA 3 - - 110 µA 3 - 1.0 1.5 mA 3 AGC Common Mode Voltage - 2.7 - V 1 OEM_TEST Bias Potential - 4.5 - V High 2.0 - - V 1 Low - - 0.8 High 2.0 - - V 1 Low - - 0.8 High 2.5 - - V 1 Low - - 0.8 Supply Voltage Supply Current SDI Common Mode Voltage SSI/CD Output Current Source, NOTES 2 TEST LEVEL 1 CLMAX = 50pF, RL = open cct. Source, CLMAX = 50pF, RL=5K Sink A/D 270, CLK_EN, IN _ENABLE Input Voltage CLK_EN Input Voltage 5 1 2 GENNUM CORPORATION 522 - 80 - 00 DC ELECTRICAL CHARACTERISTICS (continued) VCC = 5.0V, TA = 25°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER CONDITION MIN TYPICAL 500 - LOCK Output Sink Current CLK_EN Source Current Low 1 MAX UNITS NOTES TEST LEVEL - - µA 3 1 26 55 µA 1 GS7025 NOTES 1. TYPICAL - measured on characterization board. 2. VDIFF is the differential input signal swing. 3. LOCK is an open collector output and requires an external pullup resistor. 4. If OEM_TEST is permanently enabled, operating temperature range is limited from 0°C to 60°C inclusive. TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. AC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VEE = 0V, TA = 25°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER CONDITIONS MIN TYPICAL 1 MAX UNITS NOTES TEST LEVEL Serial Data Rate SDI - 270 (only) - Mb/s 1 Maximum Equalizer Gain @ 135MHz - 35 - dB 7 270Mb/s, 300m (Belden 8281) - 300 - ps p-p 2, 7 3 270Mb/s - 185 - ps p-p 2, 6 4 270Mb/s - 462 - ps p-p 2, 6 1 Input Jitter Tolerance 270Mb/s 0.40 0.56 - UI p-p 3, 6 1 Lock Time - tswitch < 0.5µs, 270Mb/s - 1 - µs 4 7 0.5µs< tswitch <10ms - 1 - ms tswitch > 10 ms - 4 - ms 0.5 1 2 µs 5 7 -200 0 200 ps 7 (see Figure 3) Additive Jitter [Pseudorandom (2 23 -1)] Intrinsic Jitter [Pseudorandom (2 23 -1)] Intrinsic Jitter [Pathological (SDI checkfield)] Synchronous Switch Carrier Loss Time SDO to SCO Synchronization SDO, SCO Output Signal Swing 75Ω DC load 600 800 1000 mV p-p 1 SDO, SCO Rise & Fall times 20%-80% 200 300 400 ps 7 SDI/SDI Input Resistance - 10 - kΩ 7 6 SDI/SDI Input Capacitance - 1.0 - pF 7 6 15 20 - dB 7 6 SDI/SDI Input Return Loss at 270MHz 3 GENNUM CORPORATION 522 - 80 - 00 AC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VEE = 0V, TA = 25°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER Carrier Detect Response Time CONDITIONS Carrier Applied, MAX UNITS NOTES TEST LEVEL 3 - µs 7 6 30 - MIN TYPICAL - - 1 CL<50pF, RL=open cct. CL<50pF, RL=open cct. NOTES 1. TYPICAL - measured on characterization board. 2. Characterized 6 sigma rms. 3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz). 4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie. line 10 switching for component NTSC). 5. Carrier Loss Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed. 6. Using the DDI input, A/D=0. 7. Using the SDI input, A/D=1. TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. DATA TEKTRONIX GigaBERT 1400 TRANSMITTER DATA GS9028 CABLE DRIVER BELDEN 8281 CABLE CHARACTERIZATION BOARD TEKTRONIX GigaBERT 1400 ANALYZER CLOCK TRIGGER Fig. 1 Test Setup for Figures 5 and 6 4 GENNUM CORPORATION 522 - 80 - 00 GS7025 Carrier Removed, 39 38 37 36 35 34 VEE COSC 40 VCC LOCK 41 CLK_EN SSI/CD 42 VEE A/D 43 33 VEE 2 32 SDO 3 31 SDO VCC 4 30 VEE VEE 5 GS7025 29 SCO SDI 6 TOP VIEW 28 SCO SDI 7 27 VEE VCC 8 26 nc VEE 9 25 nc CD_ADJ 10 24 270 AGC- 11 23 nc 15 16 17 18 19 20 VEE LF+ LFS LF- VEE RVCO 21 22 VCC 14 CBG 13 RVCO_RTN 12 VCC VCC_75 1 AGC+ DDI GS7025 DDI MOD 44 OEM_TEST VCC_75 PIN CONNECTIONS PIN DESCRIPTIONS NUMBER SYMBOL TYPE DESCRIPTION 1, 2 DDI/DDI I Digital data inputs (Differential ECL/PECL). 3, 44 VCC_75 I Power supply connection for internal 75Ω pullup resistors connected to DDI/DDI. 4, 8, 13, 22, 35 VCC I Most positive power supply connection. 5, 9, 14, 18, 27, 30, 33, 34, 37 VEE I Most negative power supply connection. 6, 7 SDI/SDI I Differential analog data inputs. 10 CD_ADJ I Carrier detect threshold adjust. 11, 12 AGC-, AGC+ I External AGC capacitor. 15, 16, 17 LF+, LFS, LF- I Loop filter component connection. 19 RVCO_RTN I RVCO Return. 20 RVCO I Frequency setting resistor. 21 CBG I Internal bandgap voltage filter capacitor. 23, 25, 26 nc - No connect - Do not connect to power or ground. Leave floating. 24 270 I 270Mb/s Data Rate Select - Always set high. 28, 29 SCO/SCO O Serial clock output. SCO/SCO are differential current mode outputs and require external 75Ω pullup resistors. 31, 32 SDO/SDO O Equalized and reclocked serial digital data outputs. SDO/SDO are differential current mode outputs and require external 75Ω pullup resistors. 5 GENNUM CORPORATION 522 - 80 - 00 PIN DESCRIPTIONS (continued) NUMBER TYPE DESCRIPTION 36 CLK_EN I Clock enable. When HIGH, the serial clock outputs are enabled. 38 COSC I Timing control capacitor for internal system clock. 39 LOCK O Lock indication. When HIGH, the GS7025 is locked. LOCK is an open collector output and requires an external 10kΩ pullup resistor. 40 SSI/CD O Signal strength indicator/Carrier detect. 41 A/D I Analog/Digital select. 42 MOD I 270 Mb/s modulus select - Always set high. 43 OEM_TEST O Output ‘Eye’ monitor test. Single-ended current mode output that requires an external 50Ω pullup resistor. This feature is recommended for debugging purposes only. If enabled during normal operation, the maximum operating temperature is rated to 60°C. 6 GENNUM CORPORATION 522 - 80 - 00 GS7025 SYMBOL TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25°C unless otherwise shown) 450 400 4.50 350 JITTER (ps p-p) (Characterized) 4.00 3.50 300 250 GS7025 SSI/CD OUTPUT VOLTAGE (V) 5.00 200 270Mb/s 150 100 3.00 50 2.50 0 50 100 150 200 250 300 350 400 450 0 500 0 50 100 150 200 250 300 350 400 CABLE LENGTH (m) CABLE LENGTH (m) Fig. 2 SSI/CD Voltage vs. Cable Length (Belden 8281) (CD_ADJ = 0V) Fig. 5 Typical Additive Jitter vs. Input Cable Length (Belden 8281) 23 Pseudorandom (2 -1) 50 45 40 GAIN (dB) 35 30 25 20 15 10 5 0 1 10 100 1000 FREQUENCY (MHz) Fig. 3 Equalizer Gain vs. Frequency Fig. 6 Intrinsic Jitter (2 23 - 1 Pattern) 270Mb/s 0.600 5.0 0.550 270Mb/s 0.500 4.0 0.450 IJT (UI) CD_ADJ VOLTAGE (V) 4.5 3.5 3.0 0.400 0.350 0.300 2.5 0.250 2.0 200 250 300 350 0.200 400 CABLE LENGTH (m) 0 10 20 30 40 50 60 70 TEMPERATURE (C˚) Fig. 4 Carrier Detect Adjust Voltage Threshold Characteristics Fig. 7 Typical IJT vs. Temperature (VCC = 5.0V) (Characterized) 7 GENNUM CORPORATION 522 - 80 - 00 DETAILED DESCRIPTION The GS7025 Serial Digital Receiver is a bipolar integrated circuit containing a built-in cable equalizer and reclocker. Serial digital signals are applied to either the analog SDI/SDI or digital DDI/DDI inputs. Signals applied to the SDI/SDI inputs are equalized and then passed to a multiplexer. Signals applied to the DDI/DDI inputs bypass the equalizer and go directly to the multiplexer. The analog/digital select pin (A/D) determines which signal is then passed to the reclocker. Packaged in a 44 pin MQFP, the receiver operates from a single 5V supply at a data rate of 270Mb/s. 4 3 CD_ADJ CONTROL RANGE GS7025 SSI/CD OUTPUT VOLTAGE (V) 5 2 1 0 0 50 100 150 200 250 300 350 400 450 500 CABLE LENGTH (m) 1. CABLE EQUALIZER Fig. 8 SSI/CD Voltage vs. Cable Length The automatic cable equalizer is designed to equalize a serial digital data rate of 270Mb/s. When the signal strength decreases to the level set at the "Carrier Detect Threshold Adjust" pin, the SSI/CD voltage goes to a logic "0" state (0.8 V) and can be used to drive other TTL/CMOS compatible logic inputs. In addition, when loss of carrier is detected, the SDO/SDO outputs are muted (set to a known static state). The serial data signal is connected to the input pins (SDI/SDI) either differentially or single-endedly. The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The gain stage provides up to 35dB of gain at 135MHz which typically results in equalization of greater than 350m of Belden 8281 cable at 270Mb/s. 1-2. Carrier Detect Threshold Adjust This feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. To alleviate this problem, the GS7025 provides a user adjustable threshold to meet the unique conditions that exist in each user's application. Override and internal default settings have also been provided to give the user total flexibility. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by an external differential AGC filter capacitor (AGC+/AGC-) providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The threshold level at which loss of carrier is detected is adjustable via external resistors at the CD_ADJ pin (see Figure 4). The control voltage at the CD_ADJ pin is set by a simple resistor divider circuit (see Typical Application Circuit). The threshold level is adjustable from 200m to 350m. By default (no external resistors), the threshold is typically 320m. In noisy environments, it is not recommended to leave this pin floating. Connecting this pin to VEE disables the SDO/SDO muting function and allows for maximum possible cable length equalization. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its corrective level irrespective of shifts due to AC coupling. 1-1. Signal Strength Indication/Carrier Detect The GS7025 incorporates an analog signal strength indicator/carrier detect (SSI/CD) output indicating both the presence of a carrier and the amount of equalization applied to the signal. The voltage output of this pin versus cable length (signal strength) is shown in Figure 2 and Figure 8. 1-3. Output Eye Monitor Test The GS7025 also provides an 'Output Eye Monitor Test' (OEM_TEST) which allows the verification of signal integrity after equalization, prior to reslicing. The OEM_TEST pin is an open collector current output that requires an external 50Ω pullup resistor. When the pullup resistor is not used, the OEM_TEST block is disabled and the internal OEM_TEST circuit is powered down. The OEM_TEST With 0m of cable (800mV input signal levels), the SSI/CD output voltage is approximately 4.5V. As the cable length increases, the SSI/CD voltage decreases linearly providing accurate correlation between the SSI/CD voltage and cable length. 8 GENNUM CORPORATION 522 - 80 - 00 provides a 100mVp-p signal when driving a 50Ω oscilloscope input. Due to additional power consumed by this diagnostic circuit, it is not recommended for continuous operation. 2-2. VCO 2. RECLOCKER The reclocker receives a differential serial data stream from the internal multiplexer. It locks an internal clock to the incoming data. It outputs the differential PECL retimed data signal on SDO/SDO. It outputs the recovered clock on SCO/ SCO. The timing between the output and clock signals is shown in Figure 9. The recommended RVCO value applications is 365Ω. for SMPTE 259M-C When the input data stream is removed for an excessive period of time (see AC electrical characteristics table), the VCO frequency can drift from the 270Mb/s centre frequency to the limits shown in Table1. SDO TABLE 1: Frequency Drift Range SCO 50% FREQUENCY MIN (%) MAX(%) 270Mb/s lock -13 28 2-3. Phase Detector Fig. 9 Output and Clock Signal Timing The phase detector compares the phase of the PLL clock with the phase of the incoming data signal and generates error correcting timing pulses. The phase detector design provides a linear transfer function which maximizes the input jitter tolerance of the PLL. The reclocker contains three main functional blocks: the Phase Locked Loop, Frequency Acquisition, and Logic Circuit. 2-1. Phase Locked Loop (PLL) 2-4. Charge Pump The Phase Locked Loop locks the internal PLL clock to the incoming data rate. A simplified block diagram of the PLL is shown below. The main components are the VCO, the phase detector, the charge pump, and the loop filter. DDI/DDI The charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. A unique differential charge pump design insures that the output phase does not drift when data transitions are sparse. This makes the GS7025 ideal for SMPTE 259M-C applications where pathological signals have data transition densities of 0.05. 2 PHASE DETECTOR INTERNAL PLL CLOCK CHARGE PUMP LF+ LFS RLF CLF1 2-5. Loop Filter The loop filter integrates the charge pump packets and produces a VCO control voltage. The loop filter is comprised of three external components which are connected to pins LF+, LFS, and LF-. The loop filter design is fully differential giving the GS7025 increased immunity to PCB board noise. VCO LF- The loop filter components are critical in determining the loop bandwidth and damping of the PLL. Choosing these component values is discussed in detail in the PLL DESIGN GUIDELINES section. Recommended values for SMPTE 259M-C applications are shown in the Typical Application Circuit. No further changes from the recommended GS7025 loop filter components are necessary. RVCO LOOP FILTER CLF2 Fig. 10 Simplified Block Diagram of the PLL 9 GENNUM CORPORATION 522 - 80 - 00 GS7025 The VCO is a differential low phase noise, factory trimmed oscillator that provides increased immunity to PCB noise and precise control of the VCO centre frequency. The VCO has a pull range of ±15% about the centre frequency. A single low impedance external resistor, RVCO, sets the VCO centre frequency. The low impedance RVCO minimizes thermal noise and reduces the PLL's sensitivity to PCB noise. 3. FREQUENCY ACQUISITION 4. LOCKING The core PLL is able to lock if the incoming data rate and the PLL clock frequency are within the PLL capture range (which is slightly larger than the loop bandwidth). To assist the PLL to lock, the GS7025 uses a frequency acquisition circuit. The GS7025 indicates valid lock when the following three conditions are satisfied: 3. The system is not locked to an integer-multiple harmonic of a 270Mb/s SMPTE 259M-C signal. The GS7025 defines the presence of input data when at least one data transition occurs every 1µs. tsys tswp 2. The incoming data signal and the PLL clock are phase locked. The GS7025 assumes that it is NOT locked to a harmonic if the pattern ‘101’ or ‘010’ (in the reclocked data stream) occurs at least once every tsys/3 seconds. Using the recommended component values, this corresponds to approximately 150µs. In a harmonically locked system, all bit cells are double clocked and the above patterns become ‘110011’ and ‘001100’, respectively. VLF A Tcycle Tcycle = tswp + tsys Fig. 11 Typical Sweep Waveform 4-1. Lock Time The VCO frequency starts at point A and sweeps up attempting to lock. If lock is not established during the up sweep, the VCO is then swept down. The system is designed such that the probability of locking within one cycle period is greater than 0.999. If the system does not lock within one cycle period, it will attempt to lock in the subsequent cycle. The average sweep time, tswp, is determined by the loop filter component, CLF1, and the charge pump current, ΙCP: 4C LF1 t SWP = ---------------3I CP Synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). When input data to the GS7025 is removed, the GS7025 latches the current state. Therefore, when data is reapplied, the GS7025 begins the lock procedure at the previous locked data rate. As a result, in synchronous switching applications, the GS7025 locks very quickly. The nominal lock time depends on the switching time and is summarized in the Table 3. TABLE 3. The nominal sweep time is approximately 121µs when CLF1 = 15nF and ΙCP = 165µA (RVCO = 365Ω). An internal system clock determines tsys (see section 3-1, Logic Circuit). SWITCHING TIME LOCK TIME <0.5µs 10µs 0.5µs - 10ms 2tsys >10ms 2Tcycle + 2tsys 3-1. Logic Circuit The GS7025 is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. That is, the system clock is completely independent of the incoming data rate. The system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the PLL.The period of the system clock is set by the COSC capacitor and is: 4 t sys = 9.6 × 10 × C OSC [ sec onds ] The recommended value for tsys is 450µs (COSC = 4.7nF) To acquire lock, the frequency acquisition circuit may have to sweep over an entire cycle depending on initial conditions. Maximum lock time is 2Tcycle + 2tsys. The nominal value of Tcycle for the GS7025 operating in a typical SMPTE 259M-C application is approximately 1.3ms. The GS7025 has a dedicated LOCK output (pin 39) indicating when the device is locked. It should be noted that in synchronous switching applications where the switching time is less than 0.5µs, the LOCK output will NOT be de-asserted and the data outputs will NOT be muted. 10 GENNUM CORPORATION 522 - 80 - 00 GS7025 The frequency acquisition circuit sweeps the VCO control voltage so that the VCO frequency changes from -10% to +10% of the centre frequency. Figure 11 shows a typical sweep waveform. 1. Input data is detected. 1. Input signal amplitudes are between 200 and 2000mV. 5. OUTPUT DATA MUTING The GS7025 internally mutes the SDO and SDO outputs when the device is not locked. When muted, SDO/SDO are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. The output data muting timing is shown in Figure 12. VALID DATA VALID DATA OUTPUTS MUTED DDI Fig. 12 Output Data Muting Timing GS7025 DDI 6. CLOCK ENABLE When CLK_EN is high, the GS7025 SCO/SCO outputs are enabled. When CLK_EN is low, the SCO/SCO outputs are placed in a high Z state and float to VCC. Disabling the clock outputs results in a power savings of 10%. It is recommended that the CLK_EN input be hard wired to the desired state. For applications which do not require the clock output, connect CLK_EN to Ground and connect the SCO/SCO outputs to VCC. 7. STRESSFULL DATA PATTERNS All PLL's are susceptible to stressful data patterns which can introduce bit errors in the data stream. PLL's are most sensitive to patterns which have long run lengths of 0's or 1's (low data transition densities for a long period of time). The GS7025 is designed to operate with low data transition densities such as the SMPTE 259M-C pathological signal (data transition density = 0.05). Fig. 14 When trace lengths become greater than 1in, controlled impedance traces should be used. The recommended interface is shown in Figure 15. In this case, a parallel resistor (RLOAD) is placed near the GS7025 inputs to terminate the controlled impedance trace. The value of RLOAD should be twice the value of the characteristic impedance of the trace. In addition, place series resistors (RSOURCE) near the driving chip to serve as source terminations. They should be equal to the value of the trace impedance. Assuming 800mV output swings at the driver, RLOAD = 100Ω, RSOURCE = 50Ω and ZO = 50Ω. RSOURCE ZO DDI RLOAD RSOURCE GS7025 DDI ZO 8. I/O DESCRIPTION Fig. 15 8-1. High Speed Analog Inputs (SDI/SDI) SDI/SDI are high impedance inputs differential or single-ended input drive. which accept Figure 13 shows the recommended interface when a singleended serial digital signal is used. Figure 16 shows the recommended interface when the GS7025 digital inputs are driven single-endedly. In this case, the input must be AC-coupled and a matching resistor (Zo) must be used. DDI 75 10nF ZO SDI 75 113 10nF GS7025 DDI GS7025 SDI Fig. 16 Fig. 13 8-2. High Speed Digital Inputs (DDI/DDI) DDI/DDI are high impedance inputs which accept differential or single-ended input drive. Two conditions must be observed when interfacing to these inputs: When the DDI and the DDI inputs are not used, saturate one input of the differential amplifier for improved noise immunity. To saturate, connect either pins 44 and 1 or pins 2 and 3 to VCC. Leave the other pair floating. 11 GENNUM CORPORATION 522 - 80 - 00 GS7025 LOCK SDO Commonly used interface examples are shown in Figures 14 to 16. Figure 14 illustrates the simplest interface to the GS7025 digital inputs. In this example, the driving device generates the PECL level signals (800mV amplitudes) having a common mode input range between 0.4 and 4.6V. This scheme is recommended when the trace lengths are less than 1in. The value of the resistors depends on the output driver circuitry. NO DATA TRANSITIONS DDI 2. The common mode input voltage range is as specified in the DC Characteristics table. 8-3. High Speed Outputs (SDO/SDO and SCO/SCO) VCC SDO/SDO and SCO/SCO are current mode outputs that require external pullups (see Figure 17). The output signal swings are 800mV when 75Ω resistors are used. To shift the signal levels down by approximately 0.7 volts, place a diode between VCC and the pullups. When the output traces are longer than 1in, use controlled impedance traces. Place the pullup resistors at the end of the output traces as they terminate the trace in its characteristic impedance (75Ω). 75 75 75 75 GS7025 SDO SDO GS7025 SCO SCO VCC Fig. 17 TYPICAL APPLICATION CIRCUIT VCC 10k VCC VCC VCC VCC VCC VCC 44 43 42 41 40 39 38 37 36 35 34 VCC_75 OEM_TEST MOD A/D SSI/CD LOCK COSC VEE CLK_EN VCC VEE 4n7 2 DDI VCC 3 VCC_75 VCC 4 VCC 5 VEE 6 SDI SCO 28 7 SDI VEE 27 nc 26 9 VEE nc 25 10 CD_ADJ 11 AGC- 15 16 17 18 Power supply decoupling capacitors are not shown. 0.1µ VCC 1.8k 15n 19 VCC 14 CBG 13 20 21 22 365 (1%) VCC nc 23 RVCO 12 All resistors in ohms, all capacitors in microfarads, unless otherwise stated. RVCO_RTN 0.1µ 270 24 VEE 100k Pot (Optional) VCC 8 LF- VCC SCO 29 LFS 75 10n VCC GS7025 TOP VIEW LF+ 37.5 10n To GS9020 VEE 30 VEE 75 SDO 31 VCC 75 SDO 32 AGC+ see Note 1 4 x 75 see Note 2 33 DDI from GS9024 15nH VEE 1 VCC VCC 0.1µ 0.1µ 3.3p NOTES 1. It is recommended that the DDI/DDI inpute are not driven when the SDI/SDI inputs are being used. This minimizes crosstalk between the DDI/DDI and SDI/SDI inputs and maximizes performance. 2. These resistors are not needed if the internal pull-up resistors on the GS9020 are used. 12 GENNUM CORPORATION 522 - 80 - 00 PACKAGE DIMENSIONS 13.20 ±0.25 10.00 ±0.10 GS7025 13.20 ±0.25 10.00 ±0.10 PIN 1 0.80 BSC 0.45 MAX 0.30 MIN 5˚ to 16˚ 0.20 MIN 0˚ MIN 2.20 MAX 1.85 MIN 7˚ MAX 0˚ MIN 2.55 MAX 0.23 MAX. 0.35 MAX 0.15 MIN 0.3 MAX. RADIUS 5˚ to 16˚ 0.88 NOM. 0.13 MIN. RADIUS 1.60 REF All dimensions in millimetres 44 pin MQFP CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION REVISION NOTES: New document. DOCUMENT IDENTIFICATION PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change. GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 For latest product information, visit www.gennum.com GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright November 2000 Gennum Corporation. All rights reserved. Printed in Canada. 13 522 - 80 - 00