1CYW2331
PRELIMINARY
CYW2331
Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers
Features
Applications
The Cypress CYW2331 is a dual serial input PLL frequency
synthesizer which includes a 2.0-GHz RF and a 600-MHz IF
dual modulus prescaler to combine the RF and IF mixer frequency sections of wireless communication systems. The synthesizer is designed for cordless/cellular telephone systems,
cable TV tuners, WLANs and other wireless communication
systems. The device operates from 2.7V and dissipates only
24 mW.
• Operating voltage: 2.7V to 5.5V
• PLL1 operating frequency:
— 2.0 GHz with prescaler ratios of 64/65 and 128/129
• PLL2 operating frequency:
— 600 MHz with prescaler ratios of 8/9 and 16/17
• Lock detect feature
• Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
• Available in a 24-pin CSP (Chip Scale Package)
• Available in a 20-pin MLF
(Mirco Lead Frame Package)
CYW2331 Dual Hi-Lo PLL Block Diagram
GND (4)
FIN1 (5)
Prescaler
64/65 or
128/129
FIN1# (6)
GND (7)
Binary 7-Bit
Swallow Counter
VCC1 (1)
Binary 11-Bit
Programmable Counter
19-Bit
Latch
VCC2 (20)
VP1 (2)
fp1
Phase
Detector
DOPLL1 (3)
Charge
Pump
Pwr-dwn
PLL1
OSC_IN (8)
fr fp
Monitor
Output
Selector
fr1
15-Bit
Reference Counter
20-Bit Latch
Latch
Selector
LE (13)
FO/LD (10)
20-Bit Latch
DATA (12)
CLOCK (11)
FIN2 (16)
Prescaler
8/9 or
16/17
FIN2# (15)
fr2
15-Bit
Reference Counter
Cntrl 22-Bit
Shift
Reg.
19-Bit
Latch
Binary 4-Bit
Swallow Counter
Pwr-dwn
PLL2
Binary 11-Bit
Programmable Counter
GND (14)
Power
Control
Phase
Detector
Charge
Pump
GND (17)
VP2 (19)
DOPLL2 (18)
fp2
GND (9)
FIN1
5
FIN1#
GND
Vp2
17
DoPLL2
4
16
GND
Vcc2
DOPLL2
17
18
18
3
Vp1
DOPLL1
Vcc1
VP2
20
VCC2
19
19
20
2
Vp2
1
VP1
Vcc1
VCC1
Vcc2
Pin Configuration
NC
20
DoPLL2
DoPLL1
3
19
GND
DoPLL1
1
15
GND
GND
GND
4
18
Fin2
GND
2
14
Fin2
16
FIN2
Fin1
5
17
Fin2#
Fin1
3
13
Fin2#
6
15
FIN2#
Fin1#
6
16
GND
Fin1#
4
12
GND
7
14
GND
GND
7
15
LE
GND
5
11
LE
OSC_IN
8
14
DATA
NC
9
13
NC
TSSOP
Cypress Semiconductor Corporation
3901 North First Street
8
9
10
Fo/LD
DATA
MLF
CSP
•
CLOCK
GND
6
CLOCK
7
11
GND
10
(Top View)
OSC_IN
FO/LD
12
DATA
CLOCK
LE
12
10
13
9
11
8
GND
(Top View)
Fo/LD
OSC_IN
22
21
2
24
1
23
NC
Vp1
•
San Jose
•
CA 95134 • 408-943-2600
February 12, 2001. Rev. **
PRELIMINARY
CYW2331
Pin Definitions
Pin
No.
(TSSOP)
Pin
No.
(CSP)
Pin
No.
(MLF)
Pin
Type
VCC1
1
24
19
P
Power Supply Connection for PLL1 and PLL2: When power
is removed from both the VCC1 and VCC2 pins, all latched data
is lost.
VP1
2
2
20
P
PLL1 Charge Pump Rail Voltage: This voltage accommodates
VCO circuits with tuning voltages higher than the VCC of PLL1.
DOPLL1
3
3
1
O
PLL1 Charge Pump Output: The phase detector gain is IP/2π.
Sense polarity can be reversed by setting the FC bit in software
(via the Shift Register).
FIN1
5
5
3
I
Input to PLL1 Prescaler: Maximum frequency 2.0 GHz.
FIN1#
6
6
4
I
Complementary Input to PLL1 Prescaler: A bypass capacitor
should be placed as close as possible to this pin and must be
connected directly to the ground plane.
OSC_IN
8
8
6
I
Oscillator Input: This input has a VCC/2 threshold and CMOS
logic level sensitivity.
FO/LD
10
11
8
O
Lock Detect Pin of PLL1 Section: This output is HIGH when
the loop is locked. It is multiplexed to the output of the programmable counters or reference dividers in the test program mode.
(Refer to Table 3 for configuration.)
CLOCK
11
12
9
I
Data Clock Input: One bit of data is loaded into the Shift Register on the rising edge of this signal.
DATA
12
14
10
I
Serial Data Input
LE
13
15
11
I
Load Enable: On the rising edge of this signal, the data stored
in the Shift Register is latched into the reference counter and
configuration controls, PLL1 or PLL2 depending on the state of
the control bits.
FIN2#
15
17
13
I
Complementary Input to PLL2 Prescaler: A bypass capacitor
should be placed as close as possible to this pin and must be
connected directly to the ground plane.
FIN2
16
18
14
I
Input to PLL2 Prescaler: Maximum frequency 600 MHz.
DOPLL2
18
20
16
O
PLL2 Charge Pump Output: The phase detector gain is IP/2π.
Sense polarity can be reversed by setting the FC bit in software
(via the Shift Register).
VP2
19
22
17
P
PLL2 Charge Pump Rail Voltage: This voltage accommodates
VCO circuits with tuning voltages higher than the VCC of PLL2.
VCC2
20
23
18
P
Power Supply Connections for PLL1 and PLL2: When power
is removed from both the VCC1 and VCC2 pins, all latched data
is lost.
GND
4, 7, 9,
14, 17
4, 7,
10,
16, 19
2, 5, 7,
12, 15
G
Analog and Digital Ground Connections: This pin must be
grounded.
N/C
N/A
1, 9,
13, 21
N/A
N/C
Pin Name
Pin Description
No Connect
2
PRELIMINARY
Absolute Maximum Ratings
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
Parameter
Description
VCC or VP
Power Supply Voltage
VOUT
Output Voltage
CYW2331
Rating
Unit
–0.5 to +6.5
V
–0.5 to VCC+0.5
V
IOUT
Output Current
±15
mA
TL
Lead Temperature
+260
°C
TSTG
Storage Temperature
–55 to +150
°C
Handling Precautions
Always turn off power before adding or removing devices from
system.
Devices should be transported and stored in antistatic containers.
Protect leads with a conductive sheet when handling or transporting PC boards with devices.
These devices are static sensitive. Ensure that equipment and
personnel contacting the devices are properly grounded.
If devices are removed from the moisture protective bags for
more than 36 hours, they should be baked at 85°C in a moisture free environment for 24 hours prior to assembly in less
than 24 hours.
Cover workbenches with grounded conductive mats.
Recommended Operating Conditions
Parameter
Description
VCC1,
VCC2
Power Supply Voltage
VP
Charge Pump Voltage
TA
Operating Temperature
Test Condition
Ambient air at 0 CFM flow
3
Rating
Unit
2.7 to 5.5
V
VCC to +5.5
V
–40 to +85
°C
PRELIMINARY
CYW2331
Electrical Characteristics: VCC = VP = 2.7V to 5.5V, TA = –40°C to +85°C, Unless otherwise specified
Parameter
Description
Test Condition
Pin
Min.
Typ.
Max.
Unit
ICC
Power Supply Current
PLL1 + PLL2
VCC1 = VCC2 = 3.0V
VCC1,
VCC2
8
IPD
Power-down Current
Power-down, VCC = 3.0V
VCC1,
VCC2
1
FIN1
Operating Frequency
PLL1
FIN1
100
2000
MHz
PLL2
FIN2
45
600
MHz
OSC_IN
5
45
MHz
10
MHz
FIN2
FOSC
Oscillator Input
Frequency
Fφ
Phase Detector
Frequency
PFIN1
Input Sensitivity
VCC = 2.7V
FIN1
VCC = 2.7V to 5.5V
VOSC
Oscillator Input Sensitivity VCC = 3.0V
IIH, IIL
High/Low Level Input
Current
VIH
High Level Input Voltage
µA
4
dBm
–10
4
dBm
FIN2
–10
4
dBm
OSC_IN
0.5
VP–P
–100
VCC = 3.0V
25
–15
VCC = 5.5V
PFIN2
mA
DATA,
CLOCK,
LE
100
VCC * 0.8
µA
V
VIL
Low Level Input Voltage
VCC * 0.2
V
IIH
High Level Input Current
–10
0.5
10
µA
IIL
Low Level Input Current
–10
0.5
10
µA
VOH
High level Output Voltage
VCC = 3.0V, IOH = –1 mA
VCC = 3.0V, IOL = 1 mA
FO/LD
VCC = VP = 3.0V,
DO = VP/2
DOPLL1
DOPLL2
VCC * 0.8
V
VOL
Low Level Output Voltage
IDOH(SO)
IDO High, Source Current
VCC * 0.2
IDOL(SO)
IDO Low, Source Current
IDOH(SI)
IDO High, Sink Current
IDOL(SI)
IDO Low, Sink Current
∆IDO
IDO Charge Pump Sink
and Source Mismatch
VCC = VP = 3.0V,
[IIDO(SI)I – IIDO(SO)I]/
[1/2*{IIDO(SI)]I+IIDO(SO)I}]*100%
3
IDO vs T
Charge Pump Current
Variation vs. Temperature
–40°C<T<85°C VDO = VP/2[1]
5
%
IOFF
Charge Pump High-ImVCC = VP = 3.0V
pedance Leakage Current
±2.5
nA
mA
–1
mA
3.8
mA
1
Note:
1. IDOvs T; Charge pump current variation vs. temperature.
[IIDO(SI)@TI - IIDO(SI)@25° CI]/IIDO(SI)@25°CI * 100% and
[IIDO(SO)@TI - IIDO(SO)@25°CI]/IIDO(SO)@25°CI *100%.
4
V
–3.8
mA
15
%
PRELIMINARY
CYW2331
Timing Waveforms
Key:
FC Bit HIGH
FC Bit LOW
Increasing
Voltage
(Refer to Table 2 for meaning of FC bit.)
Increasing Frequency
Phase Comparator Sense
VCO Characteristics
Phase Detector Output Waveform
FR
FP
tw
tw
LD
DO Charge Pump Output Current Waveform
FR
FP
tw
tw
Do
IDO
High-Impedance
State
5
PRELIMINARY
CYW2331
Timing Waveforms (continued)
Serial Data Input Timing Waveform[2, 3, 4, 5]
//
//
DATA
PD = MSB
PRE
B1
A7
CNT2
//
//
CLOCK
t2
t1
LE
CNT1 = LSB
//
//
t4
t3
//
//
//
//
t5
t6
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data as described in Table 1.
Table 1. Control Configuration
CNT1
CNT2
Function
0
0
Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector
polarity, set current in PLL2, set PLL2 to Hi-Impedance state, set monitor selector to PLL2.
0
1
Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector
polarity, set current in PLL1, set PLL1 to Hi-Impedance state, set monitor selector to PLL1
1
0
Program Counter for PLL2: A = 0 to 15, B = 3 to 2047, set PLL2 prescaler ratio, set PLL2
to power-down.
1
1
Program Counter for PLL1: A = 0 to 127, B = 3 to 2047, set PLL1 prescaler ratio, set
PLL1 to power-down.
Notes:
2. t1–t5 = t > 0.5 µs.
3. CLOCK may remain HIGH after latching in data.
4. DATA is shifted in with the MSB first.
5. For DATA definitions, refer to Table 2.
6
PRELIMINARY
CYW2331
Table 2. Shift Register Configuration[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TS
LD
FO
Reference Counter and Configuration Bits
CNT1 CNT2 R1
R2
R3
R4
R5
R6
R7
R8
R9 R10 R11 R12 R13 R14 R15 FC IDO
A4
A5
A6
A7
B1
B2
Programmable Counter Bits
CNT1 CNT2 A1
A2
A3
B3
B4
B5
B6
B7
B8
B9
B10 B11 PRE PD
Bit(s) Name
Function
CNT1, CNT2
Control Bits: Directs programming data to PLL1 (high frequency) or PLL2 (low frequency).
R1–R15
Reference Counter Setting Bits: 15 bits, R = 3 to 32767.[7]
FC
Phase Sense of the Phase Detector: Set to match the VCO polarity, H = + (Positive VCO transfer function).
IDO
Charge Pump Setting Bit: IDO HIGH = 3.8 mA, IDO LOW = 1 mA at VP = 3V.
TS
Hi-Impedance State Bit: Makes DO High-Impedance for PLL1 and PLL2 when HIGH.
LD
Lock Detect: Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when
locked. When not locked, this pin is LOW.
FO
Frequency Out: This bit can be set to read out reference or programmable divider at the LD pin for test
purposes.
PRE
Prescaler Divide Bit: For PLL1: LOW = 64/65 and HIGH = 128/129. For PLL2: LOW = 8/9 and HIGH = 16/17.
PD
Power-down: LOW = power-up and HIGH = power-down. FIN is at a high-impedance state, respective B
counter is disabled, forces DO outputs to Hi-Impedance and phase comparators are disabled. The reference
counter is disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be
input and latched in the power-down state.
A1–A7
Swallow Counter Divide Ratio: A = 0 to 127 for PLL1 and 0 to 15 for PLL2.
B1–B11
Programmable Counter Divide Ratio: B = 3 to 2047.[7]
Table 3. FO/LD Pin Truth Table
FO (Bit 22)
LD (Bit 21)
PLL1
PLL2
PLL1
PLL2
0
0
0
0
Disable
0
0
0
1
PLL2 Lock Detect
0
0
1
0
PLL1 Lock Detect
0
0
1
1
PLL1/PLL2 Lock Detect
0
1
X
0
PLL2 Reference Divider Output
1
0
X
0
PLL1 Reference Divider Output
0
1
X
1
PLL2 Programmable Divider Output
1
0
X
1
PLL1 Programmable Divider Output
1
1
0
1
PLL2 Counter Reset
1
1
1
0
PLL1 Counter Reset
1
1
1
1
PLL1/PLL2 Counter Reset
Notes:
6. The MSB is loaded in first.
7. Low count ratios may violate frequency limits of the phase detector.
7
FO/LD Pin Output State
PRELIMINARY
CYW2331
Table 4. 7-Bit Swallow Counter (A) Truth Table[8]
Divide Ratio A
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
:::
:::
:::
:::
:::
:::
:::
:::
126
1
1
1
1
1
1
0
127
1
1
1
1
1
1
1
X
X
X
0
0
0
0
PLL1 (High Frequency)
PLL2 (Low Frequency)
0
1
X
X
X
0
0
0
1
:::
:::
:::
:::
:::
:::
:::
:::
14
X
X
X
1
1
1
0
15
X
X
X
1
1
1
1
Table 5. 11-Bit Programmable Counter (B) Truth Table[9]
Divide Ratio B
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
2046
1
1
1
1
1
1
1
1
1
1
0
2047
1
1
1
1
1
1
1
1
1
1
1
Table 6. 15-Bit Programmable Reference Counter (for PLL1 and PLL2) Truth Table[9]
Divide Ratio R
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
32766
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information[10]
Ordering Code
Package
Name
Package Type
Tape and Reel Option
CYW2331
ZI
BCI
LFI
20-pin Thin Shrink Small Outline Package (0.173” wide)
24-pin Chip Scale Package (3.5 mm X 4.5 mm)
20-pin Micro Lead Frame (4 mm x 4 mm)
TR
Notes:
8. B is greater than or equal to A.
9. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:
fvco = {(P * B) + A} * fosc / R where (A < B)
fvco: Output frequency of the external VCO.
fosc: The crystal reference oscillator frequency.
A: Preset divide ratio of the 7-bit swallow counter (0 to 127) and the 4-bit swallow counter (0 to 15).
B: Preset ratio of the 11-bit programmable counter (3 to 2047).
P: Preset divide ratio of the dual modulus prescaler.
R: Preset ratio of the 15-bit programmable reference counter (3 to 32767).
The divide ratio N = (P * B) + A.
10. Operating temperature range: –40°C to +85°C.
Document #: 38-00967-**
8
PRELIMINARY
CYW2331
Typical Performance Characteristics
Charge P um p Current vs D o Voltage
Icp=Low
Charge P um p Current vs D o Voltage
Icp=High
1 .5
6
V p=5V
1
4
0 .5
Do Current (mA)
2
Do Current (mA)
V p=3V
Vp=5V
Vp=3V
0
Vp=3V
Vp = 5V
-2
0
-0 .5
V p=3V
V p = 5V
-4
-1
-6
1
0
2
D o Voltage (V)
3
4
5
-1 .5
0
2
1
100
MKR
100.0kHz
4
5
Do Output Current Low Mode
Do Output Current High Mode
VAVG
10dB/
3
Figure 3.
Figure 1.
ATTEN
10dB
RL
-2.5dBm
D o Voltage (V)
-85.50dB
1
8 5 dB c
2
START
RBW
835.8505MHz
3.0kHz
STOP
VBW
3.0kHz
836.1505MHz
SWP
84.0ms
4
3
Marker Reference
Real
Number
Figure 3. PLL
Reference
Spurs
Figure
2.
PLL Reference Spurious Level is –85.5 dBc
Imaginar y Input
Frequency
100 MHz
–823
Marker 1
623
Marker 2
21
–120
1 GHz
14
–55
1.8 GHz
13
–39
2.2 GHz
Marker 3
Marker 4
Figure 4.
Input Impedance FIN1, FIN2
9
PRELIMINARY
Package Diagram
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173” wide)
10
CYW2331
PRELIMINARY
CYW2331
Package Diagram
24-Pin Chip Scale Package (CSP 3.5 mm X 4.5 mm)
f
d
0.20
0.10
Z
4X
Z
3.50
X
d
0.10
Z
PIN 1 PAD CORNER
4.50
1.04±0.10
Y
0.70±0.05
TOP VIEW
SIDE VIEW
PIN 1 PAD CORNER
22
24
21
1
0.45 X 0.25 TYP
j
0.15 m
Z X Y
0.50
ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M-1994.
UNLESS OTHERWISE SPECIFIED
4X 0.25
9
13
12
10
0.50
4X 1.25
BOTTOM VIEW
11
PRELIMINARY
CYW2331
Package Diagram
20-Pin Micro Lead Frame Package (MLF 4 mm X 4 mm)
2X
0.25
A
C
D
A
10
D/2
0.05
D1
C
b
M
D2/2
A3
0.25
C
CA B
D2
A2
2X
N
0.10
R
A1
D1/2
4
4X P
A
8.
N
B
4X P
5
6
0.50 DIA.
E1/2
1
1
E/2
2
2
3
E1
4X Q
E
3
C B
2X
0
B
0.20
(Ne-1)Xe
REF.
E2/2
L
0.20
E2
e
C
C A
SEATING
PLANE
2X
TOP VIEW
(Nd-1)Xe
REF.
C C
CL
CL
4
A1
b
11
BOTTOM VIEW
SECTION "C-C"
e
SCALE: NONE
e
TERMINAL TIP
FOR ODD TERMINAL/SIDE
S
Y
M
B
O
L
A
A1
A2
A3
D
D1
E
E1
0
P
R
e
N
Nd
Ne
L
b
Q
D2
E2
COMMON
DIMENSIONS
MIN.
NOM.
MAX.
0.00
-
0.24
0.13
0.50
0.18
0.30
1.55
1.55
0.85
0.01
0.65
0.20 REF.
4.00 BSC
3.75 BSC
4.00 BSC
3.75 BSC
0.42
0.17
0.50 BSC
20
5
5
0.60
0.23
0.40
1.70
1.70
1.00
0.05
0.80
FOR EVEN TERMINAL/SIDE
NOTES:
N
PACKAGE OUTLINE, MLF2, 4X4mm BODY
1. DIE THICKNESS ALLOWABLE IS 0.305mm MAXIMUM(.012 INCHES MAXIMUM)
2. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. - 1994.
O
T
E
11
3. N IS THE NUMBER OF TERMINALS.
Nd IS THE NUMBER OF TERMINALS IN X-DIRECTION &
Ne IS THE NUMBER OF TERMINALS IN Y-DIRECTION.
4. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.20 AND 0.25mm FROM TERMINAL TIP.
5.
3
3
3
0.75
0.30
0.65
1.85
1.85
THE PIN #1 IDENTIFIER MUST BE EXISTED ON THE TOP SURFACE OF THE
PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF PACKAGE BODY.
12
0.60
0.23
6.
EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
7.
ALL DIMENSIONS ARE IN MILLIMETERS.
8.
THE SHAPE SHOWN ON FOUR CORNERS ARE NOT ACTUAL I/O.
9.
PACKAGE WARPAGE MAX 0.05mm.
10. APPLIED FOR EXPOSED PAD AND TERMINALS.
EXCLUDE EMBEDDING PART OF EXPOSED
PAD FROM MEASURING.
4
11.
APPLIED ONLY FOR TERMINALS.
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.