EDI8L21665V 2x64Kx16 SRAM, DSP Memory Solution FEATURES DESCRIPTION ■ Access Times of 10, 12 and 15ns The EDI8L21665VxxBC is a 3.3V, 2x64Kx16 SRAM constructed with two 64Kx16 die mounted on a multi-layer laminate substrate. The device is packaged in a 74 lead, 15mm by 15mm, BGA. ■ DSP Memory Solution • Texas Instruments TMS320C5x Operating with a 3.3V power supply and with access times as fast as 10ns, the device allows the user to develop a fast external memory for Texas Instuments’ TMS320C5x DSP. ■ Packaging: • 74 pin BGA, JEDEC MO-151 ■ 3.3V Operating Supply Voltage The device consists of two separate banks of 64Kx16 of memory. Each bank has a separate Chip Enable pin and higher order address select pin. Bank ‘A’ is controlled using CE 1\ and A15A. Bank ‘B’ is controlled using CE2\ and A15B . The two banks have common I/Os (DQ0-15) and control lines (WE\, E\ and G\). E\ connects to the mstrb\ pin of the C54x DSPs and is required for write and read timing control. ■ Single Write Control and Output Enable Lines ■ One Chip Enable Line per Memory Bank ■ 50% Space Savings vs. Monolithic TSOPs ■ Upgrade Path Available in Same Footprint ■ Multiple VCC and V SS Pins ■ Reduced Inductance and Capacitance PIN CONFIGURATION 1 A Vss 2 Vcc B Vss Vcc C Vss Vss D Vss E Vss 3 4 5 6 7 8 BLOCK DIAGRAM 9 10 Vcc DQ15 DQ14 Vcc DQ13 DQ11 DQ9 DQ8 Vcc Vss Vss 11 NC Vcc DQ12 DQ10 DQ4 Vcc Vcc B Vcc Vss Vcc C Vss Vss Vcc D Vss Vss Vcc DQ3 DQ7 F G W DQ5 DQ0 G H Vss CE 2 DQ6 DQ1 H I Vss A 14 J Vss A 12 Vcc A10 A8 Vss A6 A4 K A 15B A 13 Vcc A11 A9 Vss A7 2 3 4 5 6 7 1 February 1999 Rev. 0 ECO # Vcc G CE A15 E F A 15A CE 1 E A0-14 G W CE1 A15A E A DQ2 NC I A2 A0 G J V SS A5 A3 A1 K 8 9 10 11 U1 64K X 16 SSRAM U2 CE2 A15A 1 CE A15 64K X 16 SSRAM White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI8L21665V PIN DESCRIPTIONS Pin Symbol Type A0-14 Input Addresses Description A15A Input Addresses: A15 on Bank ‘A’ of memory A15B Input Addresses: A15 on Bank ‘B’ of memory W Input Write Enable: This active LOW input allows a full 16-bit WRITE to occur. CE1 Input Chip Enable: This active LOW input is used to enable the ‘A’ Bank of the device. CE2 Input Chip Enable: This active LOW input is used to enable the ‘B’ Bank of the device. G Input Output Enable: This active LOW asynchronous input enables the data output drivers. Various DQ0-15 Input/Output Various Vcc Supply Various Vss Ground E Input Data Inputs/Outputs Core power supply: +3.3V -5%/+10% Ground Enable, This active LOW input controls Write and Read Timing ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss RECOMMENDED OPERATING CONDITIONS -0.5V to 4.6V Symbol Min Max -0.5V to Vcc+0.5V Input High Voltage VIH 2.2 Vcc+0.5 V Storage Temperature -55°C to +125°C Input Low Voltage V IL -0.3 0.8 V Junction Temperature +125°C Supply Voltage Vcc 3.0 3.6 V Power Dissipation 3 Watts V IN Short Circuit Output Current (per I/O) Description Unit CAPACITANCE (f = 1MHz, VIN = VCC or VSS) 50 mA * Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Address Lines Data Lines Control Lines Symbol Max Unit CA 8 pF CD/Q 17 pF CC 15 pF DC ELECTRICAL CHARACTERISTICS (f = 1MHz, VIN = V CC or Vss) Parameter Symbol Power Supply Current: Operating ICC1 CMOS Standby ISB2 TTL Standby ISB3 Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ILI ILO VOH VOL White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com Conditions -10ns Device Selected; all inputs ≤ VIL or ≥ V IH; cycle time ≥ tKC MIN; -12ns VCC = MAX; outputs open -15ns Device deselected; VCC = MAX; all inputs ≤ V SS +0.2 or ≥ V CC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs ≤ V IL or ≥ VIH; all inputs static; VCC = MAX; CLK frequency = 0 0V ≤ V IN ≤ VCC Output(s) disabled, 0V ≤ VOUT ≤ VCC IOH = -4.0mA IOL = 8.0mA 2 Min -5 -5 2.4 Max Units 380 360 260 mA 60 mA 120 mA 5 5 µA µA V V 0.4 EDI8L21665V AC ELECTRICAL CHARACTERISTICS Symbol Read Cycle Min 10ns Max 10 12ns Min Max 12 Min 15ns Max Units Read Cycle Time t AVAV 15 Address Access Time t AVQV 10 12 15 ns Chip Enable Access t ELQV 10 12 15 ns Output Hold from Address Change t AVQX 3 4 4 Chip Enable to Output in Low-Z t ELQX 3 4 4 Chip Disable to Output in High-Z t EHQZ Output Enable access time t GLQV Output Enable to Output in Low-Z t GLQX Output Disable to Output in High-Z t GHQZ 5 ns ns 6 5 0 ns 6 0 7 ns 7 ns 7 ns 0 5 ns 6 Write Cycle Write Cycle Time tAVAV 10 12 15 ns Chip Enable to End of Write t ELWH 8 8 9 ns t AVGHWH 8 8 9 ns Address Setup Time t AVWL 0 0 0 ns Address Hold from End of Write t AVWH 8 8 10 ns Address valid to End of Write, with G HIGH Write Pulse Width t WLWH 10 10 11 ns t WLGHWH 8 8 9 ns Data Setup Time tDVWH 6 6 7 ns Data Hold Time tWHDX 0 0 0 ns Write Disable to Output in Low-Z t WHQX 3 4 5 Write Enable to Output in High-Z t WLQZ Write Pulse Width, with G HIGH 5 AC TEST CIRCUIT 7 ns AC TEST CONDITIONS Parameter Output ns 6 Z0 Z0==50Ω 50Ω Input Pulse Levels Input Rise and Fall Times (max) Input and Output Timing Levels 50Ω Output Load I/O Unit VSS to 3.0 V 1.5 ns 1.5 V See figure, at left Vt = 1.5V 1.25V AC Output Load Equivalent 3 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI8L21665V READ CYCLE TIMING DIAGRAMS tAVAV A tAVQV E tAVAV A ADDRESS 1 ADDRESS 2 tAVQV tAVQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ G Q DATA 1 Q DATA 2 READ CYCLE 1 (W HIGH; G, E LOW) READ CYCLE 2 (W HIGH) WRITE CYCLE TIMING DIAGRAM tAVAV A tAVEL tEHAX tELEH E tAVEH W tDVEH D tEHDX DATA VALID HIGH Z Q WRITE CYCLE 2, E CONTROLLED NOTES: All Writes are E controlled when connected to the TMS320C54X. E is connected to MSTRB and W is connected to R/W of the TMS320C54X. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 4 EDI8L21665V ORDERING INFORMATION Commercial Temperature Range (0°C to +70°C) Part Number Speed (ns) EDI8L21665V10BC 10 EDI8L21665V12BC 12 428 EDI8L21665V15BC 15 428 PACKAGE DESCRIPTION: Industrial Temperature Range (-40°C to +85°C) Part Number Speed (ns) EDI8L21665V15BI 15 Package No. 428 Package No. 428 74 PIN BGA PACKAGE NO. 428 THERMAL PACKAGE PERFORMANCE: θJ A = 28°C/Watt (Natural Connection) 0.591 SQ. θJ B = 4°C/Watt 0.029 MAX 0.125 MAX ALL DIMENSIONS ARE IN INCHES 5 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com