GALVANTECH, INC. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM SYNCHRONOUS BURST SRAM FLOW-THROUGH 128K x 36 SRAM +3.3V CORE SUPPLY, +2.5V I/O SUPPLY REGISTERED INPUTS, BURST COUNTER FEATURES GENERAL DESCRIPTION • • • • • • • • • • • The Galvantech Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The GVT71128E36 SRAM integrates 131,072x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE#), depth-expansion chip enables (CE2# and CE2), burst control inputs (ADSC#, ADSP#, and ADV#), write enables (BW1#, BW2#, BW3#, BW4#,and BWE#), and global write (GW#). Asynchronous inputs include the output enable (OE#), burst mode control (MODE), and sleep mode control (ZZ). The data outputs (Q), enabled by OE#, are also asynchronous. Addresses and chip enables are registered with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#). Address, data inputs, and write controls are registered onchip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BW1# controls DQ1-DQ8 and DQP1. BW2# controls DQ9-DQ16 and DQP2. BW3# controls DQ17-DQ24 and DQP3. BW4# controls DQ25-DQ32 and DQP4. BW1#, BW2# BW3#, and BW4# can be active only with BWE# being LOW. GW# being LOW causes all bytes to be written. The GVT71128E36 operates from a +3.3V core power supply and all outputs operate on a +2.5V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. The device is ideally suited for 486, PentiumTM, 680x0, and PowerPCTM systems and for systems that are benefited from a wide synchronous data bus. • • • • • Fast access times: 7.5, 8, 8.5, and 10ns Fast clock speed: 117, 100, 90, and 50 MHz Provide high performance 2-1-1-1 access rate Fast OE# access times: 4.0ns 3.3V -5% and +10% core power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/O’s Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs BYTE WRITE ENABLE and GLOBAL WRITE control Three chip enables for depth expansion and address pipeline Address, data and control registers Internally self-timed WRITE CYCLE Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low profile 119 lead, 14mm x 22mm BGA (Ball Grid Array) and 100 pin TQFP packages OPTIONS • • MARKING Timing 7.5ns access/8.5ns cycle 8ns access/10ns cycle 8.5ns access/11ns cycle 10ns access/20ns cycle -7 -8 -9 -10 Packages 119-lead BGA 100-pin TQFP B T Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Rev. 5/98 Pentium is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM GALVANTECH, INC. FUNCTIONAL BLOCK DIAGRAM BYTE 1 WRITE BW1# BWE# D Q CLK BYTE 2 WRITE BW2# D Q GW# BYTE 3 WRITE BW3# D Q BYTE 4 WRITE ENABLE D CE2 Q byte 2 write byte 1 write CE# Q byte 3 write D byte 4 write BW4# CE2# ZZ Power Down Logic OE# ADSP# Address Register 128K x 9 x 4 SRAM Array ADSC# CLR ADV# A1-A0 Binary Counter & Logic Output Buffers A16-A2 Input Register DQ1-DQ32, DQP1, DQP2 DQP3, DQP4 MODE NOTE: May 29, 1998 Rev. 5/98 The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. 2 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM GALVANTECH, INC. 1 2 3 4 5 6 7 A VCCQ A6 A4 ADSP# A8 A16 VCCQ B NC CE2 A3 ADSC# A9 CE2# NC C NC A7 A2 VCC A12 A15 NC A6 A7 CE# CE2 BW4# BW3# BW2# BW1# CE2# VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A8 A9 PIN ASSIGNMENT (Top View) 100 99 D DQ17 DQP3 VSS NC VSS DQP2 DQ16 E DQ18 DQ19 VSS CE# VSS DQ14 DQ15 F VCCQ DQ20 VSS OE# VSS DQ13 VCCQ G DQ21 DQ22 BW3# ADV# BW2# DQ12 DQ11 H J DQ23 DQ24 VCCQ VSS VCC NC GW# VCC VSS DQ10 VCC NC DQ9 VCCQ K DQ25 DQ27 VSS CLK VSS DQ7 DQ8 L DQ26 DQ28 BW4# NC BW1# DQ5 DQ6 M VCCQ DQ29 VSS BWE# VSS DQ4 VCCQ N DQ30 DQ31 VSS A1 VSS DQ3 DQ2 P DQ32 DQP4 VSS A0 VSS DQP1 DQ1 R NC A5 MODE VCC NC A13 NC T NC NC A10 U VCCQ NC NC A11 NC A14 NC NC NC ZZ VCCQ DQP3 DQ17 DQ18 VCCQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VCCQ DQ23 DQ24 NC VCC NC VSS DQ25 DQ26 VCCQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VCCQ DQ31 DQ32 DQP4 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 100-pin PQFP or 100-pin TQFP 15 16 17 66 65 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 DQP2 DQ16 DQ15 VCCQ VSSQ DQ14 DQ13 DQ12 DQ11 VSSQ VCCQ DQ10 DQ9 VSS NC VCC ZZ DQ8 DQ7 VCCQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VCCQ DQ2 DQ1 DQP1 50 MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A10 A11 A12 A13 A14 A15 A16 TOP VIEW 119 LEAD BGA 98 1 PIN DESCRIPTIONS BGA PINS QFP PINS SYMBOL TYPE 4P, 4N, 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49,50 A0-A16 Input- 5L, 5G, 3G, 3L 93,94,95,96 BW1#, BW2#, BW3#, BW4# 4M 87 BWE# DESCRIPTION Addresses: These inputs are registered and must meet the setup and hold Synchronous times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. Input- Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ Synchronous cycle. BW1# controls DQ1-DQ8 and DQP1. BW2# controls DQ9-DQ16 and DQP2. BW3# controls DQ17-DQ24 and DQP3. BW4# controls DQ25-DQ32 and DQP4. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE# being LOW. Input- Write Enable: This active LOW input gates byte write operations and must Synchronous meet the setup and hold times around the rising edge of CLK. 4H 88 GW# Input- Global Write: This active LOW input allows a full 36-bit WRITE to occur Synchronous independent of the BWE# and BWn# lines and must meet the setup and hold times around the rising edge of CLK. 4K 89 CLK Input- Clock: This signal registers the addresses, data, chip enables, write control Synchronous and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge. 4E 98 CE# Input- Chip Enable: This active LOW input is used to enable the device and to gate Synchronous ADSP#. 6B 92 CE2# Input- Chip Enable: This active LOW input is used to enable the device. Synchronous May 29, 1998 Rev. 5/98 3 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM GALVANTECH, INC. PIN DESCRIPTIONS (continued) BGA PINS QFP PINS SYMBOL TYPE 2B 97 CE2 input- 4F 86 OE# 4G 83 ADV# DESCRIPTION Chip enable: This active HIGH input is used to enable the device. Synchronous Input Output Enable: This active LOW asynchronous input enables the data output drivers. Input- Address Advance: This active LOW input is used to control the internal Synchronous burst counter. A HIGH on this pin generates wait cycle (no address advance). 4A 84 ADSP# Input- Address Status Processor: This active LOW input, along with CE# being Synchronous LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. 4B 85 ADSC# Input- Address Status Controller: This active LOW input causes device to be Synchronous de-selected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. 3R 31 MODE 7T 64 ZZ InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Input- Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). Asynchronous 7P, 7N, 6N, 6M, 6L, 7L, 6K, 52, 53, 56, 57, 58, DQ1-DQ32 7K, 7H, 6H, 7G, 6G, 6F, 6E, 59, 62, 63, 68, 69, 7E, 7D, 1D, 1E, 2E, 2F, 1G, 72-75, 78, 79, 2, 3, 2G, 1H, 2H, 1K, 1L, 2K, 2L, 6-9, 12, 13, 18, 19, 2M, 1N, 2N, 1P Input/ Output Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25-DQ32. Input data must meet setup and hold times around the rising edge of CLK. Input/ Output Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity bit for DQ9-DQ16. DQP3 is parity bit for DQ17-DQ24 and DQP4 is parity bit for DQ25-DQ32. 22-25, 28, 29 6P, 6D, 2D, 2P 51, 80, 1, 30 DQP1 DQP4 4C, 2J, 4J, 6J, 4R 15, 41,65, 91 VCC Supply Core power Supply: +3.3V -5% and +10% 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 17, 40, 67, 90 VSS Ground Ground: GND. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 4, 11, 20, 27, 54, 61, 70, 77 VCCQ I/O Supply Output Buffer Supply: +2.5V (from 2.375V to VCC) 5, 10, 21, 26, 55, 60, 71, 76 VSSQ I/O Ground Output Buffer Ground: GND 1B, 7B, 1C, 7C, 4D, 3J, 5J, 14, 16, 38, 39, 42, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 43, 66 2U, 3U, 4U, 5U, 6U NC - No Connect: These signals are not internally connected. BURST ADDRESS TABLE (MODE = NC/VCCQ) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A10 A...A11 A...A00 A...A01 A...A11 A...A10 A...A01 A...A00 BURST ADDRESS TABLE (MODE = GND) First Address (external) Second Address (internal) Third Address (internal) A...A00 A...A01 A...A10 A...A11 A...A01 A...A10 A...A11 A...A00 May 29, 1998 Rev. 5/98 Fourth Address (internal) A...A10 A...A11 A...A00 A...A01 A...A11 A...A00 A...A01 A...A10 4 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM GALVANTECH, INC. TRUTH TABLE ADDRESS USED CE# CE2# CE2 Deselected Cycle, Power Down None H X X X Deselected Cycle, Power Down None L X L L Deselected Cycle, Power Down None L H X L Deselected Cycle, Power Down None L X L Deselected Cycle, Power Down None L H READ Cycle, Begin Burst External L READ Cycle, Begin Burst External L OPERATION ADSP# ADSC# ADV# WRITE# OE# CLK DQ L X X X L-H High-Z X X X X L-H High-Z X X X X L-H High-Z H L X X X L-H High-Z X H L X X X L-H High-Z L H L X X X L L-H Q L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H D READ Cycle, Begin Burst External L L H H L X H L L-H Q READ Cycle, Begin Burst High-Z External L L H H L X H H L-H READ Cycle, Continue Burst Next X X X H H L H L L-H Q READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Q READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H D WRITE Cycle, Continue Burst Next H X X X H L L X L-H D READ Cycle, Suspend Burst Current X X X H H H H L L-H Q READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Q READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D Note: 1. 2. 3. 4. 5. 6. 7. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# + BW1#*BW2#*BW3#*BW4#]*GW# equals LOW. WRITE# = H means [BWE# + BW1#*BW2#*BW3#*BW4#]*GW# equals HIGH. BW1# enables write to DQ1-DQ8 and DQP1. BW2# enables write to DQ9-DQ16 and DQP2. BW3# enables write to DQ17DQ24 and DQP3. BW4# enables write to DQ25-DQ32 and DQP4. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. Suspending burst generates wait cycle. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time for OE# and staying HIGH throughout the input data hold time. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. PARTIAL TRUTH TABLE FOR READ/WRITE FUNCTION READ READ WRITE one byte WRITE all bytes WRITE all bytes May 29, 1998 Rev. 5/98 GW# BWE# BW1# BW2# BW3# BW4# H H H H L H L L L X X H L L X X H H L X X H H L X X H H L X 5 Galvantech, Inc. reserves the right to change products or specifications without notice. GALVANTECH, INC. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Supply Relative to VSS......-0.5V to +4.6V VIN .........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) .......................-55oC to +125o Junction Temperature ...................................................+125o Power Dissipation ..........................................................1.6W Short Circuit Output Current (per I/O).........................20mA DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0oC ≤ Ta ≤ 70°C; VCC = 3.3V -5% and +10% unless otherwise noted) DESCRIPTION CONDITIONS Input High (Logic 1) Voltage SYMBOL MIN MAX UNITS NOTES Data Inputs (DQxx) VIHD 1.7 VCC+0.3 V 1,2 All Other Inputs VIH 1.7 4.6 V 1,2 VIl -0.3 0.7 V 1, 2 14 Input Low (Logic 0) Voltage Input Leakage Current 0V < VIN < VCC ILI -2 2 uA Output Leakage Current Output(s) disabled, 0V < VOUT < VCC ILO -2 2 uA Output High Voltage IOH = -2.0mA VOH 1.7 Output Low Voltage IOL = 2.0mA VOL Supply Voltage I/O Supply Voltage DESCRIPTION CONDITIONS Power Supply Current: Operating V 1, 11 0.7 V 1, 11 VCC 3.135 3.6 V 1 VCCQ 2.375 VCC V 1 SYM TYP -7 -8 -9 -10 Device selected; all inputs < VILor > VIH;cycle time > tKC MIN; VCC =MAX; outputs open Icc 150 370 320 290 200 mA 3, 12, 13 CMOS Standby Device deselected; VCC = MAX; all inputs < VSS +0.2 or >VCC -0.2; all inputs static; CLK frequency = 0 ISB2 5 10 10 10 10 mA 12,13 TTL Standby Device deselected; all inputs < VIL or > VIH ; all inputs static; VCC = MAX; CLK frequency = 0 ISB3 10 20 20 20 20 mA 12,13 Clock Running Device deselected; all inputs < VIL or > VIH; VCC = MAX; CLK cycle time > tKC MIN ISB4 40 80 70 60 40 mA 12,13 May 29, 1998 Rev. 5/98 6 UNITS NOTES Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM GALVANTECH, INC. AC ELECTRICAL CHARACTERISTICS (Note 5) (0oC ≤ TA ≤ 70oC; VCC = 3.3V -5% and +10%) -7 DESCRIPTION -8 MAX MIN -9 MAX MIN - 10 SYM MIN MAX MIN MAX UNITS Clock cycle time tKC 8.5 10 11 20 ns Clock HIGH time tKH 3 4 4.5 4.5 ns Clock LOW time tKL 3 4 4.5 4.5 ns NOTES Clock Output Times tKQ Clock to output valid 7.5 8 8.5 10 tKQX 2 2 2 2 Clock to output in Low-Z tKQLZ 0 0 0 0 Clock to output in High-Z tKQHZ 2 Clock to output invalid OE to output valid tOEQ OE to output in Low-Z tOELZ OE to output in High-Z tOEHZ 3.5 2 3.5 4.0 2 3.5 4.0 0 2 0 3.5 ns 4.0 0 ns 4, 6,7 3.5 ns 4, 6,7 4.0 ns 9 ns 4, 6,7 ns 4, 6,7 0 3.5 ns 3.5 3.5 Setup Times Address, Controls and Data In tS 1.5 2.0 2.0 2.0 ns 10 tH 0.5 0.5 0.5 0.5 ns 10 Hold Times Address, Controls and Data In CAPACITANCE DESCRIPTION CONDITIONS Input Capacitance TA = 25oC; f = 1 MHz VCC = 3.3V Input/Output Capacitance (DQ) SYMBOL TYP MAX UNITS NOTES CI 4 5 pF 4 CO 7 8 pF 4 THERMAL CONSIDERATION DESCRIPTION CONDITIONS SYMBOL TQFP TYP UNITS Thermal Resistance - Junction to Ambient Still air, soldered on 4.25 x 1.125 inch 4-layer PCB ΘJA 25 oC/W ΘJC 9 oC/W Thermal Resistance - Junction to Case NOTES TYPICAL OUTPUT BUFFER CHARACTERISTICS OUTPUT HIGH VOLTAGE PULL-UP CURRENT OUTPUT LOW VOLTAGE PULL-DOWN CURRENT VOH (V) ΙΟΗ(mΑ) Μin ΙΟΗ(mΑ) Μax VOL (V) ΙΟL(mΑ) Μin ΙΟL(mΑ) Μax May 29, 1998 Rev. 5/98 -0.5 -38 -105 -0.5 0 0 -38 -105 0 0 0 0.8 -38 -105 0.4 10 20 1.25 -26 -83 0.8 20 40 1.5 -20 -70 1.25 31 63 2.3 0 -30 1.6 40 80 2.7 0 -10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80 7 0 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM GALVANTECH, INC. OUTPUT LOADS AC TEST CONDITIONS Input pulse levels 0V to 2.5V Input slew rate DQ 1.0V/ns Output rise and fall times(max) Input timing reference levels 1.25V Output reference levels 1.25V Output load Z0 = 50Ω 1.8ns 50Ω Vt = 1.25V Fig. 1 OUTPUT LOAD EQUIVALENT See Figures 1 15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. NOTES 1. All voltages referenced to VSS (GND). 2. Overshoot: Undershoot: 3. Icc is given with no output current. Icc increases with greater output loading and faster cycle times. 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. Measured at + 200mV from steady state. 7. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 8. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE. 9. OE# is a “don’t care” when a byte write enable is sampled LOW. VIH ≤ +6.0V for t ≤ tKC /2. VIL ≤ -2.0V for t ≤ tKC /2 10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “don’t care” as defined in the truth table. 11. AC I/O curves are available upon request. 12. “Device Deselected” means the device is in POWER -DOWN mode as defined in the truth table. “Device Selected” means the device is active. 13. Typical values are measured at 3.3V, 25oC and 20ns cycle time. 14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of +30 µA. May 29, 1998 Rev. 5/98 8 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM GALVANTECH, INC. READ TIMING tKC t KL CLK t t S KH ADSP# t H ADSC# t S A1 ADDRESS A2 t H BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# (See Note) t S ADV# t H OE# tKQ tKQLZ DQ tKQ t OEQ tOELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) Q(A2+2) BURST READ Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. May 29, 1998 Rev. 5/98 9 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM GALVANTECH, INC. WRITE TIMING CLK tS ADSP# tH ADSC# tS ADDRESS A1 A2 A3 tH BW1#, BW2#, BW3#, BW4#, BWE# GW# CE# (See Note) tS ADV# tH OE# tOEHZ tKQX DQ Q D(A1) D(A2) D(A2+2) SINGLE WRITE D(A2+2) D(A2+2) D(A2+3) D(A3) BURST WRITE D(A3+1) D(A3+2) BURST WRITE Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. May 29, 1998 Rev. 5/98 10 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM GALVANTECH, INC. READ/WRITE TIMING CLK tS ADSP# tH ADSC# tS ADDRESS A1 A2 A3 A4 A5 tH BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# (See Note) ADV# OE# DQ Q(A1) Q(A2) Single Reads D(A3) Q(A4) Single Write Q(A4+1) Q(A4+2) Q(A4+3) Burst Read D(A5) D(A5+1) Burst Write Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. May 29, 1998 Rev. 5/98 11 Galvantech, Inc. reserves the right to change products or specifications without notice. GALVANTECH, INC. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM 100 Pin TQFP Package Dimensions 16.00 + 0.10 14.00 + 0.10 #1 22.00 + 0.10 20.00 + 0.10 1.40 + 0.05 1.60 Max 0.65 Basic 0.30 + 0.08 0.60 + 0.15 Note: All dimensions in Millimeters May 29, 1998 Rev. 5/98 12 Galvantech, Inc. reserves the right to change products or specifications without notice. GALVANTECH, INC. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM 7 x 17 (119-lead) BGA Dimensions 22.00 + 0.20 20.32 1.27 7 5 4 3 1.27 7.62 14.00 + 0.20 6 2 1 U T R P N M L K J o 0.75+0.15 (119X) H G F E D C B A BOTTOM VIEW 0.70 REF. PIN 1A CORNER TOP VIEW 2.40 MAX. 0.90 + 0.10 12.00 + 0.10 19.50 + 0.10 30 TYP. 0.56 REF. 0.60 + 0.10 SIDE VIEW Note: All dimensions in Millimeters May 29, 1998 Rev. 5/98 13 Galvantech, Inc. reserves the right to change products or specifications without notice. GALVANTECH, INC. GVT71128E36 128K X 36 SYNCHRONOUS BURST SRAM Ordering Information GVT 71128E36 X - XX Galvantech Prefix Speed (7 = 7.5ns access/8.5ns cycle 8 = 8.0ns access/10ns cycle 9 = 8.5ns access/11ns cycle 10 = 10ns access/20ns cycle) Part Number Package (B = 119 LEAD BGA, T = 100 PIN TQFP) May 29, 1998 Rev. 5/98 14 Galvantech, Inc. reserves the right to change products or specifications without notice.