ETC GVT73512A8J-10I

GALVANTECH, INC.
ASYNCHRONOUS
SRAM
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
512K x 8 SRAM
+3.3V SUPPLY
REVOLUTIONARY PINOUT
FEATURES
GENERAL DESCRIPTIO N
•
•
•
•
•
•
•
•
•
•
•
The GVT73512A8 is organized as a 524,288 x 8 SRAM
using a four-transistor memory cell with a high performance,
silicon gate, low-power CMOS process. Galvantech SRAMs
are fabricated using double-layer polysilicon, double-layer
metal technology.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable (CE#) and output
enable (OE#) with this organization.
Writing to these devices is accomplished when write
enable (WE#) and chip enable (CE#) inputs are both LOW.
Reading is accomplished when (CE#) and (OE#) go LOW
with (WE#) remaining HIGH. The device offers a low power
standby mode when chip is not selected. This allows system
designers to meet low standby power requirements.
Fast access times: 10, 12 and 15ns
Fast OE# access times: 5, 6and 7ns
Single +3.3V +0.3V power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise immunity
JEDEC standard for functionality and revolutionary pinout
Easy memory expansion with CE# and OE# options
Automatic CE# power down
High-performance, low-power consumption, CMOS
double-poly, double-metal process
OPTIONS
•
•
•
•
MARKING
Timing
10ns access
12ns access
15ns access
-10
-12
-15
Packages
36-pin SOJ (400 mil)
J
Power consumption
Standard
Low
None
L
Temperature
Commercial
Industrial
None
I
PIN ASSIGNMENT
36-Pin SOJ
(0°C to 70°C)
(-40°C to 85°C)
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com
Rev. 1/99
A0
A1
A2
A3
A4
CE#
DQ1
DQ2
VCC
VSS
DQ3
DQ4
WE#
A5
A6
A7
A8
A9
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13
24
14
23
15
22
16
21
17
20
18
19
NC
A18
A17
A16
A15
OE#
DQ8
DQ7
VSS
VCC
DQ6
DQ5
A14
A13
A12
A11
A10
NC
Galvantech, Inc. reserves the right to chang
e
products or specifications without notice
.
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
GALVANTECH,
FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A0
MEMORY ARRAY
1024 ROWS X 512 X 8
COLUMNS
I/O CONTROL
ADDRESS BUFFER
ROW DECODER
DQ1
DQ8
CE#
WE#
OE#
A18
COLUMN DECODER
POWER
DOWN
TRUTH TABLE
MODE
READ
WRITE
OUTPUT DISABLE
STANDBY
CE#
WE#
OE#
DQ
POWER
L
L
L
H
H
L
H
X
L
X
H
X
Q
D
HIGH-Z
HIGH-Z
ACTIVE
ACTIVE
ACTIVE
STANDBY
PIN DESCRIPTION S
SOJ Pin
Numbers
SYMBOL
TYPE
A0-A18
Input
Addresses Inputs: These inputs determine which cell is addressed .
13
WE#
Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW
for a WRITE cycle and HIGH for a READ cycle .
6
CE#
Input
Chip Enable: This active LOW input is used to enable the device. When CE# is LOW, the
chip is selected. When CE# is HIGH, the chip is disabled and automatically goes into
standby power mode .
1, 2, 3, 4, 5, 14, 15,
16, 17, 18, 20, 21,
22, 23, 24, 32, 33,
34, 35
DESCRIPTION
Input
Output Enable: This active LOW input enables the output drivers .
Input/Outpu t SRAM Data I/O: Data inputs and data output s
31
OE#
7, 8,11, 12,
25, 26, 29, 3 0
DQ1-DQ8
9, 27
VCC
Supply
Power Supply:3.3V +0.3V
10, 28
VSS
Supply
Ground
January 20, 199 9
Rev. 1/99
2
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
GALVANTECH,
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS *
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V
VIN ..........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ..........................-55oC to +125o
Junction Temperature .....................................................+125o
Power Dissipation ...........................................................1.2W
Short Circuit Output Current .......................................50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITION S
(All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) voltag e
VIH
2.2
VCC+0.5
V
1, 2
Input Low (Logic 0) Voltag e
VIl
-0.5
0.8
V
1, 2
Input Leakage Curren t
0V < VIN < VCC
ILI
-5
5
uA
Output Leakage Curren t
Output(s) disabled,
0V < VOUT < VCC
ILO
-5
5
uA
Output High Voltag e
IOH = -4.0mA
VOH
2.4
Output Low Voltag e
IOL = 8.0mA
VOL
Supply Voltag e
VCC
DESCRIPTION
CONDITIONS
Power Supply
Current: Operatin g
TTL Standb y
CMOS Standb y
3.0
V
1
0.4
V
1
3.6
V
1
SYM
TYP
POWER
-10
-12
-15
Device selected; CE# < VIL; VCC =MAX;
f=fMAX; outputs ope n
Icc
90
240
210
175
240
210
175
CE# >VIH; VCC = MAX; f=fMAX
ISB1
standard
low
standard
low
70
60
50
70
60
50
CE1# >VCC -0.2; VCC = MAX ;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0
30
ISB2
0.1
standard
low
10
10
10
3.0
3.0
3.0
UNITS NOTES
mA
3, 14
mA
14
mA
14
CAPACITANCE
DESCRIPTION
CONDITIONS
Input Capacitanc e
TA = 25oC; f = 1 MH z
VCC = 3.3V
Input/Output Capacitance (DQ )
January 20, 199 9
Rev. 1/99
SYMBOL
MAX
UNITS
NOTES
CI
6
pF
4
CI/O
8
pF
4
3
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
GALVANTECH,
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 3.3V +0.3V)
DESCRIPTION
- 10
- 12
MAX
MIN
- 15
SYM
MIN
MAX
MIN
MAX
UNITS NOTES
READ cycle tim e
tRC
10
Address access tim e
tAA
10
12
15
ns
tACE
10
12
15
ns
READ Cycle
Chip Enable access tim e
12
15
tOH
3
3
3
Chip Enable to output in Low- Z
tLZCE
3
3
3
Chip disable to output in High- Z
tHZCE
Output hold from address chang e
Output Enable access tim e
5
tAOE
Output Enable to output in Low- Z
tLZOE
Output Enable to output in High- Z
tHZOE
Chip Enable to power-up tim e
tPU
Chip disable to power-down tim e
tPD
6
5
0
6
0
ns
ns
4, 7
7
ns
4, 6, 7
7
ns
0
5
0
ns
6
0
ns
7
0
10
12
15
ns
4, 6
ns
4
ns
4
WRITE Cycle
WRITE cycle tim e
tWC
10
12
15
ns
Chip Enable to end of writ e
tCW
8
8
9
ns
Address valid to end of write, with OE#
HIGH
tAW
8
8
9
ns
Address setup tim e
tAS
0
0
0
ns
Address hold from end of writ e
tAH
0
0
0
ns
WRITE pulse widt h
tWP2
10
10
11
ns
WRITE pulse width, with OE# HIG H
tWP1
8
8
9
ns
Data setup tim e
tDS
5
6
7
ns
Data hold tim e
tDH
0
0
0
ns
Write disable to output in Low- Z
tLZWE
3
4
5
Write Enable to output in High- Z
tHZWE
January 20, 199 9
Rev. 1/99
6
6
4
7
ns
4, 7
ns
4, 6, 7
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
GALVANTECH,
OUTPUT LOADS
AC TEST CONDITIONS
Input pulse levels
DQ
0V to 3.0V
Input rise and fall times
1.5ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
Z0 = 50Ω
50Ω
30 pF
Vt = 1.5V
Fig. 1 OUTPUT LOAD EQUIVALENT
See Figures 1 and 2
3.3v
317Ω
DQ
5 pF
351Ω
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
8.
WE# is HIGH for READ cycle.
1.
All voltages referenced to VSS (GND).
9.
2.
Overshoot:
Undershoot:
Device is continuously selected. Chip enable and output enables
are held in their active state.
VIH ≤ +6.0V for t ≤ tRC /2.
VIL ≤ -2.0V for t ≤ tRC /2
3.
Icc is given with no output current. Icc increases with greater
output loading and faster cycle times.
4.
This parameter is sampled.
5.
Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
6.
Output loading is specified with CL=5pF as in Fig. 2. Transition
is measured +500mV from steady state voltage.
7.
At any given temperature and voltage condition, tHZCE is less
than tLZCE and tHZWE is less than tLZWE.
10. Address valid prior to, or coincident with, latest occurring chip
enable.
11. tRC = Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a
WRITE cycle.
13. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1.
14. Typical values are measured at 3.3V, 25oC and 20ns cycle time.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only )
DESCRIPTION
CONDITIONS
SYMBOL
MIN
VDR
ICCDR
ICCDR
2
Chip Deselect to
Data Retention Tim e
tCDR
Operation Recovery Tim e
tR
Vcc for Retention Dat a
Data Retention Curren t
January 20, 199 9
Rev. 1/99
CE# >VCC -0.2;
all other inputs < VSS +0.2
or >VCC -0.2;
all inputs static; f= 0
Vcc = 2V
Vcc = 3V
5
TYP
MAX
UNITS
NOTES
0.2
1.6
mA
13
0.3
2.4
mA
13
0
ns
4
tRC
ns
4, 11
V
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
GALVANTECH,
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
3.0V
VCC
3.0V
VDR
t
CDR
CE#
tRC
VIH
VIL
READ CYCLE NO. 1(8, 9)
tRC
ADDR
VALID
tAA
tOH
Q
PREVIOUS DATA VALID
DATA VALID
READ CYCLE NO. 2(7, 8, 10, 12)
t
RC
CE#
tAOE
tLZOE
OE#
tHZCE
tACE
t
tLZCE
Q
HIGH Z
HZOE
DATA VALID
DON'T CARE
UNDEFINED
January 20, 199 9
Rev. 1/99
6
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GALVANTECH,
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
WRITE CYCLE NO. 1(7, 12, 13)
(Write Enable Controlled with Output Enable OE# active LOW))
t WC
ADDR
tAW
t
t AH
CW
CE#
tWP2
tAS
WE#
tDS
D
tDH
DATA VALID
tHZWE
tLZWE
Q
HIGH Z
WRITE CYCLE NO. 2(12, 13)
(Write Enable Controlled with Output Enable OE# inactive HIGH)
t WC
ADDR
tAW
t
t AH
CW
CE#
tWP1
tAS
WE#
tDS
D
Q
tDH
DATA VALID
HIGH Z
DON'T CARE
UNDEFINED
January 20, 199 9
Rev. 1/99
7
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
GALVANTECH,
WRITE CYCLE NO. 3(12, 13)
(Chip Enable Controlled)
t
WC
ADDR
tAW
t
tAH
t
AS
CW
CE#
tWP1
WE#
tDS
D
Q
tDH
DATA VALID
HIGH Z
DON'T CARE
January 20, 199 9
Rev. 1/99
8
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
GALVANTECH,
Package Dimension s
36-pin 400 Mil Plastic SOJ (J)
.941 (23.90)
.923 (23.44)
.405 (10.29)
.395 (10.03)
.445 (11.30)
.435 (11.05)
PIN #1 INDEX
.148 (3.76)
.138 (3.51)
.050 (1.27) TYP
.030 (0.76)
MIN
.095 (2.41)
.080 (2.03)
SEATING
PLANE
.020 (0.51)
.015 (0.38)
Note: All dimensions in inches (millimeters)
MAX
MIN
.380 (9.65)
.360 (9.14)
or typical, min where noted.
Ordering Information
GVT 73512A8 XX - XX X X
Galvantech Prefix
Temperature (Blank = Commercial
I = Industrial)
Power (Blank= Standard,
L= Low Power)
Part Number
Speed ( 10 = 10ns, 12 = 12ns
15 = 15ns)
Package (J = 400 mil SOJ)
January 20, 199 9
Rev. 1/99
9
Galvantech, Inc. reserves the right to change products or specifications without notice
.