ETC GVT73128S16TS-10

GALVANTECH, INC.
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
ASYNCHRONOUS
SRAM
64K x 16 x 2 SRAM
+3.3V SUPPLY, TWO CHIP ENABLES
REVOLUTIONARY PINOUT
FEATURES
GENERAL DESCRIPTIO N
•
•
•
•
•
•
•
•
•
•
The GVT73128S16 is organized as a 65,536 x 16 x 2
SRAM using a four-transistor memory cell with a high
performance, silicon gate, low-power CMOS process.
Galvantech SRAMs are fabricated using triple-layer
polysilicon, double-layer metal technology.
This device consists of two banks of 64K x 16 memory.
Each bank of memory has its own chip enable pin and the
highest order address. Memory bank A has CEA# and A15A
as its chip enable and high order address. Memory bank B has
CEB# and A15B as its chip enable and high order address.
The other low order addresses (A0 to A14) along with the
write enable (WE#) and output enable (OE#) are shared by
both memory banks.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enables (CEA# and CEB#)
and output enable (OE#) with this organization.
Writing to these devices is accomplished when write
enable (WE#) and chip enables (CEA# and/or CEB#) inputs
are both LOW. Reading is accomplished when (CEA# or
CEB#) and (OE#) go LOW with (WE#) remaining HIGH.
The device offers a low power standby mode when both
banks of memory are not selected. This allows system
designers to meet low standby power requirements.
•
Fast access times: 10, 12, and 15ns
Fast OE# access times: 5, 6, and 7ns
Single +3.3V +0.3V power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise immunity
Easy memory expansion with CE# and OE# options
Automatic CE# power down
High-performance, low-power consumption, CMOS
triple-poly, double-metal process
Packaged in 44-pin, 400-mil TSOP and 44-pin TQFP
OPTIONS
•
•
•
•
MARKING
Timing
10ns access
12ns access
15ns access
-10
-12
-15
Packages
44-pin TSOP (400 mil)
44-pin TQFP
TS
T
Power consumption
Standard
None
Temperature
Commercial
None
(0°C to 70°C)
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699 Web Site: http://www.galvantech.com
Rev. 1/99
Galvantech, Inc. reserves the right to chang
e
products or specifications without notice
.
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
GALVANTECH,
FUNCTIONAL BLOCK DIAGRAM
CEA#
VCC
A14
A15B
DQ1
I/O CONTROL
MEMORY ARRAY
256 ROWS X 256 X 16
COLUMNS
DQ16
COLUMN DECODER
MEMORY ARRAY
256 ROWS X 256 X 16
COLUMNS
I/O CONTROL
A0
ROW
DECODER
A15A
ROW
DECODER
A14
ADDRESS BUFFER
A0
ADDRESS BUFFER
VSS
COLUMN DECODER
CEB#
WE#
OE#
PIN ASSIGNMENT
PIN ASSIGNMENT
44-Pin TQFP
33
2
32
3
31
4
30
5
29
6
28
23
DQ16
DQ15
DQ14
DQ13
VSS
VCC
DQ12
DQ11
DQ10
DQ9
CEB#
WE#
A0
A1
A2
A3
A4
NC
A5
A6
A7
A8
22
11
21
24
20
10
19
25
18
9
17
26
16
8
15
27
14
7
13
A4
A3
A15A
A15B
A0
CEA#
DQ1
DQ2
DQ3
DQ4
VCC
VSS
DQ5
DQ6
DQ7
DQ8
WE#
A2
A1
A14
A13
A12
34
35
36
37
38
39
40
41
42
1
12
CEA#
DQ1
DQ2
DQ3
DQ4
VCC
VSS
DQ5
DQ6
DQ7
DQ8
43
44
A14
A15B
A15A
A13
A12
A11
A10
A9
OE#
NC
NC
PIN ASSIGNMENT
44-Pin TSOP
January 22, 199 9
Rev. 1/99
2
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
A5
A6
A7
OE#
NC
NC
DQ16
DQ15
DQ14
DQ13
VSS
VCC
DQ12
DQ11
DQ10
DQ9
CEB#
A8
A9
A10
A11
NC
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
GALVANTECH,
TRUTH TABLE
MODE
CEA#
CEB#
WE#
OE#
DQ1DQ16
POWE R
L
H
L
H
L
L
H
H
L
H
L
L
H
L
H
H
L
L
L
H
H
L
L
X
X
X
H
H
Q
Q
D
D
D
HIGH-Z
HIGH-Z
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
H
H
X
X
HIGH-Z
STANDBY
BANK A MEMORY READ
BANK B MEMORY READ
BANK A MEMORY WRITE
BANK B MEMORY WRITE
BOTH BANK MEMORY WRITE
OUTPUT DISABLE
STANDBY
PIN DESCRIPTION S
TQFP
Pin Number s
TSOP
Pin Number s
13-17, 19-22, 37-41, 5, 19, 18, 2, 1, 44, 43,
44
42, 27, 26, 25, 24,
22, 21, 20
SYMBO L
TYPE
DESCRIPTIO N
A0-A14
Input
Low Order Addresses Inputs: These inputs, along with the
high order address, determine which cell is addressed.
42
3
A15A
Input
High Order Addresses Input: This input, along with A0-A14,
determine which cell of bank A memory is addressed.
43
4
A15B
Input
High Order Addresses Input: This input, along with A0-A14,
determine which cell of bank B memory is addressed.
12
17
WE#
Input
Write Enable: This input determines if the cycle is a READ
or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH
for a READ cycle.
1
6
CEA#
Input
Bank A Enable: This active LOW input is used to enable
bank A of the device. When CEA# is LOW, bank A of the
chip is selected. When CEA# is HIGH, bank A of the chip is
disabled.
23
28
CEB#
Input
Bank B Enable: This active LOW input is used to enable
bank B of the device. When CEB# is LOW, bank B of the
chip is selected. When CEB# is HIGH, bank B of the chip is
disabled.
36
41
OE#
Input
Output Enable: This active LOW input enables the output
drivers.
2, 3, 4, 5, 8, 9,
10, 11, 24,25, 26,
27, 30, 31, 32, 33
7, 8, 9, 10, 13, 14,
15, 16, 29, 30, 31,
32, 35, 36, 37, 38
DQ1-DQ16
6, 28
11, 33
VCC
Supply
7, 29
12, 34
VSS
Supply
18, 34, 35
23, 39, 40
NC
-
January 22, 199 9
Rev. 1/99
Input/Output SRAM Data I/O: Data inputs and data outputs.
Power Supply: 3.3V +0.3V
Ground
N0 Connect: These signals are not internally connected.
3
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GALVANTECH,
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS *
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V
VIN ..........................................................-0.5V to VCC+1.0V
Storage Temperature (plastic) ..........................-55oC to +125o
Junction Temperature .....................................................+125o
Power Dissipation ...........................................................1.0W
Short Circuit Output Current .......................................50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITION S
(All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted)
DESCRIPTIO N
CONDITION S
SYMBO L
MIN
MAX
UNITS
NOTE S
Input High (Logic 1) voltage
VIH
2.2
VCC+0.5
V
1, 2
Input Low (Logic 0) Voltage
VIl
-0.5
0.8
V
1, 2
Input Leakage Current
0V < VIN < VCC
ILI
-5
5
uA
Output Leakage Current
Output(s) disabled,
0V < VOUT < VCC
ILO
-5
5
uA
Output High Voltage
IOH = -4.0mA
VOH
2.4
Output Low Voltage
IOL = 8.0mA
VOL
Supply Voltage
VCC
DESCRIPTIO N
CONDITION S
Power Supply
Current: Operating
TTL Standby
CMOS Standby
3.0
V
1
0.4
V
1
3.6
V
1
SYM
TYP
POWER
-10
-12
-15
Device selected; CEA# or CEB# < VIL;
VCC =MAX; f=fMAX; outputs open
Icc
70
230
200
170
210
180
150
CEA# and CEB# >VIH; VCC = MAX;
f=fMAX
ISB1
standard
low
standard
low
35
30
25
30
25
20
CEA# and CEB# >VCC -0.2; VCC = MAX;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0
ISB2
10
0.02
standard
low
10
10
10
1.5
1.5
1.5
UNITS NOTES
mA
3, 14
mA
14
mA
14
CAPACITANCE
DESCRIPTIO N
CONDITION S
Input Capacitance
TA = 25oC; f = 1 MHz
VCC = 3.3V
Input/Output Capacitance (DQ)
January 22, 199 9
Rev. 1/99
SYMBO L
MAX
UNITS
NOTE S
CI
6
pF
4
CI/O
8
pF
4
4
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
GALVANTECH,
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 3.3V +0.3V)
DESCRIPTIO N
- 10
- 12
MAX
MIN
- 15
SYM
MIN
MAX
MIN
MAX
UNITS NOTES
READ cycle time
tRC
10
Address access time
tAA
10
12
15
ns
tACE
10
12
15
ns
READ Cycle
Chip Enable access time
12
15
tOH
3
3
3
Chip Enable to output in Low-Z
tLZCE
3
4
4
Chip disable to output in High-Z
tHZCE
Output hold from address change
Output Enable access time
5
tAOE
Output Enable to output in Low-Z
tLZOE
Output Enable to output in High-Z
tHZOE
Chip Enable to power-up time
tPU
Chip disable to power-down time
tPD
6
5
0
6
0
ns
ns
4, 7
7
ns
4, 6, 7
7
ns
0
5
0
ns
6
0
ns
7
0
10
12
15
ns
4, 6
ns
4
ns
4
WRITE Cycle
WRITE cycle time
tWC
10
12
15
ns
Chip Enable to end of write
tCW
8
8
9
ns
Address valid to end of write, with OE#
HIGH
tAW
8
8
9
ns
Address setup time
tAS
0
0
0
ns
Address hold from end of write
tAH
0
0
0
ns
WRITE pulse width
tWP2
10
10
11
ns
WRITE pulse width, with OE# HIGH
tWP1
8
8
9
ns
Data setup time
tDS
5
6
7
ns
Data hold time
tDH
0
0
0
ns
Write disable to output in Low-Z
tLZWE
3
4
5
Write Enable to output in High-Z
tHZWE
January 22, 199 9
Rev. 1/99
5
6
5
7
ns
4, 7
ns
4, 6, 7
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
GALVANTECH,
OUTPUT LOADS
AC TEST CONDITIONS
Input pulse levels
DQ
0V to 3.0V
Input rise and fall times
1.5ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
Z0 = 50Ω
50Ω
30 pF
Vt = 1.5V
Fig. 1 OUTPUT LOAD EQUIVALENT
See Figures 1 and 2
3.3v
317Ω
DQ
351Ω
5 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
8.
WE# is HIGH for READ cycle.
1.
All voltages referenced to VSS (GND).
9.
2.
Overshoot:
Undershoot:
Device is continuously selected. Chip enable and output enables
are held in their active state.
VIH ≤ +6.0V for t ≤ tRC /2.
VIL ≤ -2.0V for t ≤ tRC /2
3.
Icc is given with no output current. Icc increases with greater
output loading and faster cycle times.
4.
This parameter is sampled.
5.
Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
6.
Output loading is specified with CL=5pF as in Fig. 2. Transition
is measured +500mV from steady state voltage.
7.
At any given temperature and voltage condition, tHZCE is less
than tLZCE and tHZWE is less than tLZWE.
January 22, 199 9
Rev. 1/99
10. Address valid prior to, or coincident with, latest occurring chip
enable.
11. tRC = Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a
WRITE cycle.
13. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1.
14. Typical values are measured at 3.3V, 25oC and 20ns cycle time.
6
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
GALVANTECH,
READ CYCLE NO. 1(8, 9)
t
ADDR
VALID
t
t
Q
RC
AA
OH
DATA VALID
PREVIOUS DATA VALID
READ CYCLE NO. 2(7, 8, 10, 12)
tRC
CE#
tAOE
tLZOE
OE#
tHZCE
tACE
tHZOE
tLZCE
Q
HIGH Z
DATA VALID
DON'T CARE
UNDEFINED
January 22, 199 9
Rev. 1/99
7
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GALVANTECH,
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
WRITE CYCLE NO. 1(7, 12, 13)
(Write Enable Controlled with Output Enable OE# active LOW)
)
t
WC
ADDR
tAW
tAH
tCW
CE#
tWP2
tAS
WE#
tDS
D
tDH
DATA VALID
tHZWE
tLZWE
Q
HIGH Z
WRITE CYCLE NO. 2(12, 13)
(Write Enable Controlled with Output Enable OE# inactive HIGH
)
tWC
ADDR
tAW
tAH
tCW
CE#
tWP1
tAS
WE#
tDS
D
Q
tDH
DATA VALID
HIGH Z
DON'T CARE
UNDEFINED
January 22, 199 9
Rev. 1/99
8
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
GALVANTECH,
WRITE CYCLE NO. 3(12, 13)
(Chip Enable Controlled
)
t
WC
ADDR
t
t
AW
tAS
AH
tCW
CE#
tWP1
WE#
tDH
tDS
D
Q
DATA VALID
HIGH Z
DON'T CARE
Note: CE# goes to LOW means CEA# or CEB# goes to LOW, namely, CE#=CEA#*CEB#
.
January 22, 199 9
Rev. 1/99
9
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
GALVANTECH,
Package Dimension s
44-pin 400 Mil Plastic TSOP (TS)
.741 (18.81)
.721 (18.31)
.402 (10.21)
.398 (10.11)
PIN #1 INDEX
.467 (11.86)
.459 (11.66)
.0315 (0.80) TYP
.007 (0.18)
.005 (0.12)
SEATING
PLANE
.018 (0.45)
.010 (0.25)
Note: All dimensions in inches (millimeters)
January 22, 199 9
Rev. 1/99
MAX
MIN
.047 (1.20)
MAX
.032 (0.80)
.024 (0.60)
.016 (0.40)
.008 (0.20)
.002 (0.05)
or typical, max where noted.
10
Galvantech, Inc. reserves the right to change products or specifications without notice
.
GALVANTECH,
GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
44-Pin TQFP Package Dimension s
12.00 + 0.15
10.00 + 0.10
8.00 Typ.
1.00 Typ.
12.00 + 0.15
10.00 + 0.10
8.00 Typ.
Pin 1
1.65 Max
1.40 + 0.05
0.37 Typ.
0.80 Typ.
0.60 + 0.15
Note: All dimensions in Millimeters
Ordering Information
GVT 73128S16 XX - XX X X
Galvantech Prefix
Temperature (Blank = Commercial)
Part Number
Power (Blank= Standard)
Speed (10=10ns, 12=12ns, 15= 15ns)
Package (T = 44 PIN TQFP,
TS = TSOP TYPE II)
January 22, 199 9
Rev. 1/99
11
Galvantech, Inc. reserves the right to change products or specifications without notice
.