54ABT16646 16-Bit Transceivers and Registers with TRI-STATE ® Outputs General Description Features The ’ABT16646 consists of bus transceiver circuits with TRI-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. n Independent registers for A and B buses n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9450202 Ordering Code Military Package Package Description Number 54ABT16646W-QML WA56A 56-Lead Cerpack Logic Symbol Pin Names A0–A15 Description Data Register A Inputs/ TRI-STATE Outputs B0–B15 Data Register B Inputs/ TRI-STATE Outputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OEn Output Enable Input DIR Direction Control Input DS100226-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS100226 www.national.com 54ABT16646 16-Bit Transceivers and Registers with TRI-STATE Outputs July 1998 54ABT16646 Connection Diagram Pin Assignment for Cerpack DS100226-2 Storage from Bus to Register Real Time Transfer A-Bus to B-Bus DS100226-3 DS100226-5 FIGURE 1. FIGURE 3. Real Time Transfer B-Bus to A-Bus Transfer from Register to Bus DS100226-4 DS100226-6 FIGURE 2. www.national.com FIGURE 4. 2 Inputs Data I/O (Note 1) Output Operation Mode OE1 DIR1 CPAB1 CPBA1 SAB1 SBA1 H X H or L H or L X X H X N X X X H X X N X X Clock Bn Data Into B Register L H X X L X An to Bn — Real Time (Transparent Mode) L H N X L X L H H or L X H X A Register to Bn (Stored Mode) L H N X H X Clock An Data into A Register and Output to Bn L L X X X L L L X N X L L L X H or L X H B Register to An (Stored Mode) L L X N X H Clock Bn into B Register and Output to An H = HIGH Voltage Level L = LOW Voltage Level A0–7 B0–7 Input Input Isolation Input Output Clock An Data into A Register Clock An Data to A Register Bn to An — Real Time (Transparent Mode) Output Input Clock Bn Data into B Register X = Immaterial N = LOW-to-HIGH Transition. Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control pins. 3 www.national.com 54ABT16646 Function Table DS100226-7 54ABT16646 Logic Diagram www.national.com 4 Over Voltage Latchup (I/O) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current −65˚C to +150˚C −55˚C to +125˚C Recommended Operating Conditions −55˚C to +175˚C Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −0.5V to +5.5V −0.5V to VCC 10V −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100 mV/ns Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. twice the rated IOL (mA) −500 mA Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter ABT16646 Min Typ Units VCC Conditions Max VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage 54ABT 2.5 54ABT 2.0 VOL Output LOW Voltage 54ABT VID Input Leakage Test IIH Input HIGH Current IBVI Input HIGH Current 2.0 V Recognized HIGH Signal Recognized LOW Signal Min IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) IOH = −24 mA, (An, Bn) 0.55 V Min IOL = 48 mA, (An, Bn) V 0.0 IID = 1.9 µA, (Non-I/O Pins) 5 µA Max VIN = 2.7V (Non-I/O Pins) (Note 5) 7 µA Max VIN = 7.0V (Non-I/O Pins) 100 µA Max VIN = 5.5V (An, Bn) VIN = 0.5V (Non-I/O Pins) (Note 5) 4.75 All Other Pins Grounded VIN = VCC (Non-I/O Pins) Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) IIL Input LOW Current −5 µA Max IIH + IOZH Output Leakage Current 50 µA 0V–5.5V IIL + IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX IZZ VIN = 0.0V (Non-I/O Pins) VOUT = 2.7V (An, Bn); OE = 2.0V −50 µA 0V–5.5V −275 mA Max VOUT = 0V (An, Bn) Output HIGH Leakage Current 50 µA Max VOUT = VCC (An, Bn) Bus Drainage Test 100 µA 0.0V VOUT = 5.5V (An, Bn); ICCH Power Supply Current 2.0 mA Max All Outputs HIGH ICCL Power Supply Current 60 mA Max All Outputs LOW ICCZ Power Supply Current 2.0 mA Max Outputs TRI-STATE; All Others GND ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V ICCD Dynamic ICC −100 VOUT = 0.5V (An, Bn); OE = 2.0V All Others GND All Other Outputs at VCC or GND (Note 5) No Load Outputs Open 0.23 mA/MHz Max OE, DIR, and SEL = GND, Non-I/O = GND or VCC (Note 4) One Bit toggling, 50% duty cycle 5 www.national.com 54ABT16646 Absolute Maximum Ratings (Note 2) 54ABT16646 DC Electrical Characteristics (Continued) Note 4: For 8-bit toggling, ICCD < 1.4 mA/MHz. Note 5: Guaranteed but not tested. Symbol Parameter Min Max Units Conditions VCC CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 1.0 V 5.0 TA = 25˚C (Note 6) VOLV Quiet Output Minimum Dynamic VOL −1.5 V 5.0 TA = 25˚C (Note 6) Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. AC Electrical Characteristics 54ABT TA = −55˚C to +125˚C Symbol Parameter VCC = 4.5V–5.5V Units CL = 50 pF Min Max fmax Max Clock Frequency 125 tPLH Propagation Delay 1.0 tPHL Clock to Bus 1.0 7.7 tPLH Propagation Delay 1.0 5.8 tPHL Bus to Bus 1.0 7.0 tPLH Propagation Delay 1.0 7.1 tPHL SBAn or SABn to An to Bn 1.0 7.2 tPZH Enable Time 1.0 6.4 tPZL OEn to An or Bn 1.0 6.5 tPHZ Disable Time 1.0 7.6 tPLZ OEn to An or Bn 1.0 6.5 tPZH Enable Time 1.0 6.4 tPZL DIRn to An or Bn 1.0 6.7 tPHZ Disable Time 1.0 8.1 tPLZ DIRn to An or Bn 1.0 7.1 MHz 6.9 ns ns ns ns ns ns ns AC Operating Requirements 54ABT TA = −55˚C to +125˚C Symbol Parameter VCC = 4.5V–5.5V Units CL = 50 pF Min tS(H) Setup Time, HIGH tS(L) or LOW Bus to Clock tH(H) Hold Time, HIGH tH(L) or LOW Bus to Clock tW(H) Pulse Width, tW(L) HIGH or LOW Max 4.0 ns 0.5 ns 4.3 ns Capacitance Symbol Parameter Typ Units Conditions TA = 25˚C CIN Input Capacitance 5 pF VCC = 0V (non I/O pins) CI/O (Note 7) Output Capacitance 11 pF VCC = 5.0V (An, Bn) www.national.com 6 54ABT16646 Capacitance (Continued) Note 7: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012. AC Loading DS100226-9 *Includes jig and probe capacitance FIGURE 5. Standard AC Test Load DS100226-12 FIGURE 9. Propagation Delay, Pulse Width Waveforms DS100226-10 FIGURE 6. VM = 1.5V Input Pulse Requirements DS100226-13 FIGURE 10. TRI-STATE Output HIGH and LOW Enable and Disable Times Amplitude Rep. Rate tw tr tf 3V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 7. Test Input Signal Requirements DS100226-14 FIGURE 11. Setup Time, Hold Time and Recovery Time Waveforms DS100226-11 FIGURE 8. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 7 www.national.com 54ABT16646 16-Bit Transceivers and Registers with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Cerpack NS Package Number WA56A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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