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Application Notes Hitachi Single-Chip Microcomputer Technical Questions and Answers H8/500 CPU How to Use Microcomputer Technical Questions and Answers Technical Questions and Answers has been created by arranging technical questions actually asked by users of Hitachi microcomputers in a question-and-answer format. It should be read for technical reference in conjunction with the User’s Manual. Technical Questions and Answers can be read before beginning a microcomputer application design project to gain a more thorough understanding of the microcomputer, or during the design process to check up on difficult points. Contents Q&A No. Page Registers (1) Register contents after power-up reset QA8500 - 001B (2) Page registers in single-chip mode and expanded minimum modes QA8500 - 002B (3) DP contents in unconditional jump within page QA8500 - 036A 1 2 3 Interrupts (1) (2) (3) (4) (5) (6) (7) (8) (9) Interrupt sampling and acceptance Holding of disabled external interrupts Disabling of invalid instruction exceptions Interrupt contention while waiting for instruction execution to end Time of clearing of IRQn interrupt request signal Requirements for enabling interrupts Maximum wait after BREQ Clearing of interrupt request enable bits and pending interrupts Acceptance of NMI during NMI handling QA8500 - 004B QA8500 - 006B QA8500 - 008A QA8500 - 028A QA8500 - 030A QA8500 - 031A QA8500 - 032A QA8500 - 034A QA8500 - 035A 4 5 6 7 9 11 12 13 14 QA8500 - 009B QA8500 - 010B QA8500 - 037A 15 17 18 QA8500 - 011B QA8500 - 013B QA8500 - 014B QA8500 - 016B QA8500 - 019B QA8500 - 020B QA8500 - 021B QA8500 - 027A 19 20 21 22 23 24 25 26 QA8500 - 023B 27 QA8500 - 033A 28 QA8500 - 029A 29 Reset (1) NMI sampling and acceptance immediately after a reset (2) Stack pointer initialization immediately after a reset (3) Pin states at power-up reset Power-down state (1) (2) (3) (4) (5) (6) (7) (8) Hardware standby mode entry timing Instruction execution at changeover to hardware standby mode Mode pins in hardware standby mode Recovery from hardware standby mode Notes on entering sleep mode Interrupts during fetching and execution of SLEEP instruction Sampling and acceptance of interrupts during sleep mode Execution time for entering software standby mode Instructions (1) BRN instruction Software (1) Reserved addresses in interrupt vector area Miscellaneous (1) Access to on-chip registers while bus is released 4 Technical Question and Answer Product H8/500 CPU Q&A No. Topic Register contents after power-up reset QA8500 - 001B Question 1. What are the CPU register contents after a power-up reset? ❍ Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. In minimum mode, the program counter is loaded from the vector table. The interrupt mask bits (I2, I1, I0) in the status register (SR) are set to 1, and the trace bit (T) is cleared to 0. Registers R0 to R7, the base register (BR), and the other SR bits have undetermined values. In maximum mode the code page register (CP) is loaded from the vector table. Other page registers have undetermined values. Registers other than the page registers are the same as in minimum mode. Additional Information 1 Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 002B Topic Page registers in single-chip mode and expanded minimum modes Question 1. Can the DP, EP, and TP page registers be used as data registers in the single-chip mode and expanded minimum modes? ❍ Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. Yes, but since the page registers are control registers, they can only be accessed by system control instructions (LDC, STC). Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 2 Technical Question and Answer Product H8/500 CPU Q&A No. Topic DP contents in unconditional jump within page QA8500 - 036A Question 1. If the JMP @R0 unconditional in-page jump instruction is executed in expanded maximum mode, are the data page (DP) register contents used in calculating the effective address? ❍ Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. The DP contents are not used in calculating the effective address of an unconditional jump within the same page. If the JMP @R0 instruction is executed to jump within the same page, the R0 contents are loaded into the program counter (PC), but the code page (CP) register value does not change. The DP contents are therefore ignored. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 3 Technical Question and Answer Product H8/500 CPU Topic Interrupt sampling and acceptance Q&A No. QA8500 - 004B Question 1. When are external interrupts (NMI, IRQn) sampled? Classification—H8/500 Registers Read timing Write timing ❍ Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. Level-sensitive interrupts (IRQ0) are sampled on the rising edge of the system clock. Edge-sensitive interrupts (external interrupts other than IRQ0) are sampled on the falling edge of the system clock. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 4 Technical Question and Answer Product H8/500 CPU Q&A No. Topic Holding of disabled external interrupts QA8500 - 006B Question 1. In the following two cases, are external interrupts (IRQn) held pending? (1) IRQn enable bit is cleared to 0 in on-chip register field (2) IRQn interrupt priority level ≤ interrupt mask level set in status register (SR) Classification—H8/500 Registers Read timing Write timing ❍ Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. (1) In this state, the interrupt request signal is not sampled and the interrupt is not held pending. Interrupt requests made in this state will be ignored even if the IRQn enable bit is later set to 1. (2) An interrupt that is requested in this state is held pending in the CPU’s interrupt controller. If the interrupt request mask level is later reduced to a value lower than the external (IRQn) interrupt priority level, the interrupt will be accepted. IRQ0 is level-sensitive, however, so it is not held pending. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information The interrupt request mask level is set in bits I2 to I0 in the status register (SR). 5 Technical Question and Answer Product H8/500 CPU Q&A No. Topic Disabling of invalid instruction exceptions QA8500 - 008A Classification—H8/500 Registers Can exception handling of invalid instructions be disabled? Read timing How does the exception handling routine terminate? Write timing ❍ Interrupts Reset External expansion Power-down state Question 1. Instructions Software Development tools Miscellaneous Related Manuals Manual Title: Answer 1. No, it cannot be disabled. The invalid instruction exception handler cannot be terminated by returning with an RTE instruction. Use some Other Technical other software technique, such as jumping to the reset Documentation routine. Document Name: Related Microcomputer Technical Q&A Title: Additional Information 6 Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 028A – 1 Topic Interrupt contention while waiting for instruction execution to end Question 1. Suppose an interrupt occurs during execution of an instruction, then during the waiting state before the instruction ends another, higher-priority interrupt occurs. Which interrupt does the CPU accept? Classification—H8/500 Registers Read timing Write timing ❍ Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. The CPU accepts the interrupt with the highest priority level four states before the time of acceptance. (See the next page.) The interrupt mask level in bits I2 to I0 is not changed until the status register (SR) has been saved onto the stack. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 7 8 (A) (B) 4ø (C) SR SP-4 H8/500 CPU Topic Interrupt contention while waiting for instruction execution to end Note: Conditions: minimum mode with the program and stack areas both in on-chip memory and interrupt handler starting at an even address. Interrupt vector Priority level of accepted interrupt (D) Vector Vector address Product Q&A No. Stack I bits Level before interrupt in SR PC SP-2 (A) Interrupt source 1 is input but not accepted because of instruction execution. Waiting for interrupt Internal (B) Interrupt sources 1 priority decision and cycle and 2 contend. end of instruction Interrupt source 2 is selected. (C) The instruction being Interrupt accepted executed ends. The CPU accepts interrupt source 2. (D) The I bits in the status register are changed to level 7. Interrupt source 2 (priority level = 7) Interrupt source 1 (priority level = 6) Internal data bus (16 bits) Internal address bus ø Technical Question and Answer QA8500 - 028A – 2 Answer Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 030A – 1 Topic Time of clearing of IRQn interrupt request signal Question 1. There are no interrupt request flags for edge-sensitive external interrupts (IRQn). When are these requests cleared? Classification—H8/500 Registers Read timing Write timing ❍ Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. The interrupt request is cleared during the internal cycle in which the interrupt is accepted, as indicated by the arrow in the diagram on the next page. If the same interrupt request signal (IRQn) occurs after this time, it will be latched again. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 9 Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 030A – 2 Topic Timing of clearing of IRQn interrupt request signal Answer ø Internal address bus (1) (1) (1) SP-2 IRQ n (edge-sensed) Internal data bus (16 bits) (2) (2) (2) PC Internal read signal Internal write signal Internal cycle Interrupt accepted (1) Instruction prefetch address (2) Instruction code Taken from the User’s Manual 10 Technical Question and Answer Product H8/500 CPU Q&A No. Topic Requirements for enabling interrupts QA8500 - 031A Question 1. Why do we fail to get an interrupt even though the interrupt request enable bit (IRQnE) is set to 1 and the interrupt request signal (IRQn) is asserted? Classification—H8/500 Registers Read timing Write timing ❍ Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. To enable interrupts to be accepted, software must: (1) Set the interrupt enable bits for the desired interrupt sources to 1. (2) Set values in the interrupt priority registers (IPRs). (3) Set the desired interrupt request mask level in bits I2 to I0 in the status register (SR). Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Check the above points. Related Microcomputer Technical Q&A Title: Additional Information A reset initializes all IPR values to 0 and sets bits I2 to I0 all to 1, masking all interrupts except NMI. 11 Technical Question and Answer Product H8/500 CPU Topic Maximum wait after BREQ Q&A No. QA8500 - 032A Question 1. What is the maximum waiting time from input of an external bus request signal (BREQ) until the CPU replies (BACK)? Classification—H8/500 Registers Read timing Write timing ❍ Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. The maximum waiting time is 10 to 17 states. This occurs if the CPU started executing the MOVFPE or MOVTPE instruction (which transfers data in synchronization with the E clock) just before BREQ was asserted. Because MOVTPE and MOVFPE execute in synchronization with the E clock, the number of states varies depending on the timing of the start of execution. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 12 Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 034A Topic Clearing of interrupt request enable bits and pending interrupts Question 1. While an IRQn interrupt is being held pending because its priority is equal to or less than the interrupt request mask level in the status register (SR), does clearing the IRQn enable bit (IRQnE) also clear the IRQn interrupt request? Classification—H8/500 Registers Read timing Write timing ❍ Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. When an IRQn interrupt request is held pending because of the interrupt request mask level (I2 to I0), the request remains pending even if IRQnE is cleared to 0. The IRQn interrupt will be accepted later when the interrupt request mask level is reduced to a value less than the IRQn priority level. Interrupt request mask level Level 4 1 IRQ n E Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Level 2 0 Related Microcomputer Technical Q&A Title: IRQ n (priority level 3) Interrupt request Interrupt requested Additional Information IRQ0 is level-sensitive, so it is not held pending, regardless of whether IRQ0E is set or cleared. 13 Technical Question and Answer Product H8/500 CPU Q&A No. Topic Acceptance of NMI during NMI handling QA8500 - 035A Question 1. NMI has the highest priority and is always accepted. During the NMI interrupt handling routine, if another NMI interrupt occurs will it also be accepted? Classification—H8/500 Registers Read timing Write timing ❍ Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. If another NMI request is made during the NMI interrupt handling routine, the second request will also be accepted. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 14 Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 009B – 1 Topic NMI sampling and acceptance immediately after a reset Question 1. When is the NMI signal first sampled after a reset? Classification—H8/500 Registers Read timing Write timing Interrupts ❍ Reset External expansion Power-down state Instructions Software Development tools Answer 1. Sampling of the NMI signal starts from the first falling edge of the system clock at which the reset signal is high. The NMI interrupt becomes acceptable when the first instruction has been executed after the chip comes out of reset. (See next page) Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information The reset and NMI signals are both sampled on the falling edge of the system clock. 15 Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 009B – 2 Topic NMI sampling and acceptance immediately after a reset Question [Example] ø t ress t ress High reset signal sampled RES t resw NMI not sampled NMI sampled 16 Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 010B Topic Stack pointer initialization immediately after a reset Question 1. Why is it necessary to initialize the stack pointer immediately after a reset? Classification—H8/500 Registers Read timing Write timing Interrupts ❍ Reset External expansion Power-down state Instructions Software Development tools Answer 1. If the NMI request signal is active when the chip comes out of reset, the NMI interrupt will be accepted as soon as the first instruction has been executed. To prevent program crashes, you should therefore initialize the stack pointer immediately after the reset. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 17 Technical Question and Answer Product H8/500 CPU Topic Pin states at power-up reset Q&A No. QA8500 - 037A Question 1. What needs to be noted about pin states at a power-up reset? Classification—H8/500 Registers Read timing Write timing Interrupts ❍ Reset External expansion Power-down state Instructions Software Development tools Answer 1. At a power-up reset, the mode pins (MD2 to MD0) must be tied to the desired mode setting and the STBY pin must be held high. Output from the ø and E pins is unpredictable until the clock oscillator settles into steady oscillation. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information When using a microcontroller that multiplexes the ø and E pins with general-purpose input ports, connect a resistor with a resistance of several kilohms in series with these pins. 18 Technical Question and Answer Product H8/500 CPU Q&A No. Topic Hardware standby mode entry timing QA8500 - 011B Question 1. Are there any restrictions on times t1 and t2 in the diagram below for entering hardware standby mode? STBY t1 t2 t OSC1 Instructions Software Development tools RES Miscellaneous Related Manuals Manual Title: Answer 1. Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion ❍ Power-down state The following restrictions apply. (1) To hold RAM contents, t1 must be at least 10 system clock cycles. The minimum value of t2 is 0 ns. (2) When it is not necessary to hold RAM contents, there Documentation Document Name: is no restriction on t1 and t2. STBY t1 t2 t OSC RES Additional Information 19 Other Technical Related Microcomputer Technical Q&A Title: Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 013B Topic Instruction execution at changeover to hardware standby mode Question 1. When a low STBY input drives the chip into hardware standby mode, what happens to the instruction currently being executed? Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion ❍ Power-down state Instructions Software Development tools Answer 1. The instruction being executed is aborted, without being completed. Normal execution of the instruction is not assured. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 20 Technical Question and Answer Product H8/500 CPU Q&A No. Topic Mode pins in hardware standby mode QA8500 - 014B Question 1. What happens if the states of the mode lines (MD2 to MD0) are changed during hardware standby mode? Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion ❍ Power-down state Instructions Software Development tools Answer 1. Hardware standby mode will not operate correctly. Do not change the state of the mode lines during hardware standby mode. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 21 Technical Question and Answer Product H8/500 CPU Q&A No. Topic Recovery from hardware standby mode QA8500 - 016B Question 1. The chip must be recovered from hardware standby mode by holding RES low, then driving STBY high. How long before STBY goes high does RES have to go low? Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion ❍ Power-down state Instructions Software Development tools Answer 1. To recover from hardware standby mode, drive RES low at least 100 ns before driving STBY high. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: STBY RES 100 ns t OSC Additional Information 22 Related Microcomputer Technical Q&A Title: Technical Question and Answer Product H8/500 CPU Q&A No. Topic Notes on entering sleep mode QA8500 - 019B Question 1. Are there any points to note about entering sleep mode? Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion ❍ Power-down state Instructions Software Development tools Answer 1. The points listed below should be noted, depending on the method used to recover from sleep mode. Miscellaneous Related Manuals Manual Title: Recovery Method NMI Interrupt IRQn Interrupt Clear all interrupt enable bits to 0, or set bits I2 to I0 in SR all to 1. Set bits I2 to I0 in SR to a level lower than the priority level of the interrupt used for recovery, clear interrupt enable bits to 0 except for interrupts used for recovery, and make sure NMI is not requested. Additional Information 23 Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 020B Topic Interrupts during fetching and execution of SLEEP instruction Question 1. What happens if an interrupt is accepted while the SLEEP instruction is being executed? Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion ❍ Power-down state Instructions Software Development tools Answer 1. Sleep mode is released to handle the interrupt. At the end of interrupt handling, the next instruction after the SLEEP instruction is executed. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 24 Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 021B Topic Sampling and acceptance of interrupts during sleep mode Question 1. When are external interrupts sampled during sleep mode? 2. If an interrupt is sampled, how many system clock cycles later does the chip wake up? Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion ❍ Power-down state Instructions Software Development tools Answer 1. 2. Level-sensitive interrupts (IRQ0) are sampled on the rising edge of the system clock and edge-sensitive interrupts (external interrupts other than IRQ0) are sampled on the falling edge of the system clock, just as in active mode. The chip exits sleep mode six system clock cycles after the interrupt is sampled. Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 25 Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 027A Topic Execution time for entering software standby mode Question 1. How many states does it take to enter software standby mode by executing the SLEEP instruction? Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion ❍ Power-down state Instructions Software Development tools Miscellaneous Related Manuals Manual Title: Answer 1. Two states. Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 26 Technical Question and Answer Product H8/500 CPU Topic BRN instruction Q&A No. QA8500 - 023B Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion Power-down state Question 1. What sort of instruction is BRN (or BF)? ❍ Answer 1. BRN is similar to a NOP instruction, but it has a different byte length and executes in a different number of states. See below. BRN NOP Byte Length Number of States Required for Execution d: 8 2 3* d: 16 3 3* 1 2* * When instruction is fetched from on-chip ROM BRN has the same byte length as Bcc, for example, which makes it useful in debugging. Additional Information 27 Instructions Software Development tools Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Technical Question and Answer Product H8/500 CPU Q&A No. Topic Reserved addresses in interrupt vector area QA8500 - 033A Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion Power-down state Question 1. Can the reserved addresses in the interrupt vector area be used to store program code? ❍ Miscellaneous Related Manuals Manual Title: Answer 1. Instructions Software Development tools Yes, they can. Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 28 Technical Question and Answer Product H8/500 CPU Q&A No. QA8500 - 029A Topic Access to on-chip registers while bus is released Question 1. When the H8/500 CPU releases the bus to an external device, can the external device (bus master) access the H8/500’s on-chip registers? Classification—H8/500 Registers Read timing Write timing Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. No. On-chip registers cannot be accessed externally under any circumstances. ❍ Miscellaneous Related Manuals Manual Title: Other Technical Documentation Document Name: Related Microcomputer Technical Q&A Title: Additional Information 29