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Hitachi Microcomputer Technical Q & A H8/300H Series Application Notes Hitachi Micro Systems, Incorporated 1994 ADE-502-038 When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Introduction The H8/300H series microcontrollers are high-performance Hitachi-original 16-bit microcontrollers that build in the optimum peripheral equipment for industrial machinery around high-speed H8/300 CPUs that have architecture upwardly compatible with H8/300 CPUs. The microcontroller puts a CPU, RAM, direct memory access controller (DMAC), bus controller, timers, and a serial communication interface (SCI) on a single chip, making it suitable for a wide range of applications from small to large systems. This microcontroller technical Q&A covers the H8/3001, H8/3002, H8/3003, H8/3042 series, H8/3032 series, and H8/3048 series. Table 0-1 H8/300H Series Item H8/3003 H8/3002 H8/3001 H8/3042 H8/3041 H8/3040 CPU H8/300H H8/300H H8/300H H8/300H H8/300H H8/300H Mask (byte) — — — 64 k 48 k 32 k ZTAT * — — — Yes — — 512 512 512 2k 2k 2k Memory ROM RAM (byte) Address space (byte) 16 M 16 M 16 M 16 M 16 M 16 M External data bus width (bit) 8/16 8/16 8/16 8/16 8/16 8/16 Timers ITU (integrated timer unit) 5 ch 5 ch 5 ch 5 ch 5 ch 5 ch Watchdog timer 1 ch 1 ch — 1 ch 1 ch 1 ch DMA controller Memory ↔ I/O 8 ch 4 ch — 4 ch 4 ch 4 ch Memory ↔ memory 4 ch 2 ch — 2 ch 2 ch 2 ch Programmable timing pattern controller (TPC) 16 bits 16 bits 12 bits 16 bits 16 bits 16 bits SCI (Asynchronous/clocksynchronous) 2 ch 2 ch 1 ch 2 ch 2 ch 2 ch A/D converter Resolution 10 bits 10 bits 10 bits 10 bits 10 bits 10 bits Input channel 8 ch 8 ch 4 ch 8 ch 8 ch 8 ch External trigger input Yes Yes Yes Yes Yes Yes Resolution — — — 8 bits 8 bits 8 bits Input channel D/A converter — — — 2 ch 2 ch 2 ch Refresh controller On-chip On-chip — On-chip On-chip On-chip Interrupts External interrupts 9 7 4 7 7 7 Internal Interrupts 34 30 20 30 30 30 I/O port 58 46 32 78 78 78 Package QFP-112 QFP-100 TQFP-100 QFP-80 TQFP-80 QFP-100 TQFP-100 QFP-100 TQFP-100 QFP-100 TQFP-100 Miscellaneous — — — — — — Note: ZTAT (Zero turn around time) is a trademark of Hitachi Ltd. Table I-1 H8/300H Series (cont) Item CPU H8/3048 H8/3047 H8/3044 H8/3032 H8/3031 H8/3030 H8/300H H8/300H H8/300H H8/300H H8/300H H8/300H Mask (byte) 128 k 96 k 32 k 64 k 32 k 16 k ZTAT * Yes — — Yes — — 4k 4k 2k 2k 1k 512 Address space (byte) 16 M 16 M 16 M 1M 1M 1M External data bus width (bit) 8/16 8/16 8/16 8 8 8 Timers ITU (integrated timer unit) 5 ch 5 ch 5 ch 5 ch 5 ch 5 ch Watchdog timer 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch DMA controller Memory ↔ I/O 4 ch 4 ch 4 ch — — — Memory ↔ memory 2 ch 2 ch 2 ch — — — Programmable timing pattern controller (TPC) 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits SCI (Asynchronous/clocksynchronous) 2 ch 2 ch 2 ch 1 ch 1 ch 1 ch A/D converter Resolution 10 bits 10 bits 10 bits 10 bits 10 bits 10 bits Input channel 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch Memory ROM RAM (byte) D/A converter External trigger input Yes Yes Yes Yes Yes Yes Resolution 8 bits 8 bits 8 bits — — — Input channel — 2 ch 2 ch 2 ch — — Refresh controller On-chip On-chip On-chip — — — Interrupts 7 7 7 6 6 6 External interrupts 30 30 30 21 21 21 I/O port Internal Interrupts 78 78 78 63 63 63 Package QFP-100 TQFP-100 QFP-100 TQFP-100 QFP-100 TQFP-100 QFP-80 TQFP-80 QFP-80 TQFP-80 QFP-80 TQFP-80 Miscellaneous Built-in smart card interface, improved low-voltage, low-power performance — — — For Users of the Microcontroller Technical Q & A This Microcontroller Technical Q & A was compiled from answers to technical questions we received from Hitachi microcontroller users. We hope that it will be a useful addition to the H8/300H series user manuals. Before starting design of products that use microcontrollers, read through the manual to deepen your understanding of microcontroller products and re-familiarize yourself with those areas of difficulty at the design stage. Contents Q&A No. Page Registers (1) The Difference Between the CCR’s V Flag and C Flag (2) The Relationship Between Data Size and V Flag Changes (3) Use of General Registers QA300H-001A QA300H-002A QA300H-003A 1 2 3 Bus Controller (1) Bus State While the CPU Is Operating (2) Bus Modes (3) Setting the Bus Controller in Area 7 (4) External Installation of RAM to 8-Bit Bus Areas (5) Changing the Number of Wait States Inserted Per Area (6) Receiving BREQ in Power-Down Mode (7) Maximum Wait Time After BREQ Input QA300H-004 QA300H-005A QA300H-006A QA300H-007A QA300H-008A QA300H-009A QA300H-010A 4 5 6 7 8 10 11 QA300H-011A QA300H-012A QA300H-013A QA300H-014A QA300H-015A QA300H-016A QA300H-017A QA300H-018A 12 13 14 15 16 17 18 20 QA300H-019A QA300H-020A 21 22 QA300H-021A QA300H-022A QA300H-023A QA300H-024A QA300H-025A QA300H-026A 23 24 25 26 27 28 QA300H-027A QA300H-028A QA300H-029A QA300H-030A QA300H-031A QA300H-032A 29 30 31 32 33 34 Section 1 CPU Interrupts (1) Interrupt Sampling (2) Holding External Interrupts (3) Receiving NMIs During NMI Processing (4) Edge Rise and Fall Times for Interrupt Pins (5) Disable Timing for Interrupts (6) Exception Processing After a Reset (7) Using the Interrupt Controller (8) Receiving an External IRQ1 After Returning From Hardware Standby Mode (9) Interrupt Priority Within Groups (10) Interrupts When the Bus Is Released Resets (1) NMI Sampling Timing and Receiving After Reset (2) Initializing SP After Reset (3) Pin State During Power-On Reset (4) RESO Pin Output From RES Pin Input (5) Connecting RES and RESO Pins (6) Cautions for Reset Input Power-Down Mode (1) Executing Instructions When Switching to Hardware Standby Mode (2) Mode Pins During Hardware Standby Mode (3) Returning From Hardware Standby Mode (4) Interrupt Sampling and Receiving in Sleep Mode (5) Execution Time in Software Standby Mode (6) Operation When an Interrupt is Requested During Execution or While Fetching a SLEEP Instruction Q&A No. Page QA300H-033A 36 QA300H-034A QA300H-035A QA300H-036A QA300H-037A QA300H-038A 37 38 39 40 41 QA300H-039A 42 QA300H-040A QA300H-041A QA300H-042A QA300H-043A 43 44 45 46 DMA Controller (1) Receiving DMAC Startup Requests (2) Addresses During DMA Transfers (3) TEND Signal Output Timing 1 (4) TEND Signal Output Timing 2 (5) The Relationship Between the DMAC’s DTE and DTIE Bits (6) DMAC Startup (7) The DMAC and Timer Interrupts (8) Operation After a DMAC End Interrupt Is Generated 1 (9) Operation After a DMAC End Interrupt Is Generated 2 (10) DMA Transfers Started up by Serial Transfers (11) Time Until DMAC Startup by the DREQ Pin (12) Reverse Operation in the DMA Repeat Mode (13) Use of Dual-Function Pins (14) I/O Ports and the DREQ Pin QA300H-101 QA300H-102 QA300H-103 QA300H-104 QA300H-105 QA300H-106 QA300H-107 QA300H-108 QA300H-109 QA300H-110 QA300H-111 QA300H-112 QA300H-113 QA300H-114 47 49 50 51 52 53 54 55 56 57 58 59 60 61 ITU (1) (2) (3) (4) (5) (6) (7) (8) QA300H-115 QA300H-116 QA300H-117 QA300H-118 QA300H-119 QA300H-120 QA300H-121 QA300H-122 62 63 64 65 66 67 69 72 QA300H-123 73 Instructions (1) Support for the DAA (DAS) Instruction with the INC (DEC) Instruction (2) BRA and BRN Instructions (3) BRN Instruction (4) The SUBX Instruction (5) Odd Address Values During STC Instruction Execution (6) Interrupts and DMA Transfer Requests While the EEPMOV Instruction Is Executing (7) The Difference Between EEPMOV.B and EEPMOV.W Miscellaneous (1) Cautions on Stack Operation (2) On-Chip Peripheral LSI Access When the Bus Is Released (3) Areas That Can Be Used as ROM by the Vector Table (4) Pin State During the Oscillation Settling Time Section 2 On-Chip Peripherals PWM Mode and Interrupts Clearing the Counters Pulse Output From the ITU ITU Cascade Connections Setting the ITU’s PWM Output ITU Output and Port Output ITU Settings Independent Operation of TCNT4 Using Reset-Synchronized PWM Mode Watchdog Timer (1) Halting the WDT’s System Clock Q&A No. Page QA300H-124 QA300H-125 QA300H-126 QA300H-127 QA300H-128 QA300H-129 QA300H-130 QA300H-131A QA300H-132A QA300H-133 QA300H-134 QA300H-135 74 75 76 77 78 79 81 83 85 87 88 89 A/D Converter (1) Changing the A/D Mode and Channel During A/D Conversion QA300H-136 90 I/O Ports (1) Using General-Purpose Ports (2) Processing Ports When Not in Use QA300H-137 QA300H-138 91 92 Serial Communications Interface (SCI) (1) Using the RDR and TDR When the SCI Is Not Being Used (2) I/O Settings of Clock Pins for the SCI (3) Serial I/O Pin State (4) Simultaneous Transmission and Reception with the SCI (5) RDRF (6) Setting for Asynchronous Transmission (7) How Data Is Transferred to the TDR (8) Timing of Setting RDRF (9) Timing of Setting TDRE (10) SCI Reception Errors (11) Operating the SCI in External Clock Mode (12) System Clocks and SCK Phases Section 1 CPU Technical Questions and Answers Product H8/300H Q&A No. Topic The Difference Between the CCR’s V Flag and C Flag QA300H-001A Question Classification—H8/300H Since the CCR’s V flag and C flag both flag a 1 when an operation overflows, what is the difference? Software o Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The CCR’s V flag is accessed to see if an overflow has occurred in a signed operation. In figure 1.1, which is a byte-sized operation, the flag is set to 1 when the result is smaller than the negative minimum (H'80) or larger than the positive maximum (H'7F). H'80 H'00 H'7F V flag Overflow Overflow Manual Title Other Technical Documentation Document Name Figure 1.1 V Flag Operation In contrast, the CCR’s C flag is accessed to see if an overflow has occurred in an unsigned operation. In figure 1.2, which is a byte-sized operation, the flag is set to 1 when the result is smaller than the minimum (H'00) or larger than the maximum (H'FF). Related Microcomputer Technical Q&A Title H'00 H'FF C flag Overflow Overflow Figure 1.2 C Flag Operation References 1 Technical Questions and Answers Product H8/300H Q&A No. Topic The Relationship Between Data Size and V Flag Changes QA300H-002A Question Classification—H8/300H Do the changes in the CCR’s V flag vary with data size? Software o Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The CCR’s V flag changes when an overflow is detected in the result of a signed arithmetic operation. This operation is the same for all data sizes. However, the timing of the changes in the flag varies as follows: • Byte: When the value is smaller than H'80 or larger than H'7F. • Word: When the value is smaller than H'8000 or larger than H'7FFF. • Longword: When the value is smaller than H'80000000 or larger than H'7FFFFFFF. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 2 Technical Questions and Answers Product H8/300H Q&A No. Topic Use of General Registers QA300H-003A Question Classification—H8/300H Can different general registers be used as 8-bit, 16-bit, and 32-bit registers at the same time? Software o Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Yes. Registers can be set freely for use as shown in figure 1.3. E0 R0H R0L ER1 E2 R2H R2L ER3 E4 E4 E5 E5 E6 R6H Manual Title R6L Other Technical Documentation Document Name See section 2.4.2, General Registers, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A ER7 (SP) Note: ER7 is used as the SP without any special notice being given. Figure 1.3 Use of General Registers References 3 Title Technical Questions and Answers Product H8/300H Q&A No. Topic Bus State While the CPU Is Operating QA300H-004 Question 1. Classification—H8/300H Software What is the bus state during CPU internal processing? 2. What is the bus state after DREQ is received? 3. What is the bus state after BREQ is received? Registers o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Manual Title See table 1.1. Table 1.1 Bus State While the CPU Is Operating CPU Operation Address Bus Data Bus During internal CPU processing Hold High impedance After DREQ is received DMA address DMA data Other Technical Documentation After BREQ is received High impedance High impedance Document Name See figure 6.18, External Bus Release State, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 4 Technical Questions and Answers Product H8/300H Topic Bus Modes Q&A No. QA300H-005A Question Classification—H8/300H Section 6.2.1 of the H8/3003 Hardware Manual says, “When even 1 bit of the ABWCR is cleared to 0, the bus mode becomes 16 bits.” Does this mean that all areas can be accessed in 16-bit mode? Software Registers o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer No. When a given bit ADWn (bus width control for area n) of the ABWCR (bus width control register) is cleared to 0, only that area whose bit is cleared can be accessed in 16-bit mode. The manual description might better read, "When even one area is set as a 16-bit accessed space, the H8/300H CPU goes into 16-bit bus mode and D15–D0 can all be used as the data bus. This means that I/O ports that are also used as the lower data bus (D7–D0) cannot be used as general ports, even in an 8-bit access space." Manual Title Other Technical Documentation Document Name See table 6.4, Address Space and Data Bus Used, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 5 Technical Questions and Answers Product H8/300H Topic Setting the Bus Controller in Area 7 Q&A No. QA300H-006A Question Classification—H8/300H Since area 7 mixes on-chip RAM and internal I/O registers, in which areas are the bus widths and access states set by the bus controller valid? Software Registers o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer In area 7, the bus width and number of access states set by the bus controller are valid in areas other than the on-chip RAM and internal I/O registers. (The addresses of the area differ according to the product. See the manual for details.) On-chip RAM has a fixed bus width of 16-bits and a fixed number of access states of 2. The internal I/O registers can have bus widths of 8-bits or 16-bits, and have a fixed number of access states of 3. Manual Title Other Technical Documentation Document Name See figure 6.2, Access Area Map for Each Operating Mode, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References When the RAME (RAM enable) bit of the SYSCR (system control register) is cleared to 0, the on-chip RAM is not valid and the settings of area 7 are followed. The CS signal outputs low in all of area 7. 6 Technical Questions and Answers Product H8/300H Q&A No. Topic External Installation of RAM to 8-Bit Bus Areas QA300H-007A Question Classification—H8/300H When RAM is externally installed in 8-bit bus space, which signal should be used to access it, HWR or LWR? Software Registers o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Manual Title Use the HWR signal. Other Technical Documentation Document Name See table 6.4, Address Space and Data Bus Used, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 7 Technical Questions and Answers Product H8/300H Q&A No. Topic Changing the Number of Wait States Inserted Per Area QA300H-008A-1 Question 1. 2. Classification—H8/300H Software Can the wait mode be set for individual areas? Registers If not, how should the wait mode be set to change the number of access states inserted for individual areas? o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer 1. WMS (wait mode select) bits 1 and 0 of the WCR (wait control register), which set the wait mode, are common to all areas. For this reason, the wait mode cannot be set for individual areas. 2. The following areas, can, however, be mixed: • Wait disabled areas • Areas to which wait states are only inserted by the WAIT pin (pin wait mode 0) • Areas in which WC (wait count) bits 1 and 0 of the WCR are valid (programmable wait mode, pin wait mode 1, or pin autowait mode) The number of access states for individual areas can be changed by using these in combination. An example is shown below and in tables 1.2 and 1.3. Manual Title Other Technical Documentation Document Name See section 6.3.5 (5), WSC Setting Example, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References The bus width and the enabled/disabled state of WSC (wait state controller) operation can be set for individual areas. 8 Technical Questions and Answers Product H8/300H Q&A No. QA300H-008A-2 Topic Changing the Number of Wait States Inserted Per Area Answer Example: To set the following access states for the following areas: • Areas 0–1: 2 states • Area 2: 3 states • Areas 3–4: 4 states • Area 5: 5 states • Areas 6–7: 6 states Table 1.2 Changing the Number of Wait States Inserted Per Area Area Memory Map Wait States from WC Bit Enable/Disable of Wait Insertion from WAIT Pin Waits from WAIT pin Access States Area 0 2-state access space Invalid Disable — 2 Area 1 Wait-disabled area Area 2 3-state access space pin wait mode 0 Invalid Enable 0 3 Valid/1 state Enable 0 4 Enable 1 5 Enable 3 6 Area 3 Area 4 3-state access space pin wait mode 1 Area 5 Area 6 3-state access space Area 7 pin wait mode 0 Table 1.3 Invalid Register Settings Register Address Setting ASTCR (Access state control register) H'FC WCER (Wait state control enable register) H'38 0 WCR H'F9 — 7 1 0 1 1 1 1 1 0 0 1 1 1 0 0 — — — 1 0 0 7 0 7 9 0 0 0 1 Technical Questions and Answers Product H8/300H Topic Receiving BREQ in Power-Down Mode Q&A No. QA300H-009A Question 1. 2. Classification—H8/300H Software Can BREQ be received in sleep mode? Registers Can BREQ be received in hardware/software standby mode? o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Manual Title 1. Yes 2. Since both the hardware standby mode and software standby mode bring on-chip peripheral modules to a halt (including the clock), BREQ cannot be received. Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 10 Technical Questions and Answers Product H8/300H Topic Maximum Wait Time After BREQ Input Q&A No. QA300H-010A Question Classification—H8/300H Software Why does it take so long between BREQ input and BACK output? Registers o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Because the BREQ request is held in the following cases: 1. When DMAC (DMA controller) data is being transferred in burst mode or block transfer mode. 2. When waits are inserted during accesses of external addresses. Example: When an instruction with a word-size operand is executed with an 8-bit bus in pin wait mode 1: 1 bus cycle (3 states + inserted wait states + wait states inserted by pin) × 2. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 11 Technical Questions and Answers Product H8/300H Topic Interrupt Sampling Q&A No. QA300H-011A Question Classification—H8/300H Software When are external interrupts (NMI, IRQn) sampled? Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Sampling occurs at every fall of the system clock φ. Manual Title Other Technical Documentation Document Name See figure 18.17, Interrupt Input Timing, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual See figure 20.17, Interrupt Input Timing, in the following manual: • H8/3042 Hardware Manual Related Microcomputer Technical Q&A Title References 12 Technical Questions and Answers Product H8/300H Topic Holding External Interrupts Q&A No. QA300H-012A Question 1. 2. Classification—H8/300H Are the IRQn interrupt requests held if they are produced when the IRQnE (IRQ enable) bit of the IER (IRQ enable register), which controls external interrupts (IRQn), is cleared to 0? Software Registers Bus controller o Are IRQn interrupt requests held if they are produced when interrupts are masked with the I and UI bits of the CCR (condition code register)? Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer 1. 2. Yes. When the signal specified by the ISCR (IRQ sense control register) drives the IRQn pin, the IRQnF (IRQn flag) of the ISR (IRQ status register) is set to 1. This is not affected by the state of the IRQnE bit. When the IRQnE bit is set to 1 while the IRQnF is set to 1, an interrupt is requested. The IRQnF bit can be cleared with software. Yes. As in the above case, IRQnF is not affected by the state of the I and UI bits. When the IRQnE and IRQnF bits are set to 1 and the interrupt mask is cleared, the interrupt is accepted. Manual Title Other Technical Documentation Document Name See figure 5.2, IRQ Interrupt Block Diagram, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 13 Technical Questions and Answers Product H8/300H Topic Receiving NMIs During NMI Processing Q&A No. QA300H-013A Question Classification—H8/300H If the NMI has the highest priority and is always accepted, will another NMI be accepted if it is generated while the NMI interrupt processing routine is running? Software Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer If another NMI is generated while an NMI interrupt processing routine is running, that interrupt request is accepted superimposed over the first. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 14 Technical Questions and Answers Product H8/300H Q&A No. Topic Edge Rise and Fall Times for Interrupt Pins QA300H-014A Question Classification—H8/300H Software When an edge trigger is used for an external interrupt, what are the longest allowed rise and fall times of the edge? Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Make it no more than 2 states. More than this will produce the following effects: 1. Interrupts will not be accepted because the edge change is not detected. 2. More than one edge will be detected internally for each change in the external pin signal, so multiple interrupts will be requested. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 15 Technical Questions and Answers Product H8/300H Topic Disable Timing for Interrupts Q&A No. QA300H-015A Question Classification—H8/300H 1. Are interrupts disabled the instant that the peripheral module’s interrupt enable bit is cleared to 0? 2. When the interrupt enable bit of the IER (IRQ enable register) is cleared to 0, are interrupt instantly disabled? Software Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer 1. 2. Interrupts are disabled after the instruction that cleared the interrupt enable bit to 0 finishes executing. When an interrupt request is generated while the zeroing instruction is executing, that interrupt request is accepted after the instruction completes its execution. Interrupts are disabled after the instruction that cleared the interrupt enable bit to 0 finishes executing. When an interrupt request is generated while the zeroing instruction is executing, that interrupt request is not accepted after the instruction completes its execution since the request signal is cleared simultaneously with the enable bit. However, since the IRQn flag is held, the next time the interrupt enable bit is set to 1, that interrupt is accepted. Manual Title Other Technical Documentation Document Name See section 5.5.1, Interrupt Generation and Disable Contention, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title Also see section 1.3.2, Holding External Interrupts (QA300H-012A), in this manual. References 16 Technical Questions and Answers Product H8/300H Topic Exception Processing After a Reset Q&A No. QA300H-016A Question Classification—H8/300H Software Are interrupts ever generated immediately following resets? Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer No. Immediately after a reset, all interrupts, including NMIs, are disabled. However, when the first instruction of a program is executed, NMIs are accepted. Manual Title Other Technical Documentation Document Name See section 4.2.3, Interrupts After a Reset, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 17 Technical Questions and Answers Product H8/300H Q&A No. Topic Using the Interrupt Controller QA300H-017A-1 Question Classification—H8/300H Software How should the two interrupt priority levels be used to make effective use of the interrupt controller? Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer By rewriting the values set in IPRA and IPRB (interrupt priority registers A and B) for every interrupt processing routine, the interrupt priority can be changed at any time. IPRA and IPRB are 1-word registers, so they are easy to manipulate. A sample program is shown in figure 1.4. See the procedures after the figure for a more concrete example on use. Manual Title Other Technical Documentation PUSH MOV.W PUSH MOV.W MOV.W ANDC .. . POP MOV.W POP RTE R0 @IPRA, R0 R0 #NEW, R0 R0, @IPRA #H'BF, CCR .. . R0 R0, @IPRA R0 Saves content of R0 Document Name Saves IPRA value Sets the new IPRA value to NEW Clears the UI bit Reverts to the saved IPRA value Related Microcomputer Technical Q&A Title Reverts to the saved R0 value Figure 1.4 Sample Program References 18 Technical Questions and Answers Product H8/300H Q&A No. Topic Using the Interrupt Controller QA300H-017A-2 Answer 1. 2. Procedure for setting interrupt priority: a. Set the UE (user bit enable) bit of the SYSCR (system control register) to 0, the I bit (interrupt mask) of the CCR (condition code register) to 1, and the CCR’s UI (user bit/interrupt mask) bit to 0. In this state, only NMIs and priority 1 interrupt sources are accepted. b. Set the interrupt priorities for each interrupt source on the user end. c. Perform the following processing during the interrupt processing routines. Following the interrupt priorities set by the user, interrupts of priorities lower than the interrupt in question are masked by writing a 0 to the appropriate bits in IPRA and IPRB. Figure 1.5 shows the processing procedures when the interrupt priorities set by the user are as shown in table 1.4. Table 1.4 Interrupt Priorities Interrupt Source User-Set Priorities Timer 1 5 Initial IPRA, IPRB Settings Timer 2 4 1 SCI 1 3 1 Timer 3 2 1 Timer 4 1 SCI 2 0 Highest 1 1 Lowest Main routine UE = 0 SCI1 interrupt (priority 3) I=1 • I ← 1, UI ← 1 (masks interrupts UI = 0 other than NMI) • SCI1 interrupt request flag ← 0 • Masks priority 2-0 interrupts; SCI2 of IPRA and IPRB and interrupts of timers 3 and 4 ← 0 • UI ← 0 (interrupts enabled for priority 3 or higher) 1 Timer 2 interrupt (priority 4) • UI ← 1 (masks interrupts) • Timer 2 interrupt request flag ← 0 • Masks priority 3-0 interrupts; SCI1, SCI2 of IPRA and IPRB and interrupts of timers 3 and 4 ← 0 • UI ← 0 (interrupts enabled for priority 4 or higher) UI = 0 • UI ← 0 (interrupts enabled for priority 3 or higher) • UI ← 1 (masks interrupts other than NMI) • Enables priority 2–0 interrupts; SCI2 of IPRA and IPRB and interrupts of timers 3 and 4 ← 1 • RTE • UI ← 1 (masks interrupts other than NMI) • Masks priority 2–0 interrupts (enables priority 3 interrupts); SCI2 of IPRA and IPRB and interrupts of timers 3 and 4 ← 0 (SCI1 interrupt ← 1) • RTE =: State ←: Processing _: Processing unique to H8/300H Figure 1.5 Processing Procedures 19 Technical Questions and Answers Product H8/300H Q&A No. QA300H-018A Topic Receiving an External IRQ1 After Returning From Hardware Standby Mode Question Classification—H8/300H In the hardware standby mode, I set the IRQ1 pin to low and then left the hardware standby mode. Will interrupts be accepted after returning while the IRQ1 pin remains low? Software Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Interrupts will not be accepted immediately after returning. A reset clears hardware standby mode. This initializes the IER (IRQ enable register) and IRQ1 becomes disabled (the IRQ1E (IRQ1 enable) bit of the IER = 0). Thereafter, if the IRQ1E bit of the IER is set to 1 and the I and UI bits of the CCR enable interrupts, interrupts will be accepted. Manual Title Other Technical Documentation Document Name See section 4.2.3, Interrupts After a Reset, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 20 Technical Questions and Answers Product H8/300H Topic Interrupt Priority Within Groups Q&A No. QA300H-019A Question Classification—H8/300H 1. When external interrupts occur simultaneously within groups with the same priority (for example, IRQ4–IRQ7) which has priority? 2. When an IRQ4 interrupt occurs during an IRQ7 interrupt processing routine, what happens? (Does IRQ4 wait or does IRQ4 processing take priority?) Software Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer 1. A priority is set within the IRQ4–IRQ7 interrupt group of IRQ4 > IRQ5 > IRQ6 > IRQ7. 2. The IRQ7 is accepted first. After it is accepted, IRQ4–IRQ7 are all masked. When the I (interrupt mask) and UI (interrupt mask) bits of the CCR (condition code register) are enabled during the IRQ7 processing routine, IRQ4–IRQ7 can be accepted. When not enabled in the IRQ7 processing routine, the IRQ4 is accepted after returning from the IRQ7 processing routine. Manual Title Other Technical Documentation Document Name See table 5.3, Interrupt Factors, Vector Addresses, and Interrupt Priority Ranking (1) , in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 21 Technical Questions and Answers Product H8/300H Topic Interrupts When the Bus Is Released Q&A No. QA300H-020A Question Classification—H8/300H Software Are interrupts that occur when the bus is released held? Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer They are. After the bus release ends, they are accepted after the execution of one instruction. This is the same regardless of whether they are sensed by edge or level. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 22 Technical Questions and Answers Product H8/300H Q&A No. Topic NMI Sampling Timing and Receiving After Reset QA300H-021A Question Classification—H8/300H Software After reset, when does sampling of the NMI signal begin? Registers Bus controller Interrupts o Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Sampling of the NMI signal begins simultaneously with the fall of the system clock in which the reset clear was sampled. The NMI is not accepted, however, until after the execution of the first instruction after the reset is cleared (see figure 1.6) Manual Title Other Technical Documentation φ Document Name Reset clear tRESS sampling tRESS RES Related Microcomputer Technical Q&A tRESW NMI not sampled Title NMI sampled Figure 1.6 NMI Sampling Timing and Receiving After Reset References 23 Technical Questions and Answers Product H8/300H Topic Initializing SP After Reset Q&A No. QA300H-022A Question Classification—H8/300H Software Why does the SP (stack pointer) have to be initialized immediately after a reset? Registers Bus controller Interrupts o Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals If an interrupt is accepted before the SP is initialized, the save address when the PC (program counter) is saved by the interrupt exception processing becomes undefined. The PC could be written to a blank address, to the I/O registers and so on, which makes it impossible to read them correctly on return. This can cause run-away operation. To avoid this, initialize the SP immediately after a reset. Manual Title Other Technical Documentation Document Name See section 4.2.3, Interrupts After a Reset, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 24 Technical Questions and Answers Product H8/300H Topic Pin State During Power-On Reset Q&A No. QA300H-023A Question Classification—H8/300H Software What pin states do I need to pay attention to during power-on resets? Registers Bus controller Interrupts o Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals During a power-on reset, set the device to an operating mode that uses the mode pins (MD0–MD2) and keep the STBY pin high. Also remember that the φ output data is undefined until oscillation settles. Manual Title Other Technical Documentation Document Name See section 3.1.1, Types of Operating Mode Selection, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 25 Technical Questions and Answers Product H8/300H Topic RESO Pin Output From RES Pin Input Q&A No. QA300H-024A Question Classification—H8/300H Software What is the RESO pin state for reset state (RES = low)? Registers Bus controller Interrupts o Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals The RESO pin is high impedance for reset state (RES = low). It does not go to reset output (RESO = low). Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 26 Technical Questions and Answers Product H8/300H Q&A No. Topic Connecting RES and RESO Pins QA300H-025A Question Classification—H8/300H Software Is there any problem with taking RESO pin low output and inputting it directly to the RES pin? Registers Bus controller Interrupts o Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Yes. When a WDT (watchdog timer) overflow causes RESO output to be input directly to the RES pin, a reset caused by RES pin input is triggered at that moment and everything internal to the LSI, including the WDT, is initialized. This forcibly disables the RESO output as well, meaning that the RES input spec tRESW (RES pin pulse width) minimum of 10 tcyc cannot be satisfied and the operation of the H8/300H CPU after that point cannot be guaranteed. A buffer thus needs to be inserted to ensure that the RESO output does not find its way to the RES pin. (See figure 1.7.) RES RESO H8/300H External reset Figure 1.7 Connecting RES and RESO Pins References 27 Other Technical Documentation Document Name Related Microcomputer Technical Q&A RES Peripheral LSI Manual Title Title Technical Questions and Answers Product H8/300H Topic Cautions for Reset Input Q&A No. QA300H-026A Question Classification—H8/300H Software Are there any cautions for reset input? Registers Bus controller Interrupts o Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals When the RES pin is made low, a reset begins, but to be sure that a reset is performed, it must be low for at least 20 ms when the power is turned on and at least 10 system clock cycles when operating. When it goes high thereafter, reset exception processing begins. If these conditions are not satisfied, operation thereafter cannot be guaranteed. Manual Title Other Technical Documentation Document Name See section 4.2.2, Reset Sequence, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 28 Technical Questions and Answers Product H8/300H Q&A No. Topic Executing Instructions When Switching to Hardware Standby Mode QA300H-027A Question Classification—H8/300H Software What happens to executing instructions when the STBY pin goes low and the hardware standby mode is entered? Registers Bus controller Interrupts Resets o Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The executing instruction halts without waiting to finish and its operation cannot be guaranteed. To preserve the contents of RAM, clear the RAME (RAM enable) bit of the SYSCR (system control register) to 0. Manual Title Other Technical Documentation Document Name See section 17.5.1, Transition to Hardware Standby Mode, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual See section 19.5.1, Transition to Hardware Standby Mode, in the following manual: • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 29 Technical Questions and Answers Product H8/300H Q&A No. Topic Mode Pins During Hardware Standby Mode QA300H-028A Question Classification—H8/300H Software What happens when the mode pins (MD2–MD0) are changed in hardware standby mode? Registers Bus controller Interrupts Resets o Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The result is abnormal hardware standby mode operation. Do not change the mode pins while in hardware standby mode. When the mode is changed to PROM mode, for example, the power consumption goes up. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 30 Technical Questions and Answers Product H8/300H Q&A No. Topic Returning From Hardware Standby Mode QA300H-029A Question Classification—H8/300H Software I know that the RES pin has to be kept low and the STBY pin changed to high to return from hardware standby mode, but how long before the STBY pin is changed to high does the RES pin have to be low? Registers Bus controller Interrupts Resets o Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer To return from hardware standby mode, the RES pin has to be low for 100 ns before the STBY pin is changed to high. (See figure 1.8.) Manual Title Other Technical Documentation STBY Document Name RES 100 ns tOSC Figure 1.8 Standby Release Timing See Appendix E, Hardware Standby Mode Transition (Return Timing), in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 31 Technical Questions and Answers Product H8/300H Q&A No. Topic Interrupt Sampling and Receiving in Sleep Mode QA300H-030A Question Classification—H8/300H 1. When are external interrupts sampled during sleep mode? 2. How many states after an interrupt is sampled is sleep mode cleared? Software Registers Bus controller Interrupts Resets o Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer 1. Sampling is the same as during program execution. Sampling occurs at every fall of the system clock. 2. Sleep mode is cleared 6 states after the interrupt is sampled. (See figure 1.9.) Manual Title Other Technical Documentation Sleep mode 6 states Document Name φ Address bus 1 2 3 Data bus (D15–D0) 5 6 7 4 8 Interrupt request signal Related Microcomputer Technical Q&A Title 1: SP-2 2: SP-4 3, 4: Interrupt vector address 5, 6: Saved PC and saved CCR 7, 8: Interrupt processing routine start address (contents of vector address) Note: Example is an H8/3003 (16-bit bus mode, 2-state access, stack is external memory) Figure 1.9 Timing of Clearing Sleep Mode by Interrupt 32 Technical Questions and Answers Product H8/300H Q&A No. Topic Execution Time in Software Standby Mode QA300H-031A Question Classification—H8/300H Software How many states are needed to transition to the software standby mode using a SLEEP instruction? Registers Bus controller Interrupts Resets o Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The time required to transition to the software standby mode is the time (states) required for the SLEEP instruction to execute. When the SLEEP instruction is stated in on-chip memory, it takes 2 states; when the SLEEP instruction is in external 8-bit 3-state-access space, it takes 6 states. The figure below shows the timing for execution of the SLEEP instruction. (See figure 1.10.) Manual Title Other Technical Documentation Document Name SLEEP instruction execution time Sleep mode φ Internal address bus Related Microcomputer Technical Q&A 1 Internal data bus (16 bits) 2 3 Title 4 1: PC 2: PC+2 3: SLEEP instruction 4: Next instruction (not executed) Figure 1.10 Sleep Instruction Timing 33 Technical Questions and Answers Product H8/300H Q&A No. QA300H-032A-1 Topic Operation When an Interrupt is Requested During Execution or While Fetching a SLEEP Instruction Question Classification—H8/300H Software How does the H8/300H CPU operate when an interrupt comes in during a SLEEP instruction fetch or while a SLEEP instruction is executing? Registers Bus controller Interrupts Resets o Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Operation varies, depending on the time the interrupt request occurs, as shown below: A. During SLEEP instruction fetch: The interrupt exception processing starts after the previous instruction finishes executing. The saved PC becomes the address of the SLEEP instruction. After returning from the interrupt service routine, the SLEEP instruction executes. Manual Title Other Technical Documentation Document Name B. C. During SLEEP instruction execution (case 1): Interrupt exception processing starts without going through the sleep state. The saved PC becomes the address of the instruction after the SLEEP instruction. After returning from the interrupt service routine, the instruction after the SLEEP instruction executes. During SLEEP instruction execution (case 2): The sleep mode is canceled 6 states later and the interrupt service routine starts. (See figure 1.11.) References 34 Related Microcomputer Technical Q&A Title Technical Questions and Answers Product H8/300H Q&A No. QA300H-032A-2 Topic Operation When an Interrupt is Requested During Execution or While Fetching a SLEEP Instruction Answer NOP SLEEP instruction instruction Sleep mode φ Internal address bus 1 Internal data bus (16 bits) 2 3 4 Interrupt request signal (A) (B) (C) 1: SP 2: SP + 2 3: SLEEP instruction 4: Next instruction Note: During H8/3003 (mode 2, 2-state access) Figure 1.11 Timing When an Interrupt Request Occurs During SLEEP Instruction Fetch or Execution 35 Technical Questions and Answers Product H8/300H Q&A No. QA300H-033A Topic Support for the DAA (DAS) Instruction with the INC (DEC) Instruction Question 1. 2. Classification—H8/300H Software The DAA instruction can be used with an add instruction (ADD), but how about executing it after an INC instruction executes? Registers Bus controller The DAS instruction can be used with a subtract instruction (SUB), but how about executing it after an DEC instruction executes? Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer 1. Execution of a DAA instruction after execution of an INC instruction is not supported, since the C and H flags do not reflect the results of the operation after INC instruction execution. To increment decimal data, execute a DAA instruction after adding 1 with the ADD instruction (ADD.B #1, Rd). 2. Execution of a DAS instruction after execution of an DEC instruction is not supported, since the C and H flags do not reflect the results of the operation after DEC instruction execution. To decrement decimal data, execute a DAS instruction after adding –1 with the ADD instruction (ADD .B #–1, Rd) and inverting the C and H flags (XORC #A0, CCR). Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References Actual operation is determined by the flag state. 36 Technical Questions and Answers Product H8/300H Topic BRA and BRN Instructions Q&A No. QA300H-034A Question Classification—H8/300H 1. What is the difference between BRA (BT) and JMP? Also, what does it mean for the condition to be "True"? 2. What does it mean for the BRN (BF) condition to be "False"? Software Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer 1. Related Manuals The BRA instruction can be used just like the JMP instruction, but differs in the following points: • It can only branch in the range +127 bytes to –128 bytes for d:8 and +32767 bytes to –32768 bytes for d:16. • If the relative values of objects do not change, the program can be relocated. • Execution states and instruction size are different. • Assembler format is different. Manual Title Other Technical Documentation Document Name A condition of True means that since this instruction always branches, the branch condition is always True. 2. A condition of False means that since this instruction never branches, the branch condition is always False. Related Microcomputer Technical Q&A Title References 37 Technical Questions and Answers Product H8/300H Topic BRN Instruction Q&A No. QA300H-035A Question Classification—H8/300H Software What kind of instruction is BRN (BF)? Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals BRN is a convenient instruction that replaces conditional branch instructions during debugging. It operates the same as the NOP instruction, but its size and execution time differ as described in table 1.5. Table 1.5 The BRN Instruction Other Technical Documentation Instruction Instruction Size (Bytes) Instruction Execution Time (States) BRN d:8 2 4* d:16 4 6* 2 2* NOP Note: Manual Title For a 16-bit bus/2-state access space or an instruction fetch from the onchip ROM. Document Name Related Microcomputer Technical Q&A Title References Like BRN, BRA (BT) is convenient to use during debugging. 38 Technical Questions and Answers Product H8/300H Q&A No. Topic The SUBX Instruction QA300H-036A Question Classification—H8/300H Software Why does the SUBX instruction (subtraction with carry) preserve the Z flag when the result of execution is 0? Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The SUBX instruction is used to divide a subtraction operation into multiple subtractions. After the SUBX instruction is executed, the Z flag reflects the result of all of these operations (See figure 1.12.). It does not reflect the results of each individual SUBX instruction. SUB RmL, RnL Manual Title Other Technical Documentation Document Name Reflected in Z flag SUBX RmH, RnH Figure 1.12 Z Flag When the SUBX instruction results in a 0, the Z flag thus holds the result of the previous operation. Related Microcomputer Technical Q&A Title References 39 Technical Questions and Answers Product H8/300H Q&A No. Topic Odd Address Values During STC Instruction Execution QA300H-037A Question Classification—H8/300H Software What is the odd address value when an STC instruction is executed and the CCR stored in an (register indirect) even address? Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Manual Title Undefined. Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 40 Technical Questions and Answers Product H8/300H Q&A No. QA300H-038A Topic Interrupts and DMA Transfer Requests While the EEPMOV Instruction Is Executing Question Classification—H8/300H 1. When an interrupt occurs during the execution of an EEPMOV instruction, what happens to that interrupt request? 2. What happens when a DMA transfer request occurs during the execution of an EEPMOV instruction? Software Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer 1. 2. Related Manuals When an interrupt occurs during the execution of an EEPMOV.B instruction, the interrupt is held and accepted when the instruction finishes executing. It is handled the same as when an interrupt occurs during ordinary instruction execution. However, NMIs that occur during EEPMOV.W execution are accepted after transfer of the byte in transfer is completed. For interrupts other than NMIs, operation is the same as for EEPMOV.B. The DMA transfer is executed between the read cycle and write cycle of the EEPMOV instruction. Manual Title Other Technical Documentation Document Name See section 2.2.28 (items 1 and 2), EEPMOV, in the following manual: • H8/300H Series Programming Manual Related Microcomputer Technical Q&A Title References 41 Technical Questions and Answers Product H8/300H Q&A No. Topic The Difference Between EEPMOV.B and EEPMOV.W QA300H-039A Question Classification—H8/300H Software What is the difference between EEPMOV.B and EEPMOV.W? Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals The transfer data size of both the EEPMOV.B and EEPMOV.W instructions is byte, but there are some differences, as described below. • • Size of register that counts the transfer bytes: EEPMOV.B: Byte (maximum number of transfer bytes is 255). EEPMOV.W: Word (maximum number of transfer bytes is 65535). Enable/disable of interrupt acceptance: EEPMOV.B: Accepted after instruction executes (all held). EEPMOV.W: NMI alone is accepted after transfer of byte in transfer is completed (all others held). Manual Title Other Technical Documentation Document Name See section 2.2.28 (1), (2) EEPMOV • H8/300H Series Programming Manual Related Microcomputer Technical Q&A Title References 42 Technical Questions and Answers Product H8/300H Topic Cautions on Stack Operation Q&A No. QA300H-040A Question Classification—H8/300H Software Are there any particular cautions about stack operation to be aware of? Registers Bus controller Interrupts Resets Power-down mode Instructions o Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer On the H8/300H, the stack area is always accessed by word or longword. When the stack pointer is set to an odd number, malfunctions can result. Use the PUSH or POP instructions to stack. The initial value of SP (stack pointer) is undefined. It is initialized by the user. Manual Title Other Technical Documentation Document Name See section 2.4.4 Inicial CPU Resistor, section 2.5.2 Memory Data Formats, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 43 Technical Questions and Answers Product H8/300H Q&A No. Topic On-Chip Peripheral LSI Access When the Bus Is Released QA300H-041A Question Classification—H8/300H Software Can external devices (bus master) access internal registers of the H8/300H when the H8/300H CPU has released the bus to an external device? Registers Bus controller Interrupts Resets Power-down mode Instructions o Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals No. Internal registers cannot be accessed from external devices. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 44 Technical Questions and Answers Product H8/300H Q&A No. Topic Areas That Can Be Used as ROM by the Vector Table QA300H-042A Question Classification—H8/300H 1. Can the empty areas of the vector table (reserved by system or reserve) be used as ROM? 2. Can the empty areas of the I/O registers be used as ROM? Software Registers Bus controller Interrupts Resets Power-down mode Instructions o Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals 1. The vector numbers reserved by the system (4–6) on the vector table cannot be used. Reserve addresses, however, can be used as ROM. Unused interrupt vector addresses on the vector table can also be used. 2. The empty areas of the I/O registers cannot be used. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References Items reserved by the system are used by development tools. Addresses reserved by the system and reserve addresses are listed in the manual. Branch address areas of "memory indirect" addressing can use addresses other than those reserved by the system or those of used by the vector table. 45 Technical Questions and Answers Product H8/300H Q&A No. Topic Pin State During the Oscillation Settling Time QA300H-043A Question Classification—H8/300H Software What are the pin states during oscillation settling time after the software standby mode is cleared? Registers Bus controller Interrupts Resets Power-down mode Instructions o Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Manual Title The same as in the software standby mode. Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 46 Section 2 On-Chip Peripherals Technical Questions and Answers Product Common Q&A No. Topic Receiving DMAC Startup Requests QA300H-101-1 Question Classification—H8/300H Software When a DMA controller startup request occurs: Registers Bus controller 1. When is the request forced to wait? 2. Is the request accepted under the following conditions? • During EEPMOV execution • During read-modify-write instruction execution • During DMAC cycle steal transfers. Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer 1. The bus arbiter priority order is: external bus master > refresh controller > DMAC > CPU. This means that DMA requests are not accepted when an external bus master or refresh controller with a priority higher than the DMAC has the bus. Since the DMAC channels have the priorities (for H8/3003) shown in table 2.1, the request waits when a higher priority channel is transferring. Table 2.1 Manual Title Other Technical Documentation Document Name DMAC Channel Priority Short Address Mode Full Address Mode Priority Channel 0 A Channel 0 B Channel 0 Highest Channel 1 A Channel 1 B Channel 1 Channel 2 A Channel 2 B Channel 2 Channel 3 A Channel 3 B Channel 3 Related Microcomputer Technical Q&A Title Lowest References 47 Technical Questions and Answers Product Common Q&A No. Topic Receiving DMAC Startup Requests QA300H-101-2 Answer 2. During EEPMOV execution, requests are accepted between the read cycle and the write cycle. During read-modify-write instruction execution, requests are accepted between the read cycle, instruction fetch, and the write cycle. During cycle steal transfers, requests are accepted if the channel of the transfer request is higher in priority than the current channel. References 1. BSET, BCLR, BNOT, BST and BIST are read-modify-write instructions. 2. When the wait is longer than those described above, wait states may have been inserted by a CPU bus cycle that has a DREQ request. (See figure 2.1.) CPU cycle CPU cycle T1 T2 Tw T3 T1 T2 Tw T3 DREQ request DMA cycle Requires 7 states in the case shown Figure 2.1 Wait State Insertion 48 Technical Questions and Answers Product Common Q&A No. Topic Addresses During DMA Transfers QA300H-102 Question Classification—H8/300H Software Doesn’t the CPU cause problems in DMAC operation if it reads the MAR (memory address register) during DMA transfers? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Reading the MAR does not have any affect on DMA operation. However, when longword data is read, a DMA cycle can enter in between reading of the top 16-bits of data and the bottom 16-bits of data, as described in the manual. As a result, the value read may differ from the actual value. The timing at which the MAR is updated is shown in figure 2.2. Manual Title Other Technical Documentation Document Name DMA cycle Td T1 T2 T1 Transfer source 1 2 T2 Transfer destination 3 1' Related Microcomputer Technical Q&A Title 1. MAR updated at transfer source. 2. Counter updated. 3. MAR updated at transfer destination Note: MAR also updated at transfer source at 1' (during burst transfers and in the block transfer mode). Figure 2.2 MAR Update Timing References There should be no mistake in the value read so long as the bottom 16-bit (MARH, MARL) value is read with the MOV.W instruction. 49 Technical Questions and Answers Product Common Q&A No. Topic TEND Signal Output Timing 1 QA300H-103 Question Classification—H8/300H Software Is the TEND signal output at every byte/word transfer? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The TEND signal is output when the startup source is an external request (using the DREQ pin). In operating modes other than block transfer mode, the TEND signal is driven low during the final transfer write cycle. For block transfers, it is low during the write cycle just before the end of a 1 block transfer. It is not output at every byte/word. (See figure 2.3.) Manual Title Other Technical Documentation Final DMA cycle Td T1 T2 T1 CPU cycle Document Name T2 φ Address bus Related Microcomputer Technical Q&A RD Title HWR, LWR TEND Figure 2.3 TEND Output References 50 Technical Questions and Answers Product Common Q&A No. Topic TEND Signal Output Timing 2 QA300H-104 Question Classification—H8/300H Software At what timing is the TEND signal output? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The TEND signal is output in the write cycle when the ETCR (transfer count register) becomes H'00. Figure 2.4 illustrates the timing. Final DMA cycle Td T1 T2 T1 Manual Title CPU cycle Other Technical Documentation T2 φ Document Name Address bus RD HWR, LWR Related Microcomputer Technical Q&A TEND ETCR Title H'01 H'00 Figure 2.4 TEND Output Timing References 51 Technical Questions and Answers Product Common Q&A No. Topic The Relationship Between the DMAC’s DTE and DTIE Bits QA300H-105 Question Classification—H8/300H Software When the DTIE (data transfer interrupt enable) bit is 1 and the DTE (data transfer enable) bit is then cleared to 0, the manual says that an interrupt is requested of the CPU. Registers Bus controller Interrupts 1. 2. Will DMA transfer end interrupts occur continuously, as shown in figure 2.5? If so, what can be done to keep interrupts from occurring? Resets Power-down mode Instructions Miscellaneous DTE = 0, DTIE = 1 o DMA controller ITU DMA interrupt processing Watchdog timer SCI Holds the values DTE = 0, DTIE = 1 A/D converter I/O ports RTE Figure 2.5 Continuous Interrupts from DTE and DTIE Answer Related Manuals Manual Title 1. Yes, interrupts will occur continuously. 2. If DTE = 0 and DTIE = 1 (enabling interrupts), interrupts will always be produced. To prevent this, set DTE to 1 (the BSET instruction can be used), or clear the DTIE bit to 0 (the BCLR instruction can be used). Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 52 Technical Questions and Answers Product Common Q&A No. Topic DMAC Startup QA300H-106 Question Classification—H8/300H Software When the DMAC is started up with an ITU compare match interrupt, what happens if the I (interrupt mask) and UI (user bit/interrupt mask) of the CCR (condition code register) are masked? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Interrupts selected as DMAC startup sources are not affected by the CPU’s interrupt mask bits (I and UI bits). (See figure 2.6.) Manual Title SYSCR UE Peripheral module UI I Flag for compare match or the like Interrupt enable bit CCR Other Technical Documentation Document Name Priority determination circuit CPU Related Microcomputer Technical Q&A DMAC Title DTE Figure 2.6 DMAC Startup References When an interrupt is disabled with an interrupt enable bit in a module, interrupts will not occur for either the DMAC startup request or the CPU. 53 Technical Questions and Answers Product Common Topic The DMAC and Timer Interrupts Q&A No. QA300H-107 Question Classification—H8/300H Software When the DMAC startup source has compare-matched the ITU, is an interrupt produced to the CPU of the ITU? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Interrupt requests selected as startup sources startup the DMAC when the DTE (data transfer enable) bit of the DMAC’s DTCR (data transfer control register) is set to 1, and no interrupt is generated to the CPU. When the DTE bit is 0, no startup request is generated and an interrupt goes to the CPU. An interrupt that is used as a startup source cannot simultaneously generate an interrupt to the CPU. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 54 Technical Questions and Answers Product Common Q&A No. Topic Operation After a DMAC End Interrupt Is Generated 1 QA300H-108 Question Classification—H8/300H Software When the transfer count register becomes H'0000 while the DMAC is in use and an end interrupt is generated: 1. When is the next transfer request accepted? 2. Are transfer requests generated before the DMA transfer starts ignored? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer 1. 2. Related Manuals The next transfer request is accepted when the DTE (data transfer enable) bit is set to 1 by software. When the transfer count register reaches H'0000 and a transfer end interrupt is generated, the DTE bit of the DTCR (data transfer control register) is cleared and data transfer is disabled. To do another transfer, set the transfer count register during the end interrupt routine and then set the DTE bit to 1. When the startup request is an internal interrupt, a CPU interrupt is requested when the DTE bit is 0. For more information, see the hardware manual. When the startup request is an external request, it is ignored if it is an edge. Manual Title Other Technical Documentation Document Name See section 8.6, Cautions on Use, in the following manuals: • H8/3002 Hardware Manual • H8/3003 Hardware Manual • H8/3042 Series Hardware Manual Related Microcomputer Technical Q&A Title References 55 Technical Questions and Answers Product Common Q&A No. Topic Operation After a DMAC End Interrupt Is Generated 2 QA300H-109 Question Classification—H8/300H Software When the transfer count register becomes H'0000 while the DMAC is in use and the transfer ends, when is the transfer end interrupt generated? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals After the transfer ends, an interrupt request is generated and the bus is released. When the CPU captures the bus, the transfer end interrupt is performed after the executing instruction ends. (See figure 2.7.) CPU cycle Final DMA transfer cycle CPU cycle Exception processing started by DMAC transfer end interrupt Manual Title Other Technical Documentation Document Name φ Transfer end interrupt signal Related Microcomputer Technical Q&A Figure 2.7 Timing at DMAC End Interrupt References 56 Title Technical Questions and Answers Product Common Q&A No. Topic DMA Transfers Started up by Serial Transfers QA300H-110 Question Classification—H8/300H Software Can more than 256 transfers be done between memory and I/Os when SCI and DMAC are used together to send and receive? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals When the DMAC is started up by the SCI, I/O mode should be used. The maximum number of transfers allowed will then be 65,536. To transfer more data than this, data must be stored in memory and the transfer counter reset with a transfer end interrupt. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 57 Technical Questions and Answers Product Common Q&A No. Topic Time Until DMAC Startup by the DREQ Pin QA300H-111 Question Classification—H8/300H Software Why is 4 states the minimum time to startup the DMAC from the DREQ pin? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals The delay time from the DREQ pin to the internal DMAC module is 2 states. The bus arbiter internal processing time is also 2 states. This means a minimum of 4 states (the sum of these figures) is required. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 58 Technical Questions and Answers Product Common Q&A No. Topic Reverse Operation in the DMA Repeat Mode QA300H-112 Question Classification—H8/300H Software What do I do to pause a DMA transfer that uses repeat mode and then start it up in the opposite direction? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Manual Title The flowchart in figure 2.8 illustrates the process. Forward byte transfer (DTID = 0) Disable internal interrupts that cause start-ups Document Name DTE = 0 true false i≥2* DMAC halted MAR = MAR – 2 ETCRH = i – 1 Other Technical Documentation MAR = MAR + (ETCRL + i – 2) ETCRH = ETCRL + i – 1 Related Microcomputer Technical Q&A Title DTE = 1 Reversed byte transfer (DTID = 1) Enable internal interrupts that cause start-ups i: Number of transfer cycles. i = ETCRL–ETCRH. Figure 2.8 Reverse Operation in the DMA Repeat Mode 59 Technical Questions and Answers Product Common Topic Use of Dual-Function Pins Q&A No. QA300H-113 Question Classification—H8/300H Software When the DMAC is used under the following conditions, can the TEND/CS dual-function pin be used as a CS output? Registers Bus controller Conditions: Full-address transfer mode, external request (low level input from DREQ pin) for the startup source. Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer It cannot be used as a CS output. When external request is selected as the startup source, the TEND/CS dual-function pin concerned becomes a TEND output pin. For more information, see the I/O Port section in the hardware manual. Manual Title Other Technical Documentation Document Name See section 9, I/O Ports, in the following manual: • H8/3003 Hardware Manual Related Microcomputer Technical Q&A Title References 60 Technical Questions and Answers Product Common Topic I/O Ports and the DREQ Pin Q&A No. QA300H-114 Question 1. 2. Classification—H8/300H Software How should the DTE (data transfer enable) bit of the DTCR (data transfer control register) be set to use pins that are used both as DREQ pins and I/O ports as I/O ports? Registers Bus controller Interrupts How should dual-function pins be set for use as DREQ pins? Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer 1. They can be used as I/O ports without regard to the DTE bit. 2. To use dual-function pins as DREQ pins, clear the DDR (data direction register) of affected ports to 0. When the DDR is set to 1, port output is detected as DREQ input. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 61 Technical Questions and Answers Product Common Q&A No. Topic PWM Mode and Interrupts QA300H-115 Question Classification—H8/300H Software When the ITU is used in the PWM mode and interrupts are enabled, is it necessary to clear the IMFB (input capture/compare match flag B) of the TSR (timer status register) to 0 within the interrupt processing routine or is the IMFB automatically cleared when an IMIB interrupt is generated? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals The IMFB flag must be cleared to 0 within the interrupt processing routine. The timing when the flag is cleared by the program is shown in figure 2.9. T1 T2 T3 Other Technical Documentation Document Name φ Address Manual Title TSR address Related Microcomputer Technical Q&A IMF Flag cleared Figure 2.9 IMFB Flag References To clear the IMFB flag, use the BCLR instruction. 62 Title Technical Questions and Answers Product Common Topic Clearing the Counters Q&A No. QA300H-116 Question Classification—H8/300H Software How do I clear the ITU counter using software? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Clear the TCNT (timer counter) by writing H'0000 to it. The counter value is not cleared by rewriting the TSTR (timer start register). Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 63 Technical Questions and Answers Product Common Topic Pulse Output From the ITU Q&A No. QA300H-117 Question Classification—H8/300H Software How do I get a specific number of pulses output (say, 10) and then stop the pulse output? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Answer 1. 2. 3. Related Manuals When 1 DMAC channel can be used: Pulses are output in the ITU’s PWM mode. In this case, the DMAC is started up by an ITU compare match. Set DMA transfers for 10 and generate a transfer end interrupt to stop the ITU. This DMA transfer is aimed at starting up 10 times; set the data transfer so that it does not affect CPU operation (transfer data, transfer source address, transfer destination address). When other timers can be used: Output pulses are input to the TCLK pin (clock input pin) and events counted by another timer (x). When the timer (x) compare register reaches a count of 10, a compare match interrupt is generated and the ITU stops. On the H8/300H, TIOCA0/TCLKC and TIOCB0/TCLKD are dualfunction pins. For this reason, no extra wiring needs to be added on the board to output pulses from channel 0 and use TCLKC and TCLKD as input pins. When using software: Generate compare match interrupts each time and count with the interrupt processing routine. References 64 Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title Technical Questions and Answers Product Common Q&A No. Topic ITU Cascade Connections QA300H-118 Question Classification—H8/300H Software Can cascade connections be used with the ITU? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The PA2 and PA3 pins of port A are dual function pins for outputs TIOCA0 and TIOCB0 of the ITU’s channel 0 and clock inputs TCLKC and TCLKD. This enables direct ITU cascade connections without external wiring. The count timing for the ITU in the host is shown in figure 2.10. Manual Title Other Technical Documentation φ (system clock) Document Name TIOCA0/TCLKC TIOCB0/TCLKD Sampling Figure 2.10 ITU Count Timing Related Microcomputer Technical Q&A Title When there is no wiring from TIOCA0/TCLKC or TIOCB0/TCLKD to off the chip and the load is light, TCLKC and TCLKD sample the compare match output of TIOCA0 and TIOCB0 at the rise of the next φ. References 65 Technical Questions and Answers Product Common Topic Setting the ITU’s PWM Output Q&A No. QA300H-119 Question Classification—H8/300H Software When the ITU is used in PWM mode, how should the TIOR (timer I/O control register) be set? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals The TIOR setting does not affect PWM output. When the PWM mode is set with the PWM bit of the TMDRs (timer mode registers) located in each of the channels of the ITU, GRA/GRB are used as output compare registers for output setting, regardless of the contents of the TIOR. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 66 Technical Questions and Answers Product Common Q&A No. Topic ITU Output and Port Output QA300H-120-1 Question Classification—H8/300H Software When the ITU is set to toggle output on a GRB (output capture/input compare dual-function register B) compare match to get the output shown in figure 2.11, what kind of value is output when changing from port output to ITU output? Registers Bus controller Interrupts Resets Power-down mode Instructions (TCNT value) Miscellaneous GRB DMA controller o ITU Watchdog timer (Time) TIOCB output, port output SCI A/D converter ITU output Port output I/O ports ITU output High output or low output? Set for toggle output upon compare match in the TIOR (timer I/O control register) Set for port output with output upon compare match in the TIOR (timer I/O control register) disabled Set for toggle output upon compare match in the TIOR (timer I/O control register) Related Manuals Manual Title Figure 2.11 ITU Output and Port Output (Q) Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 67 Technical Questions and Answers Product Common Q&A No. Topic ITU Output and Port Output QA300H-120-2 Answer 1. When port output is changed to ITU output, the value from before the change is output. 2. When a compare match signal is generated at the point when the port output is to be changed to ITU output, the value changes. (See figure 2.12.) Case 1 TIOCB output, port output High output before set for port output Output becomes high at ITU toggle output ITU output I/O port output Port output set to low by program Set to ITU toggle output again in program Low level output, since compare match signal is generated before setting to ITU output Case 2 Compare match signal TIOCB output, port output ITU output Output becomes high at ITU toggle output ITU output I/O port output Port output set to low by program ITU output Set to ITU toggle output again by program Figure 2.12 ITU Output and Port Output (A) References 1. When the ITU was started after a reset, the TIOCn output is low until the first compare match occurs. 2. When set to input capture and output is disabled, the output level changes when an input capture occurs. 68 Technical Questions and Answers Product Common Topic ITU Settings Q&A No. QA300H-121-1 Question Classification—H8/300H Software Please explain in detail the pulse width, cycle settings and register settings for ITU pulse output as well as the relationship to the internal clock. Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals When outputting pulses in the PWM mode, the duty can be found from the following equation. Duty = n + 1 / N + 1 where GRA = n (set the counter value corresponding to the Low width – 1), and GRB = N (set the counter value corresponding to the cycle – 1) Manual Title Other Technical Documentation Document Name Example: When the operating frequency is 10 MHz, the internal clock for the count is φ/2 and GRB = 9, so to get a duty of 50% (with an N of 9): (n + 1)/(9 + 1) = 0.5 GRA must be set to 4. The exact timing is shown in figures 2.13 to 2.16. Related Microcomputer Technical Q&A Title References 69 Technical Questions and Answers Product Common Topic ITU Settings Q&A No. QA300H-121-2 Answer φ Internal clock (φ/4) 1.5 tcyc 1.5 tcyc H'0000 H'0000 TCNT H'0001 H'0000 TIOCA Figure 2.13 ITU Settings (1) φ Internal clock (φ/4) Compare match occurs n–1 n TCNT 0.5 tcyc n+1 n+1 n n–1 TIOCA Figure 2.14 ITU Settings (2) φ Internal clock (φ/4) Compare match occurs N–1 N 0.5 tcyc H'0000 TCNT N N–1 TIOCA Figure 2.15 ITU Settings (3) 70 Technical Questions and Answers Product Common Topic ITU Settings Q&A No. QA300H-121-3 Answer Figure 2.15 TCNT value GRB (N) Figure 2.14 GRA (n) Time Figure 2.13 TIOCA output n N Figure 2.16 ITU Settings (4) 71 Technical Questions and Answers Product Common Q&A No. QA300H-122 Topic Independent Operation of TCNT4 Using Reset-Synchronized PWM Mode Question Classification—H8/300H Software The manual states that "TCNT4 runs independently" when resetsynchronized PWM mode is used. Do this mean it can be used for other purposes? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Reset-synchronized PWM mode uses channel 3 and 4 together, but the only counters and registers it uses are TCNT3, GRA3, GRA4, GRB3 and GRB4. This allows TCNT4 to be used independently. One way to use it might be to run it as an interval timer using counter overflows. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 72 Technical Questions and Answers Product Common Topic Halting the WDT’s System Clock Q&A No. QA300H-123 Question Classification—H8/300H Software When the system clock is halted, does the WDT (watchdog timer) detect abnormalities? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU o Watchdog timer SCI A/D converter I/O ports Answer Related Manuals When the system clock of the entire LSI is halted, the WDT count stops as well, so it cannot detect abnormalities. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 73 Technical Questions and Answers Product Common Q&A No. Topic Using the RDR and TDR When the SCI Is Not Being Used QA300H-124 Question Classification—H8/300H Software When the SCI is not being used: Registers 1. Can the RDR (receive data register) be used as a data register? 2. Can the TDR (transmit data register)? Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals Manual Title Yes and No. 1. The RDR cannot be used as a data register because it is a read-only register. 2. The TDR can be used as a data register. Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 74 Technical Questions and Answers Product Common Topic I/O Settings of Clock Pins for the SCI Q&A No. QA300H-125 Question Classification—H8/300H Software When the SCI is being used, does the DDR (data direction register) of the port for the SCK (serial clock) pin set the I/O specification for that pin? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals The I/O direction for the SCK pin when the SCI is being used is specified by the C/A bit (communications mode) of the SMR (serial mode register) and the CKE1 and CKE0 (clock enable) bits of the SCR (serial control register). Setting the DDR of the port is not necessary. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 75 Technical Questions and Answers Product Common Topic Serial I/O Pin State Q&A No. QA300H-126 Question Classification—H8/300H Software After using the dual-function pins that can be used as I/O ports (TXD, RXD and SCK) as SCI pins, I reset them as I/O ports with the SCR (serial control register) and SMR (serial mode register). What happens to the values of the DDR (data direction register) pins when this happens? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals SCI operation does not affect the contents of the DDR of the I/O port. This means that in the case described above the DDR holds the value it had before being set as an SCI pin. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 76 Technical Questions and Answers Product Common Q&A No. Topic Simultaneous Transmission and Reception with the SCI QA300H-127 Question Classification—H8/300H Software When the SCI is being used, can transmission using the internal clock occur simultaneous with reception on the external clock (or vice versa)? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals Only 1 clock source can be selected as the SCI transfer clock. This prevents simultaneous transmission and reception using 2 types of clocks. Simultaneous transmission/reception using the same clock is possible. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 77 Technical Questions and Answers Product Common Topic RDRF Q&A No. QA300H-128 Question Classification—H8/300H Software What happens if, when clearing the RDRF (receive data register full) flag of the SSR (serial status register) to 0 during SCI reception, it is cleared to 0 directly without first reading a 1? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals It will not be cleared. When the BCLR instruction is used, the SSR is first read in byte units, then the bit that corresponds to the RDRF flag is cleared to 0 and a write occurs, again in byte units. While the RDRF flag is set to 1 (RXI interrupt processing routine), the BCLR instruction thus cannot clear the RDRF flag. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 78 Technical Questions and Answers Product Common Topic Setting for Asynchronous Transmission Q&A No. QA300H-129-1 Question Classification—H8/300H Software Asynchronous transmission uses the SCI. How do I set it to do a transfer by software (i.e., using the data empty interrupt (TXI) but not the DMAC)? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals When the TDRE = 1, the data empty interrupt is always generated and the TIE is set to 1. There are thus 2 methods. 1. Setting the first byte with an interrupt processing routine: Rn ← 0 (transfer counter) TE = 1 (transfer enable) TIE = 1 (empty interrupt enable) Manual Title Other Technical Documentation Document Name 2. Setting the first byte with the initialization: Rn ← 1 (transfer counter) TE = 1 (transfer enable) First byte set to TDR TDRE cleared (transfer starts, TDRE = 1 after TDR → TSR TIE = 1 (empty interrupt enable) In either case, the TXI interrupt processing routine is as shown in the figure 2.17. References 79 Related Microcomputer Technical Q&A Title Technical Questions and Answers Product Common Q&A No. Topic Setting for Asynchronous Transmission QA300H-129-2 Answer (Empty interrupt generation) Rn ← Rn + 1 Rn = 16 No Yes TIE = 0 (interrupt disabled) (Rn)th byte of data is written to TDR; TDRE is cleared (TDRE is read and cleared) RTE Figure 2.17 TXI Interrupt Processing Routine 80 Technical Questions and Answers Product Common Q&A No. Topic How Data Is Transferred to the TDR QA300H-130-1 Question Classification—H8/300H Software Are there ways, when transferring transfer data located in 16-bit bus space to the SCI’s transmit data register (TDR, length 8 bits) as shown in figure 2.18, to: Registers Bus controller Interrupts 1. Transfer using software? 2. Use the DMAC? Resets Power-down mode Instructions Miscellaneous DMA controller H8/3003 ITU SCI Watchdog timer DRAM o Data transfer DMAC 16-bit data bus Transfer data SCI A/D converter I/O ports Figure 2.18 Transferring Data to the TDR Answer 1. Related Manuals 16-bit bus spaces can be accessed in byte units. Read transfer data on the DRAM 1 byte at a time and transfer it to the SCI’s TDR. To transfer data stored in the transfer buffer, do as shown in figure 2.19. Manual Title Other Technical Documentation 10000 Document Name 10010 Note: Start address of transfer buffer 10000 stored in ER0. Figure 2.19 Transfer Buffer References 81 Related Microcomputer Technical Q&A Title Technical Questions and Answers Product Common Q&A No. Topic How Data Is Transferred to the TDR QA300H-130-2 Answer LOOP: MOV.B #12,R2L Waiting for interrupt DEC.B R2L Set the number of transfer words Can be placed in the sleep mode Copy the transfer data (1 byte) to R3L and increment the transfer buffer pointer (ER0) by 1 Continue until the transfer counter hits 0 TxI Interrupt: MOV.B @ER0+,R3L Transfer the transfer data to the SCI’s TDR MOV.B R3L,@TDR Decrement transfer counter by 1 BCLR #7,@SSR Clear TDRE to 0 BNE LOOP Return to main routine BNE 2. LOOP Using the DMAC: Start up the DMAC with the SCI’s TXI interrupt and transfer the transfer data on DRAM 1 byte at a time to the SCI’s TDR. Byte needs to be specified as the size in the DMAC. (Word size transfers are impossible, since they start up the DMAC at every transmission of a byte.) References The bus controller function can be used to enable word-sized transfers as shown in figure 2.20. For each read cycle (16-bit data), 2 consecutive write cycles of 8-bit data are necessary. H8/300H DMA transfer RAM in 16-bit address space RAM in 8-bit space Figure 2.20 Using the Bus Controller Function to Enable Word-Sized Transfers 82 Technical Questions and Answers Product Common Q&A No. Topic Timing of Setting RDRF QA300H-131A-1 Question 1. Classification—H8/300H Software When data reception ends, the RDRF (receive data register full) flag of the SSR (serial status register) is set to 1. At what point in the asynchronous mode is the RDRF set? Registers Bus controller Interrupts 2. When is it set in clock-synchronous mode? Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer 1. Related Manuals The RDRF flag is set after the MSB data is received and the data sampling clock falls. (See figure 2.21.) Manual Title 1 2 3 4 5 6 7 8 9 101112 13141516 1 2 3 4 5 6 7 8 9 10111213141516 Basic clock Other Technical Documentation Document Name Receive data D7 Stop Data sampling Related Microcomputer Technical Q&A RDRF Title Note: When SCK clock source is the internal clock, 0.5 basic clocks + 2 states. When SCK clock source is an external clock, 3-4 states. Figure 2.21 8-Bit Data, 1 Stop Bit References 83 Technical Questions and Answers Product Common Q&A No. Topic Timing of Setting RDRF QA300H-131A-2 Answer 2. The RDRF flag is set after the MSB data is received and synchronization clock rises. (See figure 2.22.) Synchronization clock Receive data Bit 6 Bit 7 RDRF Note: When SCK clock source is the internal clock, 1 state. When SCK clock source is the external clock, 2-3 states. Figure 2.22 8-Bit Data 84 Technical Questions and Answers Product Common Q&A No. Topic Timing of Setting TDRE QA300H-132A-1 Question 1. Classification—H8/300H Software When 8-bit data transmission ends, the TDRE (transmit data register empty) flag of the SSR (serial status register) is set to 1. At what point in the asynchronous mode is the TDRE set? Registers Bus controller Interrupts 2. When is it set in clock-synchronous mode? Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Related Manuals Answer The TDRE flag is set at different times when there is transmission data in the TSR (transmit shift register) and when there is not. 1. Manual Title Asynchronous mode. (See figure 2.23.) 1 2 3 4 5 6 7 8 9 101112 13141516 1 2 3 4 5 6 7 8 9 10111213141516 Basic clock Transmit data TDRE Other Technical Documentation Document Name Stop bit Start bit When SCK clock source is the internal clock, 4 state. When SCK clock source is the external clock, 4–5 state. Figure 2.23 Transmit data in TSR (Asynchronous mode) References 85 Related Microcomputer Technical Q&A Title Technical Questions and Answers Product Common Q&A No. Topic Timing of Setting TDRE QA300H-132A-2 Answer The start of transmission according to the setting of the TE (transmit enable) bit also follows this timing. (See figure 2.24.) T1 T2 T3 φ Internal write signal 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10 11121314 Basic clock TDRE 2.5 states Figure 2.24 No transmit data in TSR (Asynchronous mode) 2. Clock-synchronous mode (See figures 2.25 and 2.26.) Synchronization clock Bit 6 Transmit data Bit 7 When SCK clock source is the internal clock, 2 state. When SCK clock source is the external clock, 1.5–2.5 state. TDRE Figure 2.25 Transmit data in TSR (Clock-synchronous mode) T1 T2 T3 φ Internal write signal TDRE TDRE set timing 2.5 states Figure 2.26 No transmit data in TSR (Clock-synchronous mode) 86 Technical Questions and Answers Product Common Topic SCI Reception Errors Q&A No. QA300H-133 Question Classification—H8/300H Software By returning to the main routine during a receive error interrupt routine without clearing the reception error flags of the SSR (serial status register), is a receive error interrupt generated again? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals The receive error flag is not automatically cleared. After returning to the main routine (after executing the RTE instruction), a receive error interrupt will be generated again. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 87 Technical Questions and Answers Product Common Q&A No. Topic Operating the SCI in External Clock Mode QA300H-134 Question Classification—H8/300H Software When the SCI is operated in clock-synchronous external clock mode: 1. 2. Registers Bus controller Does the SCI start the next transmit operation if, after the completion of 1 byte of data transmission, the external clock is applied to the SCK pin before the H8/300H CPU writes to the TDR (transmit data register)? Interrupts Resets Power-down mode Instructions What happens after reception? Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals Manual Title The results are as follows: 1. Transmission does not start. The next transmission will not start until the TDRE (transmit data register empty) of the SSR (serial status register) is cleared to 0. 2. Reception starts, however, an overrun error will occur unless the RDRF (receive data register full) of the SSR is cleared before the next data is completely received. Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 88 Technical Questions and Answers Product Common Topic System Clocks and SCK Phases Q&A No. QA300H-135 Question Classification—H8/300H Software Is the SCK (serial transfer clock) output synchronous to system clock (φ) rise or fall? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals The SCK signal is output synchronous to system clock (φ) fall. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 89 Technical Questions and Answers Product Common Q&A No. Topic Changing the A/D Mode and Channel During A/D Conversion QA300H-136 Question Classification—H8/300H 1. How do I switch the A/D conversion mode during A/D conversion? 2. How do I change the selected channel during A/D conversion? Software Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI o A/D converter I/O ports Related Manuals Answer 1. Switching the A/D conversion mode during A/D conversion will decrease conversion accuracy. We advise against it. 2. Changing the selected channel during A/D conversion causes the same problem as switching the conversion mode. Again, we advise against it. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References Before switching the A/D conversion mode or changing the selected channel, check the ADF (A/D end flag) in the ADCSR (A/D control/status register). 90 Technical Questions and Answers Product Common Q&A No. Topic Using General-Purpose Ports QA300H-137 Question Classification—H8/300H Software Can instructions that manipulate bits be used on I/O ports when a bit of the port is designated an output port? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter o Answer I/O ports Related Manuals Yes. When a port set as an output port is read by the CPU, the contents of the port data register (DR) are read, regardless of the pin state. When an input port is read, the pin state is read. This means there are no problems in using instructions that manipulate bits. When there are pins in the port that have been designated input ports, however, the DR values of the input ports will become undefined (pin state). (See figure 2.27.) 1 1 1 1 0 0 0 0 Pin status 1 1 0 0 1 1 0 0 DR contents 1 0 1 0 1 0 1 0 Read DR 1 0 1 0 1 1 0 0 Related Microcomputer Technical Q&A Bit 7 set to 1 by CPU Read DR Read pin values values DR contents after instruction BCLR #7, @DR is executed Other Technical Documentation Document Name Output Input settings settings DDR contents Manual Title 0 0 1 0 1 1 0 0 Changes with pin status Figure 2.27 Using General-Purpose Ports References The BSET, BCLR, BNOT, BST and BIST instructions manipulate bits. 91 Title Technical Questions and Answers Product Common Topic Processing Ports When Not in Use Q&A No. QA300H-138 Question Classification—H8/300H Software How should I process ports that are not in use? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter o Answer I/O ports Related Manuals 1. Clear the DDR (data direction register) of I/O ports to 0 to put them in input state and pull each pin up or down with a resistance of about 10 kΩ. 2. Handle input-only ports the same way. Manual Title Other Technical Documentation Document Name Related Microcomputer Technical Q&A Title References 92