NBSG16 2.5 V/3.3 V SiGe Differential Receiver/Driver with RSECL* Outputs *Reduced Swing ECL http://onsemi.com Description The NBSG16 is a differential receiver/driver targeted for high frequency applications. The device is functionally equivalent to the EP16 and LVEP16 devices with much higher bandwidth and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), HSTL, LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used as a reference voltage for single-ended NECL or PECL inputs and the VMM pin is used as a reference voltage for LVCMOS inputs. For all single-ended input conditions, the unused complementary differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. Features • • • • • • • • • • • Maximum Input Clock Frequency > 12 GHz Typical Maximum Input Data Rate > 12 Gb/s Typical 120 ps Typical Propagation Delay 40 ps Typical Rise and Fall Times RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output Only 50 W Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices VBB and VMM Reference Voltage Output These are Pb-Free Devices © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 20 1 QFN−16 MN SUFFIX CASE 485G MARKING DIAGRAMS* ÇÇÇ ÇÇÇ 16 1 SG 16 ALYWG G A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Publication Order Number: NBSG16/D NBSG16 VEE VBB 16 VTD 1 D 2 VMM VEE 15 14 Exposed Pad (EP) 13 12 VCC 11 Q NBSG16 D 3 10 Q VTD 4 9 VCC 5 6 7 8 VEE NC NC VEE Figure 1. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O 1 VTD − Description 2 D ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC. 3 D ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted differential input. Internal 75 kW to VEE 4 VTD − Internal 50 W Termination Pin. See Table 2. 5, 8, 13, 16 VEE − Negative Supply Voltage 6,7 NC − No Connect 9, 12 VCC − Positive Supply Voltage 10 Q RSECL Output Noninverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V 14 VMM − LVCMOS Reference Voltage Output. (VCC − VEE)/2 15 VBB − ECL Reference Voltage Output − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to VEE on the PC board. Internal 50 W Termination Pin. See Table 2. 1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 2. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. http://onsemi.com 2 NBSG16 VCC VTD VMM 36.5 KW 50 W D Q D Q 50 W 75 kW 75 kW VTD VBB VEE Figure 2. Logic Diagram Table 2. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTD and VTD to VCC LVDS Connect VTD and VTD together AC−COUPLED Bias VTD and VTD Inputs within (VIHCMR) Common Mode Range RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL The external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. LVCMOS VMM should be connected to the unused complementary differential input. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (D, D) 75 kW Internal Input Pullup Resistor (D) ESD Protection 36.5 kW Human Body Model Machine Model > 2 kV > 100 V Pb-Free Level 1 Moisture Sensitivity (Note 3) Flammability Rating Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 167 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. http://onsemi.com 3 NBSG16 Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC Positive Power Supply VEE = 0 V 3.6 V VEE Negative Power Supply VCC = 0 V −3.6 V Positive Input Negative Input VEE = 0 V VCC = 0 V 3.6 −3.6 V V VCC − VEE ≥ 2.8 V VCC − VEE < 2.8 V 2.8 |VCC − VEE| V Continuous Surge 25 50 mA VI VINPP Parameter Differential Input Voltage Condition 1 |D − D| Condition 2 VI ≤ VCC VI ≥ VEE Iout Output Current IBB VBB Sink/Source 1 mA IMM VMM Sink/Source 1 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) (Note 4) 0 lfpm 500 lfpm 41.6 35.2 °C/W qJC Thermal Resistance (Junction-to-Case) 2S2P (Note 4) 4.0 °C/W Tsol Wave Solder 265 °C Pb-Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NBSG16 Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT (VCC = 2.5 V; VEE = 0 V) (Note 5) −40°C Symbol 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 17 23 29 17 23 29 17 23 29 mA Output HIGH Voltage 1450 1530 1575 1525 1565 1600 1550 1590 1625 mV Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV Characteristic POWER SUPPLY CURRENT IEE Negative Power Supply Current RSPECL OUTPUTS (Note 6) VOH VOUTPP DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 5 & 7) (Note 7) VIH Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VIL Input LOW Voltage 0 VIH − 150 0 VIH − 150 0 VIH − 150 mV Vth Input Threshold Voltage Range (Note 8) 950 VCC – 75 950 VCC – 75 950 VCC – 75 mV VISE Single-Ended Input Voltage (VIH – VIL) 150 2600 150 2600 150 260 mV VBB PECL Output Voltage Reference 1080 1200 1080 1200 1080 1200 mV 1140 1140 1140 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 & 8) (Note 9) VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VILD Differential Input LOW Voltage 0 VIHD − 75 0 VIHD − 75 0 VIHD − 75 mV VID Differential Input Voltage (VIHD – VILD) 75 2600 75 2600 75 2600 mV 1200 2500 1200 2500 1200 2500 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 10) (Figure 9) IIH Input HIGH Current (@VIH) 30 100 30 100 30 100 mA IIL Input LOW Current (@VIL) 25 50 25 50 25 50 mA 1100 1250 1400 1100 1250 1400 1100 1250 1400 mV 45 50 55 45 50 55 45 50 55 W LVCMOS CONTROL PIN VMM CMOS Output Voltage Reference VCC/2 TERMINATION RESISTORS RTIN Internal Input Termination Resistor Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. All loading with 50 W to VCC − 2.0 V. 7. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2. 9. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NBSG16 Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT (VCC = 3.3 V; VEE = 0 V) (Note 11) −40°C Symbol 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 17 23 29 17 23 29 17 23 29 mA Output HIGH Voltage 2250 2330 2375 2325 2365 2400 2350 2390 2425 mV Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV Characteristic POWER SUPPLY CURRENT IEE Negative Power Supply Current RSPECL OUTPUTS (Note 12) VOH VOUTPP DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 5 & 7) (Note 13) VIH Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VIL Input LOW Voltage 0 VIH − 150 0 VIH − 150 0 VIH − 150 mV Vth Input Threshold Voltage Range (Note 14) 950 VCC – 75 950 VCC – 75 950 VCC – 75 mV VISE Single-Ended Input Voltage (VIH – VIL) 150 2600 150 2600 150 260 mV VBB PECL Output Voltage Reference 1880 2000 1880 2000 1880 2000 mV 1940 1940 1940 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 & 8) (Note 15) VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VILD Differential Input LOW Voltage 0 VIHD − 75 0 VIHD − 75 0 VIHD − 75 mV VID Differential Input Voltage (VIHD – VILD) 75 2600 75 2600 75 2600 mV 1200 3300 1200 3300 1200 3300 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 16) (Figure 9) IIH Input HIGH Current (@VIH) 30 100 30 100 30 100 mA IIL Input LOW Current (@VIL) 25 50 25 50 25 50 mA 1500 1650 1800 1500 1650 1800 1500 1650 1800 mV 45 50 55 45 50 55 45 50 55 W LVCMOS CONTROL PIN VMM CMOS Output Voltage Reference VCC/2 TERMINATION RESISTORS RTIN Internal Input Termination Resistor Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. 12. All loading with 50 W to VCC − 2.0 V. 13. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 14. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2. 15. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 6 NBSG16 Table 7. DC CHARACTERISTICS, NECL or RSNECL INPUT WITH NECL OUTPUT (VCC = 0 V; VEE = −3.465 V to −2.375 V) (Note 17) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 17 23 29 17 23 29 17 23 29 mA −1050 −970 −925 −975 −935 −900 −950 −910 −875 mV 350 410 525 350 410 525 350 410 525 mV POWER SUPPLY CURRENT IEE Negative Power Supply Current RSPECL OUTPUTS (Note 18) VOH VOUTPP Output HIGH Voltage Output Voltage Amplitude DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 5 & 7) (Note 19) VIH Input HIGH Voltage VEE + 1200 VCC VEE + 1200 VCC VEE + 1200 VCC mV VIL Input LOW Voltage VEE VIH − 150 VEE VIH − 150 VEE VIH − 150 mV Vth Input Threshold Voltage Range (Note 20) VEE + 950 VCC – 75 VEE + 950 VCC – 75 VEE + 950 VCC – 75 mV 150 2600 150 2600 150 260 mV −1300 −1420 −1300 −1420 −1300 mV VISE Single-Ended Input Voltage (VIH – VIL) VBB NECL Output Voltage Reference −1420 −1360 −1360 −1360 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 & 8) (Note 21) VIHD Differential Input HIGH Voltage VEE + 1200 VCC VEE + 1200 VCC VEE + 1200 VCC mV VILD Differential Input LOW Voltage VEE VIHD − 75 VEE VIHD − 75 VEE VIHD − 75 mV VID Differential Input Voltage (VIHD – VILD) 75 2600 75 2600 75 2600 mV VEE + 1200 0 VEE + 1200 0 VEE + 1200 0 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 22) (Figure 9) IIH Input HIGH Current (@VIH) 30 100 30 100 30 100 mA IIL Input LOW Current (@VIL) 25 50 25 50 25 50 mA VMM − 150 VMM VMM + 150 VMM − 150 VMM VMM + 150 VMM − 150 VMM VMM + 150 mV 45 50 55 45 50 55 45 50 55 W LVCMOS CONTROL PIN (Note 23) VMM CMOS Output Voltage Reference VCC/2 TERMINATION RESISTORS RTIN Internal Input Termination Resistor Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC − 2.0 V. 19. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 20. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2. 21. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. 22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 23. VMM typical = |VCC − VEE|/2 + VEE = VMMT http://onsemi.com 7 NBSG16 Table 8. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V) −40°C Symbol Characteristic fmax Maximum Input Clock Frequency (See Figure 3. fmax/JITTER) (Note 24) tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 25) tJITTER RMS Random Clock Jitter Min Typ 10.7 12 90 110 130 3 0.2 tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 26) Output Rise/Fall Times @ 1 GHz (20% − 80%) Max 85°C Min Typ Max Min Typ 10.7 12 100 120 140 15 3 2 0.2 Max 10.7 12 95 125 145 ps 15 3 15 ps 2 0.2 2 Unit GHz ps fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C 8 75 Q, Q 20 30 8 2600 75 50 20 30 8 2600 75 50 20 30 2600 mV 50 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 24. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%). 25. See Figure 10. tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform. 26. VINPP(max) cannot exceed VCC − VEE http://onsemi.com 8 NBSG16 700 600 8.5 7.5 500 6.5 OUTPUT AMP 5.5 400 4.5 Q Q 300 3.5 200 2.5 1.5 100 RMS JITTER 0.5 0 −0.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 INPUT FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) X = 17ps/Div Y = 70 mV/Div Figure 4. 10.709 Gb/s Diagram (3.0 V, 255C) http://onsemi.com 9 JITTEROUT ps (RMS) OUTPUT VOLTAGE AMPLITUDE (mV) 9.5 NBSG16 IN VIH Vth IN VIL IN IN Vth Figure 5. Differential Input Driven Single-Ended VCC Vthmax Figure 6. Differential Inputs Driven Differentially VIHmax VILmax Vth IN Vthmin VEE VIH Vth VIL IN IN VID = |VIHD(IN) − VILD(IN)| VIHD VILD VIHmin VILmin Figure 7. Vth Diagram Figure 8. Differential Inputs Driven Differentially VCC VIHDmax VIHCMRmax VILDmax VIHCMR VIHDtyp VID = VIHD − VILD IN IN VILDtyp VIHDmin VIHCMRmin VILDmin VEE Figure 9. VIHCMR Diagram http://onsemi.com 10 NBSG16 D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 10. AC Reference Measurement Q Zo = 50 W D Receiver Device Driver Device Q Zo = 50 W D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 11. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NBSG16MNG QFN-16 (Pb-Free / Halide-Free) 123 Units / Tube NBSG16MNR2G QFN-16 (Pb-Free / Halide-Free) 3000 / Tape & Reel NBSG16MNHTBG QFN-16 (Pb-Free / Halide-Free) 100 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 11 NBSG16 PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE F D ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ PIN 1 LOCATION 0.10 C 2X L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉÉ ÉÉÉ TOP VIEW DETAIL B 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L EXPOSED Cu 0.10 C 2X A B (A3) ÉÉ ÉÉ ÇÇ MOLD CMPD A3 A1 DETAIL B A 0.05 C ALTERNATE CONSTRUCTIONS NOTE 4 A1 SIDE VIEW C SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.18 0.24 0.30 3.00 BSC 1.65 1.75 1.85 3.00 BSC 1.65 1.75 1.85 0.50 BSC 0.18 TYP 0.30 0.40 0.50 0.00 0.08 0.15 RECOMMENDED SOLDERING FOOTPRINT* 16X 0.10 C A B 16X L DETAIL A 0.58 PACKAGE OUTLINE D2 8 4 1 9 2X E2 16X 2X 1.84 3.30 K 1 16X 16 e e/2 BOTTOM VIEW 0.30 16X b 0.50 PITCH 0.10 C A B 0.05 C NOTE 3 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NBSG16), may be covered by U.S. patents including 6,362,644. There may be other patents pending. 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