NTHS4101P 20 V, P−Channel Power MOSFET ChipFET Single Package Features • Offers an Ultra Low RDS(on) Solution in the ChipFET Package • Miniature ChipFET Package 40% Smaller Footprint than TSOP−6 • • • • making it an Ideal Device for Applications where Board Space is at a Premium Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin Environments such as Portable Electronics Designed to Provide Low RDS(on) at Gate Voltage as Low as 1.8 V, the Operating Voltage used in many Logic ICs in Portable Electronics Simplifies Circuit Design since Additional Boost Circuits for Gate Voltages are not Required Operated at Standard Logic Level Gate Drive, Facilitating Future Migration to Lower Levels using the same Basic Topology http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 21 m @ −4.5 V −20 V −4.8 A 30 m @ −2.5 V 42 m @ −1.8 V S G Applications • Optimized for Battery and Load Management Applications in • • D Portable Equipment such as MP3 Players, Cell Phones, Digital Cameras, Personal Digital Assistant and other Portable Applications Charge Control in Battery Chargers Buck and Boost Converters P−Channel MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS −20 Vdc Gate−to−Source Voltage − Continuous VGS 8.0 Vdc Drain Current − Continuous − 5 seconds ID ID −4.8 −6.7 A Total Power Dissipation Continuous @ TA = 25°C (5 sec) @ TA = 25°C Continuous @ 85°C (5 sec) @ 85°C PD Continuous Source Current Is −4.8 RJA RJA 50 95 TL 260 Rating Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds PIN CONNECTIONS MARKING DIAGRAM D 8 1 D 1 8 D 7 2 D 2 7 D 6 3 D 3 6 S 5 4 G 4 5 W 1.3 2.5 0.7 1.3 C6 Thermal Resistance (Note 1) Junction−to−Ambient, 5 sec Junction−to−Ambient, Continuous ChipFET CASE 1206A Style 1 A °C/W C6 = Specific Device Code ORDERING INFORMATION °C 1. When surface mounted to a 1″ x 1″ FR4 board. Package Shipping† NTHS4101PT1 ChipFET 3000 Tape / Reel NTHS4101PT1G ChipFET (Pb−free) 3000 Tape / Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2003 October, 2003 − Rev. 0 1 Publication Order Number: NTHS4101P/D NTHS4101P ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Typ Max Unit V(Br)DSS VGS = 0 Vdc, ID = −250 Adc −20 − − Vdc Gate−Body Leakage Current Zero IGSS VDS = 0 Vdc, VGS = 8.0 Vdc − − 100 nAdc Zero Gate Voltage Drain Current IDSS VDS = −16 Vdc, VGS = 0 Vdc VDS = −16 Vdc, VGS = 0 Vdc, TJ = 85°C − − − − −1.0 −5.0 Adc Gate Threshold Voltage VGS(th) VDS = VGS, ID = −250 Adc −0.45 − −1.5 Vdc Static Drain−to−Source On−Resistance RDS(on) VGS = −4.5 Vdc, ID = −4.8 Adc VGS = −2.5 Vdc, ID = −4.2 Adc VGS = −1.8 Vdc, ID = −1.0 Adc − − − 21 30 42 34 40 52 m Forward Transconductance gFS VDS = −5.0 Vdc, ID = −4.8 Adc − 15 − S Diode Forward Voltage VSD IS = −4.8 Adc, VGS = 0 Vdc − −0.8 −1.2 V Input Capacitance Ciss − 2100 − pF Output Capacitance Coss VDS = −16 Vdc VGS = 0 V f = 1.0 1 0 MHz − 290 − Transfer Capacitance Crss − 200 − Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 2) Temperature Coefficient (Positive) ON CHARACTERISTICS (Note 2) DYNAMIC CHARACTERISTICS SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge td(on) VDD = −16 Vdc − 8.0 − tr VGS = −4.5 Vdc − 28 − td(off) ID = −4.5 Adc − 75 − tf RG = 2.5 − 60 − Qg VGS = −4.5 Vdc − 25 35 Qgs ID = −4.5 Adc − 4.0 − Qgd VDS = −16 Vdc (Note 3) − 7.0 − 2. Pulse Test: Pulse Width = 250 s, Duty Cycle = 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns nC NTHS4101P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) −1.8 V 8 7 6 5 −1.6 V 4 3 2 −1.4 V 1 1 0 2 3 4 5 9 8 7 6 5 4 125°C 3 25°C 2 TJ = −55°C 1 −1.2 V 0 0 7 6 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.5 2.5 1 1.5 2 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0 3 1.5 0.1 VGS = −4.5 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) VGS = −1.8 V 0.08 0.06 0.04 VGS = −2.5 V 0.02 VGS = −4.5 V 2 4 8 10 12 −ID, DRAIN CURRENT (AMPS) 6 14 1.3 1.1 0.9 0.7 0.5 −50 0 16 −25 0 25 75 100 125 Figure 4. On−Resistance Variation with Temperature 10000 VGS = 0 V TJ = 125°C 1000 TJ = 100°C 100 10 TJ = 25°C 1 0.1 0 50 TJ, JUNCTION TEMPERATURE (°C) Figure 3. On−Resistance vs. Drain Current and Gate Voltage −IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE () 10 TJ = 25°C VGS = −10 V to −2.4 V 9 −ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS) 10 2 4 6 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 8 150 NTHS4101P 5000 VDS = 0 V C, CAPACITANCE (pF) 4500 VGS = 0 V −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) TJ = 25°C 4000 3500 3000 2500 Ciss Crss 2000 1500 1000 Coss 500 0 −6 −4 −2 0 2 −VGS −VDS 4 8 6 10 12 14 16 18 20 5 QT 4 3 2 1 ID = −4.5 A TJ = 25°C 0 0 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 3 21 15 18 6 9 12 Qg, TOTAL GATE CHARGE (nC) 24 27 Figure 7. Gate−to−Source and Drain−to−Source Voltage vs. Total Gate Charge Figure 6. Capacitance Variation 1000 5 100 −IS, SOURCE CURRENT (AMPS) VDD = −16 V ID = −4.5 A VGS = −4.5 V td(off) tf tr 10 td(on) 1 1 10 VGS = 0 V TJ = 25°C 4 3 2 1 0 0.4 100 RG, GATE RESISTANCE (OHMS) 0.5 0.6 10 0.1 0.01 0.1 0.8 0.9 1.0 Figure 9. Diode Forward Voltage vs. Current 100 1 0.7 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 8. Resistive Switching Time Variation vs. Gate Resistance −I D, DRAIN CURRENT (AMPS) t, TIME (ns) Q2 Q1 10 s 100 s 1 ms VGS = 8 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc 10 1 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 10. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 100 NTHS4101P PACKAGE DIMENSIONS ChipFET CASE 1206A−03 ISSUE E A 8 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 7. 1206A−01 AND 1206A−02 OBSOLETE. NEW STANDARD IS 1206A−03. M 6 K 5 S 5 6 7 8 4 3 2 1 B 1 2 3 4 L D J G STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. C 0.05 (0.002) DIM A B C D G J K L M S DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.20 0.28 0.42 0.55 BSC 5 ° NOM 1.80 2.00 INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.011 0.017 0.022 BSC 5 ° NOM 0.072 0.080 SOLDER FOOTPRINT* 2.032 0.08 2.032 0.08 0.457 0.018 0.635 0.025 1.727 0.068 0.457 0.018 0.178 0.007 0.711 0.028 0.711 0.028 0.66 0.026 0.66 0.026 Figure 11. Basic SCALE 20:1 Figure 12. Style 1 *For information on soldering specifications, please refer to our Soldering Reference Manual, SOLDERRM/D. http://onsemi.com 5 mm inches NTHS4101P ChipFET is a trademark of Vishay Siliconix ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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