NTHS5441 Power MOSFET −20 V, −5.3 A, P−Channel ChipFET] Features • • • • • Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature ChipFET Surface Mount Package Pb−Free Package is Available http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX −20 V 46 mW @ −4.5 V −5.3 A S Applications • Power Management in Portable and Battery−Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards G MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol 5 sec Steady State Drain−Source Voltage VDS −20 V Gate−Source Voltage VGS "12 V Continuous Drain Current (TJ = 150°C) (Note 1) TA = 25°C TA = 85°C ID IS Operating Junction and Storage Temperature Range 1 A −3.9 A PD MARKING DIAGRAM PIN CONNECTIONS W 2.5 1.3 TJ, Tstg ChipFET CASE 1206A STYLE 1 1.3 0.7 °C −55 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). D 8 1 D 1 D 7 2 D 2 D 6 3 D 3 S 5 4 G 4 8 A3 MG G Maximum Power Dissipation (Note 1) TA = 25°C TA = 85°C −5.3 8 −3.9 −2.8 "20 IDM Continuous Source Current (Note 1) P−Channel MOSFET A −5.3 −3.8 Pulsed Drain Current D Unit 7 6 5 A3 = Specific Device Code M = Month Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Package Shipping† NTHS5441T1 ChipFET 3000/Tape & Reel NTHS5441T1G ChipFET (Pb−Free) 3000/Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2005 July, 2005 − Rev. 13 1 Publication Order Number: NTHS5441T1/D NTHS5441 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction−to−Ambient (Note 2) t v 5 sec Steady State RqJA Maximum Junction−to−Foot (Drain) Steady State RqJF Typ Max 40 80 50 95 15 20 Unit °C/W °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min VGS(th) VDS = VGS, ID = −250 mA −0.6 Gate−Body Leakage IGSS Zero Gate Voltage Drain Current IDSS Typ Max Unit −1.2 V VDS = 0 V, VGS = "12 V "100 nA VDS = −16 V, VGS = 0 V −1.0 mA VDS = −16 V, VGS = 0 V, TJ = 85°C −5.0 Static Gate Threshold Voltage On−State Drain Current (Note 3) ID(on) VDS v −5.0 V, VGS = −4.5 V −20 Drain−Source On−State Resistance (Note 3) rDS(on) VGS = −3.6 V, ID = −3.7 A VGS = −4.5 V, ID = −3.9 A − − Forward Transconductance (Note 3) Diode Forward Voltage (Note 3) A W 0.050 0.046 0.06 − VGS = −2.5 V, ID = −3.1 A 0.070 0.083 gfs VDS = −10 V, ID = −3.9 A 12 VSD IS = −2.1 A, VGS = 0 V −0.8 −1.2 V 9.7 22 nC mhos Dynamic (Note 4) Total Gate Charge QG Gate−Source Charge QGS Gate−Drain Charge QGD Input Capacitance Ciss VDS = −10 V, VGS = −4.5 V, ID = −3.9 A 1.2 3.6 pF 710 VDS = −5.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz Output Capacitance Coss Reverse Transfer Capacitance Crss 140 Turn−On Delay Time td(on) 14 30 22 55 42 100 35 70 30 60 Rise Time Turn−Off Delay Time tr td(off) Fall Time tf Source−Drain Reverse Recovery Time trr VDD = −10 V, RL = 10 W ID ^ −1.0 A, VGEN = −4.5 V, RG = 6 W IF = −1.1 A, di/dt = 100 A/ms 2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 400 ns NTHS5441 TYPICAL ELECTRICAL CHARACTERISTICS −3.5 V TJ = 25°C 16 −4.5 V −4 V −2.5 V 12 8 −2 V 4 TJ = −55°C 16 25°C 125°C 12 8 4 VGS = −1.5 V 0 0 0 0.5 1 1.5 2 2.5 3 0 1.5 2 2.5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.2 ID = −3.9 A TJ = 25°C 0.15 0.1 0.05 0 0 1 0.5 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1 2 4 3 5 TJ = 25°C 0.15 VGS = 2.5 V 0.1 VGS = 3.6 V 0.05 VGS = 4.5 V 0 2 6 10 14 18 −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.6 ID = −3.9 A VGS = −4.5 V 1.4 1.2 1 0.8 0.6 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature http://onsemi.com 3 3 0.2 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 20 −3 V −ID, DRAIN CURRENT (AMPS) −5 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (AMPS) 20 150 20 NTHS5441 TJ = 25°C VGS = 0 C, CAPACITANCE (pF) 1200 900 Ciss 600 Coss 300 Crss 0 0 4 8 12 20 16 −VDS, DRAIN−TO−SOURCE VOLTAGE () NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE Figure 6. Capacitance Variation 5 11 QG 10 9 4 8 7 3 6 QGS 5 QGD 2 4 ID = −3.9 A TJ = 25°C QGD/QGS = 3.0 1 0 0 1 2 3 4 5 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1500 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL ELECTRICAL CHARACTERISTICS 6 7 8 9 3 2 1 0 10 QG, TOTAL GATE CHARGE (nC) Figure 7. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 1 Duty Cycle = 0.5 0.2 0.1 0.1 PDM 0.05 t1 0.02 t2 DUTY CYCLE, D = t1/t2 PER UNIT BASE = RqJA = 80°C/W TJM − TA = PDMZqJA(t) SURFACE MOUNTED Single Pulse 0.01 0.001 0.01 0.1 1 10 SQUARE WAVE PULSE DURATION (sec) Figure 8. Normalized Thermal Transient Impedance, Junction−to−Ambient 5 −IS, SOURCE CURRENT (AMPS) 0.0001 4 VGS = 0 V TJ = 25°C 3 2 1 0 0.1 0.3 0.5 0.7 0.9 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Diode Forward Voltage versus Current http://onsemi.com 4 100 1000 NTHS5441 PACKAGE DIMENSIONS ChipFET] CASE 1206A−03 ISSUE G D 8 7 q 6 L 5 HE 5 6 7 8 4 3 2 1 E 1 2 3 e1 4 b NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A b c D E e e1 L HE q c e A MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5° NOM MIN 1.00 0.25 0.10 2.95 1.55 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.014 0.011 0.071 0.075 5° NOM MIN 0.039 0.010 0.004 0.116 0.061 0.05 (0.002) SOLDERING FOOTPRINT* 2.032 0.08 2.032 0.08 0.457 0.018 0.635 0.025 1.727 0.068 0.457 0.018 0.711 0.028 0.66 0.026 SCALE 20:1 0.178 0.007 0.711 0.028 mm Ǔ ǒinches 0.66 0.026 Basic SCALE 20:1 Styles 1 and 4 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 mm Ǔ ǒinches MAX 0.043 0.014 0.008 0.122 0.067 0.017 0.079 NTHS5441 ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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