ETC TXC-05802BIPQ

CUBIT®-Pro Device
CellBus® Bus Switch
TXC-05802B
FEATURES
DESCRIPTION
• UTOPIA and 16-Bit (ATM or PHY) Layer cell interfaces
• Inlet-side address translation and routing header
insertion, using external SRAM of up to 256 kB
• Programmable OAM-cell and RM-cell routing
• CellBus bus access request, grant reception and
bus transmission
• CellBus bus cell reception and address recognition
• Outlet cell queuing: various modes
• Ability to insert GFC field in real time
• Ability to insert FECN indication, under programmable conditions
• Ability to send and receive cells for control purposes over same CellBus bus
• Cell insertion and extraction via microprocessor
port
• Master bus arbiter and frame pulse generator included in each CUBIT-Pro, with enabling pin
• Improved internal GTL+ transceivers for CellBus
bus connection
• Interface port to translation table in SRAM
• Microprocessor control port, selectable for Intel or
Motorola interface
• +5 V and +3.3 V power supplies (dual-supply operation) or single-supply +3.3 V operation
• 208-pin plastic quad flat package (28 x 28 mm)
CUBIT-ProTM is a single-chip solution for implementing
cost effective ATM access systems. It is based on the
CellBus® Bus Architecture (CellBus). Such systems are
constructed from a number of CUBIT-Pro devices, all
interconnected by a 37-line common bus, the CellBus
bus. When operating at a 38 MHz clock rate, a CellBus
bus system can handle 1 Gbit/s of net ATM cell bandwidth. CUBIT-Pro supports unicast and multicast transfers, and has all necessary functions for implementing a
switch: cell address translation, cell routing, and outlet
cell queuing.
The TXC-05802B has GTL+ drivers with improved slew
rate control. This ensures CellBus compatibility with new
generations of CellBus devices. The TXC-05802B is a
functional replacement for the TXC-05802 and is targeted for GTL+ applications. It can operate with dual 5 V
and 3.3 V supplies, or a single 3.3 V supply.
APPLICATIONS
•
•
•
•
•
•
•
•
xDSL Access Multiplexer
Remote Access Equipment
Cable Modem Access Multiplexer
ATM LAN hub
ATM multiplexer/concentrator
Small-stand-alone ATM switch
Add-Drop Ring Switch
Edge switching equipment
Translation RAM
Address
Cell Inlet
Cell Outlet
Data
Other
Data
Other
Clock, controls, test, etc.
18
8
Data
2
Control
8
4
8
8
CUBIT-Pro
37
CellBus Bus Switch
TXC-05802B
2
22
Address
8
8 Data
7
CellBus Bus Port (32-bit data)
Other CellBus bus-related signals
Controls and clock input
U.S. Patents No. 5,568,060; 5,901,146
Microprocessor Port
U.S. and/or foreign patents issued or pending
Copyright  2001 TranSwitch Corporation
CUBIT-Pro is a trademark of TranSwitch Corporation
TranSwitch, TXC, CellBus, CUBIT and SALI-25C are registered trademarks of TranSwitch Corporation
TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484
Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
Document Number:
TXC-05802B-MB
Ed. 3, February 2001
•
USA
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
TABLE OF CONTENTS
Section
Page
List of Figures .................................................................................................................................................. 3
Block Diagram.................................................................................................................................................. 5
Operation ......................................................................................................................................................... 7
Introduction to CellBus Bus Architecture ................................................................................................... 7
CellBus Bus Operation ....................................................................................................................... 7
CellBus Bus Cell Routing ................................................................................................................... 9
CellBus Bus Status Signals and Monitoring ..................................................................................... 11
CUBIT-Pro Cell Inlet and Outlet Ports .................................................................................................... 11
8-Bit UTOPIA Mode - ATM and PHY Layer Emulation.................................................................... 12
Back-to-Back Mode ......................................................................................................................... 15
Byte Ordering for UTOPIA and Back-to-Back Modes...................................................................... 16
16-Bit Cell Interface Mode - ATM and PHY Layer Emulation.......................................................... 16
Word Ordering for 16-Bit Cell Interface Mode ................................................................................. 19
Traffic Management Functions ............................................................................................................... 19
Dynamic Generic Flow Control (GFC) Field Insertion ..................................................................... 19
Forward Explicit Congestion Notification (FECN)............................................................................ 20
Paralleling Cell Inlet/Outlet Ports for Redundancy .......................................................................... 21
Inlet-side Translation .............................................................................................................................. 22
Introduction...................................................................................................................................... 22
Translation RAM Connections......................................................................................................... 23
Translation RAM Control ................................................................................................................. 23
Translation RAM Organization ........................................................................................................ 23
Translation Procedure ..................................................................................................................... 25
Translation Record Formats ............................................................................................................ 27
Multicast Number Memory...................................................................................................................... 31
The CellBus Bus Interface ....................................................................................................................... 31
Operation with Internal GTL+ Transceivers..................................................................................... 31
Clock Source ................................................................................................................................... 32
Bus Arbiter Selection ....................................................................................................................... 32
Outlet-side Queue Management............................................................................................................. 32
Single Queue Operation .................................................................................................................. 32
Split-Queue Operation..................................................................................................................... 32
Microprocessor Interface ........................................................................................................................ 33
General Description......................................................................................................................... 33
Intel Mode........................................................................................................................................ 33
Motorola Mode................................................................................................................................. 34
Interrupts ......................................................................................................................................... 34
Control Queue Send and Receive................................................................................................... 36
Loopback Cell Send, Receive and Relay ............................................................................................... 38
Memory Map Reset States ..................................................................................................................... 39
Pin Diagram ................................................................................................................................................... 40
Pin Descriptions ............................................................................................................................................. 41
Absolute Maximum Ratings and Environmental Limitations ......................................................................... 47
Thermal Characteristics ................................................................................................................................. 47
Power Requirements ..................................................................................................................................... 47
Input, Output and Input/Output Parameters................................................................................................... 48
Timing Characteristics ................................................................................................................................... 51
Memory Map ................................................................................................................................................. 72
Memory Map Descriptions ............................................................................................................................. 74
TXC-05802B-MB
Ed. 3, February 2001
- 2 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Section
CUBIT-Pro
TXC-05802B
Page
Package Information ......................................................................................................................................
Ordering Information ......................................................................................................................................
Related Products............................................................................................................................................
Standards Documentation Sources ...............................................................................................................
List of Data Sheet Changes ...........................................................................................................................
Documentation Update Registration Form* ..............................................................................................
80
81
81
83
85
89
* Please note that TranSwitch provides documentation for all of its products. Customers who are using a
TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive
relevant updated and supplemental documentation as it is issued. They should also contact the Applications
Engineering Department to ensure that they are provided with the latest available information about the
product, especially before undertaking development of new designs incorporating the product.
LIST OF FIGURES
Figure
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Page
CUBIT-Pro TXC-05802B Block Diagram ...............................................................................................5
CellBus Bus Structure ...........................................................................................................................7
CellBus Bus Frame Format ...................................................................................................................8
CellBus Bus 16/32-User Modes - Frame Formats .................................................................................9
CellBus Bus Routing Header Formats .................................................................................................10
ATM Layer Emulation 8-Bit UTOPIA Mode Signal Connections and Operating Mode Selection ........13
PHY Layer Emulation 8-Bit UTOPIA Mode Signal Connections and Operating Mode Selection .......14
Back-to-Back Mode Signal Connections and Operating Mode Selection ...........................................15
Byte Ordering on Cell Inlet and Outlet in UTOPIA and Back-to-Back Modes .....................................16
ATM Layer Emulation 16-Bit Mode Signal Connections and Operating Mode Selection ....................17
PHY Layer Emulation 16-Bit Mode Signal Connections and Operating Mode Selection ....................18
Word Ordering on Cell Inlet and Outlet in 16-Bit Mode ......................................................................19
GFC Insertion on the Outlet Queue (GFCENA = 1) ...........................................................................19
Example of Congestion Indication in Single-Queue Mode (QM = 0) ..................................................20
Example of Congestion Indication in Split-Queue Mode (QM=1) .......................................................21
Translation RAM Connections ............................................................................................................23
Translation RAM Organization ............................................................................................................24
VCI Page 0 Organization (Bit OAMRMEN=1) .....................................................................................25
VPI Translation Record Formats .........................................................................................................27
VCI Translation Record Formats .........................................................................................................28
OAM F5 and RM-VCC Cell Routing (Bit OAMRMEN=1) ....................................................................29
OAM F4 and RM-VPC Cell Routing (Bit OAMRMEN=1) ....................................................................30
OAM/RM-Cells Translation Record Formats .......................................................................................30
Multicast Number Memory ..................................................................................................................31
External Circuit Requirements for GTL+ Transceivers ........................................................................31
Microprocessor Port Interface Connections ........................................................................................33
CUBIT-Pro Status Register at Address 05H .......................................................................................34
CUBIT-Pro Status Register at Address 08H .......................................................................................35
Transmit and Receive Control Cell Formats .......................................................................................37
Loading the Loopback Registers ........................................................................................................38
CUBIT-Pro TXC-05802B Pin Diagram ................................................................................................40
Translation RAM Timing - Read from RAM .........................................................................................52
- 3 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Figure
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Page
Translation RAM Timing - Write to RAM ............................................................................................. 53
Timing of UTOPIA (ATM Layer Emulation) Cell Inlet Interface ........................................................... 54
Timing of UTOPIA (PHY Layer Emulation) Cell Inlet Interface ........................................................... 55
Timing of UTOPIA (ATM Layer Emulation) Cell Outlet Interface ......................................................... 56
Timing of UTOPIA (PHY Layer Emulation) Cell Outlet Interface ........................................................ 57
Timing of 16-Bit (ATM Layer Emulation) Cell Inlet Interface ............................................................... 58
Timing of 16-Bit (PHY Layer Emulation) Cell Inlet Interface ............................................................... 59
Timing of 16-Bit (ATM Layer Emulation) Cell Outlet Interface ............................................................ 60
Timing of 16-Bit (PHY Layer Emulation) Cell Outlet Interface ............................................................ 61
Timing of Back-to-Back Cell Receive Interface .................................................................................. 62
Timing of Back-to-Back Cell Transmit Interface .................................................................................. 63
GFC Field Insertion Timing ................................................................................................................ 64
CellBus Bus Timing ............................................................................................................................. 65
CellBus Bus Frame Position, 16-User and 32-User Applications ........................................................ 66
Intel Microprocessor Read Cycle Timing ............................................................................................ 67
Intel Microprocessor Write Cycle Timing ............................................................................................ 68
Motorola Microprocessor Read Cycle Timing .................................................................................... 69
Motorola Microprocessor Write Cycle Timing .................................................................................... 70
Microprocessor Interrupt Timing ......................................................................................................... 71
CUBIT-Pro TXC-05802B 208-Pin Plastic Quad Flat Package ............................................................ 80
CUBIT-Pro TXC-05802B and Related Product Applications in ATM Access Switching ...................... 82
TXC-05802B-MB
Ed. 3, February 2001
- 4 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
BLOCK DIAGRAM
PHYEN
CID(7-0)
Reset
External Translation RAM Port
and Test
Address TRA(17-0)
Data TRD(7-0)
Translation
6
Control
TROE
Inlet Queue
TRWE
8
CBDISABLE
VREF
Data Cell Queue
4 cells
CellBus Bus Port
CICLAV
Control Queue
1 cell
Cell
Inlet
Port
CICLK
32
CBD(31-0)
Loopback Queue
1 cell
CIENB
CISOC
CellBus
Bus
Interface
Logic
Outlet Queue
CBRC
CBWC
CBF
CBACK
CBCONG
Loopback Queue
1 cell
Synchronization FIFO
8
COD(7-0)
3 cells
Data Cell Queue
123
cells
Cell
Address
Screen
Control Queue
4 cells
COCLAV
Cell
Outlet
Port
COCLK
COENB
Bus
Arbiter
and
Frame
Pulse
Generator
COSOC
GFC(3-0)
Microprocessor Interface
4
8
FRCABRCNG
8
Address Data INT/ RDY/ RD or WR SEL PCLK
LCLOCK A(7-0) D(7-0)
IRQ DTACK RD/WR
MOTO
12
ENARB
Other Controls
Figure 1. CUBIT-Pro TXC-05802B Block Diagram
A block diagram of the CUBIT-Pro device is shown in Figure 1. Further information on device operation and
the interfaces to external circuits is provided below in the following Operation section.
On the cell inlet side of the CUBIT-Pro is circuitry associated with accepting cells from the line and passing
them to the CellBus bus with an appropriate header. The Cell Inlet Port block is pin-selectable to be compliant
with either the ATM Forum UTOPIA (Universal Test and Operations Physical Interface for ATM) interface, or a
TranSwitch 16-Bit interface. Incoming cells may carry a CellBus Routing Header and translated outgoing
VPI/VCI address, the translation function having been performed externally, or this address translation and
routing header insertion may be done by the CUBIT-Pro Translation Control block. Translation and routing
header tables to support this function are contained in an external static RAM (up to 256k x 8 bits). They support VPI and/or VPI/VCI address translation. The incoming cells then pass through a FIFO queue in the Inlet
Queue block to the CellBus Bus Port via the CellBus Bus Interface Logic block. When there is a cell in this 4-cell
data cell queue, the CUBIT-Pro makes a bus access request, and waits for a grant from the Bus Arbiter and
Frame Pulse Generator block of the one CUBIT-Pro device attached to the bus that has been enabled to per-
- 5 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
form these two functions. When a bus access grant is received, the CUBIT-Pro sends the cell to the bus, in
standard CellBus bus format. The cell can then be received by any connected CUBIT-Pro or CUBIT-Pros. In
addition to these incoming data cells, the CUBIT-Pro can also send Control cells from the local microprocessor
to the bus via the Microprocessor Interface block. Special cells of Loopback type received from the bus may
also be returned to the bus, re-directed back to the CUBIT-Pro which launched the original Loopback cell. Both
the Control cells and the Loopback cells have 1-cell inlet queues.
On the cell outlet side, cells of proper unicast address, broadcast address or selected multicast address,
received from the bus via the CellBus Bus Interface Logic block, are recognized by the Cell Address Screen
block and routed into a FIFO structure in the Outlet Queue block. The unicast address is unique per device, set
by device straps. Each CUBIT-Pro may be programmed to accept cells associated with multicast sessions.
From zero up to the full 256 multicast sessions may be accepted independently by each CUBIT-Pro on the
bus. Data cells from the bus go into a 123-cell outlet data cell queue structure. Control cells and Loopback
cells arriving from the bus are routed to the 4-cell outlet control queue, and the 1-cell outlet loopback queue,
respectively. The outlet data cell FIFO structure can be treated as a single 123-cell queue, or it can be subdivided into four individual queues for traffic of different service types. The four-queue split is typically into
high-speed control data cells, CBR cells, VBR cells, and ABR cells, in decreasing order of outlet service priority. This allows for delay minimization of critical service types, and for more efficient traffic management. At the
cell outlet, provisions are made for insertion of an outgoing Generic Flow Control (GFC) field and an Explicit
Forward Congestion Indication (EFCI) bit.
TXC-05802B-MB
Ed. 3, February 2001
- 6 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
CUBIT-Pro
TXC-05802B
OPERATION
INTRODUCTION TO CellBus BUS ARCHITECTURE
CellBus Bus Operation
The CUBIT-Pro is a versatile CMOS VLSI device for implementing ATM switching functions. Various ATM cell
switching or multiplexing structures can be formed by interconnection of a number of CUBIT-Pro devices over
a 37-line parallel bus with 32 data bits, the CellBus bus. Since the interconnect structure is a bus, communications between any of the devices on the bus is possible. Each cell placed onto the CellBus bus by a CUBIT-Pro
device can be routed either to one single CUBIT-Pro (unicast addressing), or to multiple CUBIT-Pro devices
(multicast or broadcast addressing). Depending upon the needs of an application, up to 32 CUBIT-Pro devices
may be interconnected on one CellBus bus. With a maximum bus frequency of more than 38 MHz, the raw
bandwidth of the CellBus bus exceeds 1 Gbit/s.
Enabled
CUBIT-Pro’s
Bus
Arbiter
and
Frame
Pulse
Generator
Data (32)
Clock (2)
Frame
Acknowledge
Congestion Indicator
CUBIT-Pro
CUBIT-Pro
CUBIT-Pro
Figure 2. CellBus Bus Structure
The CellBus bus, shown in Figure 2, is a shared bus, and can be implemented either on a single circuit card, or
in a backplane configuration among multiple circuit cards. Since multiple CUBIT-Pros share the same bus, bus
access contention must be resolved. This access contention is resolved by use of a central arbitration function.
CUBIT-Pros will request bus access, and the central Bus Arbiter will grant access back, in response. The circuitry for this Bus Arbiter is included inside the CUBIT-Pro device. Any one CUBIT-Pro in a system may be
selected to perform the bus arbitration function by setting its ENARB pin low.
- 7 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Cycle
Number
Request
0
31
16 15
0
16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1
b a b a b a b a b a b a b a b a b a b a b a b a b a b a b a b a
1
2
Cell
Body
(14 cycles)
Grant
CellBus Routing Header
GFC
Tandem Routing Header (Optional)
VPI
VCI
PT
3
Byte 0
Byte 1
Byte 2
Byte 3
4
Byte 4
Byte 5
Byte 6
Byte 7
5
Byte 8
Byte 9
Byte 10
Byte 11
6
Byte 12
Byte 13
Byte 14
Byte 15
7
Byte 16
Byte 17
Byte 18
Byte 19
8
Byte 20
Byte 21
Byte 22
Byte 23
9
Byte 24
Byte 25
Byte 26
Byte 27
10
Byte 28
Byte 29
Byte 30
Byte 31
11
Byte 32
Byte 33
Byte 34
Byte 35
12
Byte 36
Byte 37
Byte 38
Byte 39
13
Byte 40
Byte 41
Byte 42
Byte 43
14
Byte 44
Byte 45
Byte 46
Byte 47
15
BIP-8
Unused
G G
P E
R N
C
L
P
Granted
Terminal
Number
Figure 3. CellBus Bus Frame Format
The CellBus bus has a framed format 16 clock cycles long and 32 bits wide, which is illustrated in Figure 3. The
first cycle of each frame is the Request cycle (Cycle 0), during which those CUBIT-Pros which have a cell to
send to the bus each make an access request by asserting one or two assigned bits on the bus. The CBF,
CBACK and CBCONG signals are asserted during a Request cycle. The device address assigned to each
CUBIT-Pro by device straps (UA(4-0) at pins 2-6) uniquely specifies which two bits it may assert during the bus
Request cycle time. For example, UA(4-0) = HHHHH selects bits 1a and 1b. By asserting one of its assigned
bits, or the other, or both, access requests of three different priorities may be made (controlled via bits P1, P0
in memory address 0AH). A central Bus Arbiter accepts these access requests, executes an arbitration algorithm (highest priority served first, round-robin within each priority), and issues a bus access grant during the
final cycle of the frame, the Grant cycle (Cycle 15). Each grant issued by the arbiter is for one CUBIT-Pro to
send one cell to the bus. Whichever CUBIT-Pro is issued a grant during a Grant cycle will transmit its cell during the 14 Cell Body clock cycles of the next bus frame, and will also drive an 8-bit cell parity check during the
Grant cycle of that bus frame. Each cell sent can be of unicast, multicast, or broadcast type. CUBIT-Pros will
accept single-address cells routed to an address defined by their address straps, all broadcast cells, and
selected multicast cells. Thus, cells may be sent from any one CUBIT-Pro to any one CUBIT-Pro or to multiple
CUBIT-Pros.
The CUBIT-Pro can be operated in either 16-user or 32-user mode, selectable via the U32 pin, as shown in
Figure 4. For the 16-user mode the CellBus bus frame is identical to Figure 3. However, in 32-user mode the
frame is duplicated, so that an odd and even frame are provided. The distinction between the two frames is
TXC-05802B-MB
Ed. 3, February 2001
- 8 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
given by the location of the frame pulse. The cycles for both frames are the same, except for the meaning of
the Request cycle. The Request cycle in the even frame coincides with the frame pulse, whereas in the odd
frame the pulse is not present. Furthermore, in the even frame CUBIT-Pros 0-15 (lower 16 users) request
access to the bus and in the odd frame CUBIT-Pros 16-31 (upper 16 users) request access to the bus. The full
bus bandwidth is available to be shared among all the users on the bus in either 16 or 32-user mode.
32-User Mode
16-User Mode
Framing Pulse
Framing Pulse
Request
Users 1-16
Request
Grant
Request
Users 1-16
Users 17-32
Cell body
Cell body
Grant
Request
Even
Cell body
Cell body
Grant
Request
Users 1-16
Grant
Request
Users 1-16
Odd
Users 1-16
Figure 4. CellBus Bus 16/32-User Modes - Frame Formats
To detect CellBus bus errors, a BIP-8 (Bit Interleave Parity byte) is calculated over the 54-byte data field that
extends from the first Tandem Routing Header byte through the final payload data byte, Byte 47. The BIP-8 is
generated by the transmitting CUBIT-Pro using the following algorithm. The first byte of the Tandem Routing
Header is exclusive-or gated with an all-ones byte, creating a starting seed value. This seed value is then
exclusive-or gated with the second byte of the Tandem Routing Header. The result is then exclusive-or gated
with the next byte in the cell. This process is repeated with every successive byte in the cell, through Byte 47 of
the payload, and the final result is transmitted as the BIP-8 byte in cycle 15. The receiving CUBIT-Pro performs
the same process and compares the generated BIP-8 with the received BIP-8. If no errors are detected the
receiving CUBIT-Pro pulls CBACK low, acknowledging receipt of a cell. The CellBus Routing Header has its
own CRC-4 field and is not included in the BIP-8 calculation. A cell with a BIP-8 or CRC-4 error is discarded.
The only signals required to operate the bus which are not sourced by a CUBIT-Pro device are two transfer
clocks: write clock (CBWC) and read clock (CBRC). These clock signals are of the same frequency, but may
be slightly phase-offset to allow for reliable bus operation. The framing pulse used to define the bus frame
cycle is sent out by one of the CUBIT-Pros, and the arbitration function is also performed by the same
CUBIT-Pro. Each CUBIT-Pro contains the circuitry for both the Bus Arbiter and the Frame Pulse Generator.
Only one CUBIT-Pro will have this circuitry enabled, by setting control pin ENARB.
CellBus Bus Cell Routing
The CellBus bus architecture allows several types of cell routing from any one inlet port to the outlet ports of the
CUBIT-Pros on the CellBus bus:
• Point-to-Point Routing: In Unicast or Single Address cell routing a cell coming into an inlet port is transferred
to a single outlet port. The CUBIT-Pro can address a cell to itself, effectively implementing both the inlet and
outlet ports.
- 9 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
• Point-to-Multipoint (Broadcast): A cell coming into the inlet port can be routed to the outlet ports of all the
CUBIT-Pros on the CellBus bus.
• Point-to-Multipoint (Multicast): In multicast routing the cell arriving at the inlet port is sent to the subset of outlet ports that belong to the specific multicast session by means of selection in the receiving CUBIT-Pros.
For each of the routing methods the cells can be sent to different output queues according to whether the cell
is used as a data cell or as control/loopback cell. Furthermore, data cells can be selected to go to four different
data outlet queues: Control Data queue, Constant Bit Rate (CBR) queue, Variable Bit Rate (VBR) queue, and
Available Bit Rate (ABR) queue. The CUBIT-Pro can be programmed to receive cells into separate queues
(split-queue mode) or not (single-queue mode).
The encoding rules for the two-byte CellBus Bus Routing Header in Bits 31-16 of Cycle 1 are summarized in
Figure 5.
31
16 15
R R Q Q
A A A A A H H H H
0 0
0
1 0 1 0
4 3 2 1 0 3 2 1 0
16 15
_ _ _ _
A A A A A H H H H
0 1
0
4 3 2 1 0 3 2 1 0
0
Tandem Routing Header
31
31
0 0 0
_ _ _
31
0 0 1
_ _ _
1
16 15
A A A A A H H H H
4 3 2 1 0 3 2 1 0
16 15
_ _ _ _ _ H H H H
1
3 2 1 0
16 15
_ _ _
_ _ _ _ _ H H H H
0 1 1
1
3 2 1 0
Tandem Routing Header
1 0
16 15
R R MM MM MM MM H H H H
1 0 7 6 5 4 3 2 1 0 3 2 1 0
16 15
R R MM MM MM MM H H H H
1 1
1 0 7 6 5 4 3 2 1 0 3 2 1 0
Single Address_Control
0
Tandem Routing Header
Single Address_Loopback
0
Tandem Routing Header
31
31
Single Address_Data
0
Broadcast Address_Data
0
Tandem Routing Header
Broadcast Address_Control
0
Tandem Routing Header
31
Multicast Address_Data
0
Tandem Routing Header
Multicast Address_Control
Figure 5. CellBus Bus Routing Header Formats
CellBus Bus Routing Header Format
The CellBus Bus Routing Header contains the following fields, as shown in Figure 5:
R: Multi-PHY selector field (2 bits). Not interpreted by CUBIT-Pro currently (passed through intact). This field
is ignored.
Q: Queue selection field for split-queue mode (2 bits). 00 is outlet Control Data queue, 01 is Constant Bit Rate
(CBR) queue, 10 is Variable Bit Rate (VBR) queue, 11 is Available Bit Rate (ABR) queue. This coding is
only valid for data cells which contain Q1, Q0 fields in the header. For multicast and broadcast cell routing,
cells are routed to the VBR and CBR queues, respectively, when using split-queue mode.
A: CUBIT-Pro single address field (5 bits, for 32 addresses). A0 is the LSB. For example, A(4-0)=00000 is the
address value for the CUBIT whose five device identity straps UA(4-0) are all tied high (HHHHH).
M: Multicast number field (8 bits, for 256 multicast sessions). M0 is the LSB.
H: CRC-4 field. This 4-bit field (H3-H0) provides Routing Header error protection across the CellBus bus in
TXC-05802B-MB
Ed. 3, February 2001
- 10 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
CUBIT-Pro
TXC-05802B
both directions. It is calculated over the 12-bit word (X11-X0) in bits 31-20 of the Routing Header using the
following logic:
Η3 = (Χ7 ⊕ Χ9 ⊕ Χ3 ⊕ Χ10 ⊕ Χ8 ⊕ Χ5 ⊕ Χ2)
Η2 = (Χ6 ⊕ Χ8 ⊕ Χ2 ⊕ Χ9 ⊕ Χ7 ⊕ Χ4 ⊕ Χ1)
Η1 = (Χ5 ⊕ Χ7 ⊕ Χ1 ⊕ Χ8 ⊕ Χ6 ⊕ Χ3 ⊕ Χ0)
Η0 = (Χ8 ⊕ Χ10 ⊕ Χ11 ⊕ Χ4 ⊕ Χ9 ⊕ Χ6 ⊕ Χ3 ⊕ Χ0)
where ⊕ represents logical exclusive-or. For cells arriving from the CellBus bus, the CUBIT-Pro automatically
calculates the corresponding CRC-4 and sets to 1 the status bit CRCF (bit 7 in register 08H) if it is not the
same as that in bits H3-H0 of the received Routing Header. This status bit may be enabled to cause an interrupt signal to the microprocessor by setting to 1 the enable bit INTEN7 (bit 7 in register 09H). For cells supplied
to the cell inlet interface from an external source for transmission via the CellBus bus, the CRC-4 may either be
supplied in the input signal by use of external logic (as is required for the CUBIT device) or it may be generated
internally and inserted into the Routing Header by the CUBIT-Pro. Setting control bit CRC4EN to 1 (bit 3 in register 0EH) activates the internal CRC-4 insertion for all incoming cells (i.e., not only data cells, but also control
cells and loopback cells). When control bit CRC4I (bit 4 in register 0EH) is set to 1 the internally generated
CRC-4 is inverted for testing purposes. This bit has no effect on an externally-supplied CRC-4. For operation in
the CUBIT TXC-05801 mode with an externally-supplied CRC-4, bit CRC4EN should be set to 0, which is the
default at power-up/reset.
Tandem Routing Header Format
The two-byte Tandem Routing Header format in Bits 15-0 of Cycle 1 is the same as the CellBus Bus Routing
Header format, if it is to be used by a cascaded CellBus bus, or may conform to a different specification if it is
used by another system. The Tandem Routing Header is passed unchanged through the CellBus bus.
CellBus Bus Status Signals and Monitoring
The CUBIT-Pro provides the capability to monitor the activity on the CellBus bus. The essential signals that
determine whether the bus is active (in the absence of any cell traffic) are the clock signals and the frame
pulse.
The CellBus bus clocks (read and write) are generated externally to the CUBIT-Pro. If either of these clocks
fails, the entire bus will cease operation. The CUBIT-Pro provides the capability to detect the absence of clock
signal for more than the equivalent of 32 processor clock (PCLK) cycles. The failure detection is performed
independently for the CellBus Bus Read Clock (CBRC) and the CellBus Bus Write Clock (CBWC).
Two bits (register 05H bits CBLORC and CBLOWC) in the CUBIT-Pro memory map are used to indicate the
clock loss event. Once the event is detected, these bits in register 05H will remain set to one until the microprocessor reads the register, at which point the register will be cleared. These events can be used to generate a
microprocessor interrupt provided that the appropriate bits in the interrupt enable register (address 06H, bits
INTENA1 and INTENA0) are 1.
The second monitoring function concerns the detection of loss of frame. The detection mechanism looks for
two consecutive missing CellBus bus frame pulses in 32-user mode (U32 = Low), and four consecutive missing
CellBus bus frame pulses in 16-user mode. The CellBus Bus Read Clock must be present to detect Loss of
Frame Pulse. If CellBus Bus Read Clock is present and CellBus Bus Write Clock is not, then both CBLOWC and
CBLOF will be set. CBLOF can generate an interrupt to the microprocessor assuming that the appropriate
interrupt enable bit is 1 (register 06H, bit 2: INTENA2).
- 11 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
CUBIT-Pro CELL INLET AND OUTLET PORTS
The Cell Inlet and Outlet ports constitute the main interfaces for the cell traffic between the CUBIT-Pro and
other devices in either the upper ATM or Physical (PHY) Layers. Several interfaces are supported by the
device: UTOPIA 8-bit mode, TranSwitch 16-Bit mode and Back-to-Back (CUBIT-Pro-to-CUBIT-Pro interface).
The CUBIT-Pro can provide address translation if selected via the input pin TRAN (pin 154). If no translation is
selected, the external hardware must provide the CellBus Bus Routing Header, the Tandem Routing Header
(optional), and the ATM cell. If translation mode is selected, the hardware is required only to provide the ATM
cell and the CUBIT-Pro will perform the translation based on the information programmed into the attached
translation SRAM.
For all the modes the cell size is selectable via external pins LMODE2, LMODE1 and LMODE0 (pins 156, 157,
and 158, respectively), as described below. This feature permits the CUBIT-Pro to accommodate the requirements for different designs.
Additionally, the UTOPIA and 16-Bit modes can be selected to behave as either the master (ATM layer device)
or the slave (PHY layer device). The selection between ATM and PHY layer device for the UTOPIA and 16-Bit
modes is made via the PHYEN pin (pin 48), where a low enables PHY layer device operation.
The CUBIT-Pro allows the selection of the clock for the cell Inlet/Outlet operation from three different sources:
CellBus bus clocks (CBRC, pin 78 and CBWC, pin 77), processor clock (PCLK, pin 32), or an externally supplied clock (LCLOCK, pin 45). The clock selected will be used for the UTOPIA and 16-Bit ATM layer device
modes and the Back-to-Back (cell inlet clock) mode, for which the CUBIT-Pro sources the interface clock. For
all other modes the clock is an input to the CUBIT-Pro. The selection of the clock source for the cell interfaces
is performed via six control bits in register 0BH: CLKS1, CLKS0 and LINEDIV (3-0). The coding for the clock
selection is as follows:
CLKS1, CLKS0 = 0,0: Cell interface clock = CellBus bus clock divided by 2LINEDIV
CLKS1, CLKS0 = 0,1: Cell interface clock = LCLOCK clock divided by 2LINEDIV
CLKS1, CLKS0 = 1,0: Cell interface clock = PCLK clock divided by 2LINEDIV
CLKS1, CLKS0 = 1,1: Reserved, do not use
8-Bit UTOPIA Mode - ATM and PHY Layer Emulation
Typical signal connections for the CUBIT-Pro when operating in UTOPIA mode are illustrated in Figures 6 and
7, for ATM Layer and PHY Layer cell level handshake modes, respectively. The operating mode options for
UTOPIA mode are controlled by the input pins TRAN, PHYEN, LMODE2, LMODE1 and LMODE0, as indicated
in the tables of Figures 6 and 7. TRAN selects the internal translation mode, if asserted. In UTOPIA mode,
PHYEN determines whether the CUBIT-Pro emulates an ATM or PHY device. LMODE2, LMODE1 and
LMODE0 determine the cell inlet/outlet cell size.
When internal translation is used, the cell input and cell output is exactly that defined by UTOPIA, with 53-byte
inlet cells. For applications in which the internal translation function is not used, the timing and logical flow of
the cell input and cell output is still identical to that of UTOPIA, except that 57-byte or 55-byte inlet cells are
used, instead of 53. The additional bytes are the Routing Header bytes which would be inserted by the
CUBIT-Pro if the translation function were used, but are instead added by an external translation function. The
pin connections and the different inlet and outlet byte counts per cell in the various modes are shown in the
table of Figure 6 for ATM Layer emulation. Similarly, Figure 7 shows the pin connections and byte counts for
PHY Layer emulation.
The ABRENA pin must be held high or left floating (it has internal pull-up) for proper UTOPIA mode operation.
TXC-05802B-MB
Ed. 3, February 2001
- 12 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Figure 6. ATM Layer Emulation 8-Bit UTOPIA Mode Signal Connections and Operating Mode Selection
UTOPIA
PHY Layer
Device
PHY
Inlet
8
CID(7-0)
CISOC
RxData
RxSOC
CUBIT-Pro
CellBus bus
CBD(31-0)
CICLAV
CIENB
CICLK
GFC3
GFC2
GFC1
GFC0
COD(7-0)
COSOC
COCLAV
COENB
COCLK
RxClav
RxEnb
RxClk
GFC
Input
8
TxData
TxSOC
TxClav
TxEnb
TxClk
32
CBRC
CBWC
CBF
CBACK
CBCONG
Outlet
Microprocessor
PHYEN
TRAN
LMODE2
LMODE1
LMODE0
Operating Mode: Inlet
Operating Mode: Outlet
High
High
High
X
High
UTOPIA, 57 bytes: cell
plus CellBus Bus Routing
Header plus two bytes of
Tandem Routing Header
UTOPIA, 53-byte cell
High
High
High
High
Low
UTOPIA, 57 bytes: cell
plus CellBus Bus Routing
Header plus two bytes of
Tandem Routing Header
UTOPIA, 55 bytes: cell
plus Tandem Routing
Header
High
High
Low
Low
High
UTOPIA, 55 bytes: cell
plus CellBus Bus Routing
Header
UTOPIA, 53-byte cell
High
High
Low
Low
Low
UTOPIA, 55 bytes: cell
plus CellBus Bus Routing
Header
UTOPIA, 55 bytes: cell
plus Tandem Routing
Header
High
Low
High
High
High
UTOPIA, 53-byte cell
UTOPIA, 53-byte cell
High
Low
High
High
Low
UTOPIA, 53-byte cell
UTOPIA, 55 bytes: cell
plus Tandem Routing
Header
High
High
Low
High
High
Reserved
Reserved
High
Low
Low
High
High
Reserved
Reserved
High
Low
Low
High
Low
Reserved
Reserved
High
Low
Low
Low
High
Reserved
Reserved
Note: High = VDDIO = +5V; Low = VSS = Ground; X = Don’t Care
- 13 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Figure 7. PHY Layer Emulation 8-Bit UTOPIA Mode Signal Connections and Operating Mode Selection
UTOPIA
ATM Layer
Device
ATM
Inlet
8
TxData
TxSOC
CID(7-0)
CISOC
CUBIT-Pro
CellBus bus
CBD(31-0)
TxClav
TxEnb
TxClk
8
CICLAV
CIENB
CICLK
GFC3
GFC2
GFC1
GFC0
COD(7-0)
COSOC
COCLAV
COENB
COCLK
GFC
Input
RxData
RxSOC
RxClav
RxEnb
RxClk
32
CBRC
CBWC
CBF
CBACK
CBCONG
Outlet
Microprocessor
PHYEN
TRAN
LMODE2
LMODE1
LMODE0
Operating Mode: Inlet
Operating Mode: Outlet
Low
High
High
X
High
UTOPIA, 57 bytes: cell
plus CellBus Bus Routing
Header plus two bytes of
Tandem Routing Header
UTOPIA, 53-byte cell
Low
High
High
High
Low
UTOPIA, 57 bytes: cell
plus CellBus Bus Routing
Header plus two bytes of
Tandem Routing Header
UTOPIA, 55 bytes: cell
plus Tandem Routing
Header
Low
High
Low
Low
High
UTOPIA, 55 bytes: cell
plus CellBus Bus Routing
Header
UTOPIA, 53-byte cell
Low
High
Low
Low
Low
UTOPIA, 55 bytes: cell
plus CellBus Bus Routing
Header
UTOPIA, 55 bytes: cell
plus Tandem Routing
Header
Low
Low
High
High
High
UTOPIA, 53-byte cell
UTOPIA, 53-byte cell
Low
Low
High
High
Low
UTOPIA, 53-byte cell
UTOPIA, 55 bytes: cell
plus Tandem Routing
Header
Low
High
Low
High
High
Reserved
Reserved
Low
Low
Low
High
High
Reserved
Reserved
Low
Low
Low
High
Low
Reserved
Reserved
Low
Low
Low
Low
High
Reserved
Reserved
TXC-05802B-MB
Ed. 3, February 2001
- 14 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Back-to-Back Mode
The Back-to-Back mode is used to support interconnection of two CellBus buses, as shown in Figure 8. If pin
TRAN is low, each of the CUBIT-Pros has a translation memory connected, the cell address translation function is active, and the inlet cells are 53 bytes long. The cells from the outlet can either be 55 or 53 bytes long. If
55 bytes are selected, the cell will carry the Tandem Routing Header from the CellBus bus.
If TRAN is high, the translation function is not used. The transfers into the cell inlet will 55 bytes long. The two
initial bytes are presented to the CUBIT-Pro as the CellBus Bus Routing Header. The cell outlet can present
cells of either 55 or 53 bytes, whether or not internal translation is performed on the cell inlet side. If 55 bytes
are selected, the cell will carry the Tandem Routing Header from the CellBus bus.
The cell outlet will carry two extra bytes which are the Tandem Routing Header from the CellBus bus. These
two bytes are presented to the inlet port of the connected CUBIT-Pro, which uses them as a CellBus Bus Routing Header when it puts the cell on the bus.
In order to avoid re-transmission of multicast or broadcast cells from one CellBus bus to another, and back
again, a CUBIT-Pro which is operating in the Back-to-Back mode will reject all incoming broadcast and multicast cells which originated from its own inlet side.
The timing of this mode is similar to that for UTOPIA ATM Layer emulation mode, except that the directionality
of the COCLAV, COENB and COCLK signals is reversed, as shown in the connections diagrams of Figures 6
and 8.
The ABRENA pin must be held high or left floating (it has internal pull-up).
Inlet
CUBIT-Pro
CellBus Bus
CBD(31-0)
32
Outlet
CID(7-0)
CISOC
CICLAV
CIENB
CICLK
COD(7-0)
COSOC
COCLAV
COENB
COCLK
CUBIT-Pro
CellBus Bus
CBD(31-0)
CBRC
CBRC
CBWC
CBWC
CBF
CBF
CBACK
CBACK
CBCONG
32
CBCONG
COCLK
COENB
COCLAV
COSOC
COD(7-0)
CICLK
CIENB
CICLAV
CISOC
CID(7-0)
Outlet
Inlet
Microprocessor
Microprocessor
PHYEN
TRAN
LMODE2
LMODE1
LMODE0
Operating Mode: Inlet
Operating Mode: Outlet
X
High
High
Low
Low
Back-to-Back: 55 bytes, cell
plus two bytes of CellBus
Bus Routing Header
Back-to-Back: 55 bytes, cell
plus two bytes of Tandem
Routing Header
X
Low
High
Low
Low
Back-to-Back: 53-byte cell
Back-to-Back: 53-byte cell
X
Low
Low
Low
Low
Back-to-Back: 53-byte cell
Back-to-Back: 55 bytes, cell
plus two bytes of Tandem
Routing Header
X
High
Low
High
Low
Back-to-Back: 55 bytes, cell
plus two bytes of CellBus
Bus Routing Header
Back-to-Back: 53-byte cell
Figure 8. Back-to-Back Mode Signal Connections and Operating Mode Selection
- 15 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Byte Ordering for UTOPIA and Back-to-Back Modes
Byte ordering for the two cell inlet and outlet alternatives described above is illustrated in Figure 9.
First Byte
Transferred
TandemRH MSB
TandemRH LSB
CellBusBusRH MSB
CellBusBusRH MSB
TandemRH MSB
CellBusBusRH LSB
CellBusBusRH LSB
TandemRH LSB
GFC, VPI
GFC, VPI
GFC, VPI
GFC, VPI
VPI, VCI
VPI, VCI
VPI, VCI
VPI, VCI
VCI
VCI
VCI
VCI
VCI, PT, CLP
VCI, PT, CLP
VCI, PT, CLP
VCI, PT, CLP
HEC
HEC
HEC
HEC
Byte 0
Byte 0
Byte 0
Byte 0
Byte 1
Byte 1
Byte 1
Byte 1
Byte 2
Byte 2
Byte 2
Byte 2
5 bytes, header
48 bytes, data
Last Byte
Transferred
Byte 45
Byte 45
Byte 45
Byte 45
Byte 46
Byte 46
Byte 46
Byte 46
Byte 47
Byte 47
Byte 47
Byte 47
57 Bytes
Inlet
55 Bytes
Inlet
55 Bytes
Outlet
53 Bytes
Inlet, Outlet
Cell
Note: RH = Routing Header
Figure 9. Byte Ordering on Cell Inlet and Outlet in UTOPIA and Back-to-Back Modes
16-Bit Cell Interface Mode - ATM and PHY Layer Emulation
16-Bit cell interface mode can be selected to emulate an ATM Layer UTOPIA device, or alternatively to emulate a PHY Layer UTOPIA device, as shown in Figures 10 and 11, respectively.
16-Bit mode is enabled by setting device strap pin ABRENA low, with the settings of TRAN, LMODE2,
LMODE1 and LMODE0 selected according to the table in Figure 10 for ATM Layer emulation, or according to
the table in Figure 11 for PHY Layer emulation. The PHY Layer emulation is enabled with PHYEN.
The timing of the 16-Bit mode is identical to that of the UTOPIA mode, but the data width is expanded to a
word of 16 bits in and out. The translation RAM is not used in this case. The extra 8 inlet bits are connected to
the pins used for the data of the translation RAM, TRD (7-0), and the extra 8 outlet pins are the pins for the 8
LSB of the translation RAM address output, TRA (7-0).
TXC-05802B-MB
Ed. 3, February 2001
- 16 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Inlet
8 LSB
8 MSB
TRD(7-0)
CID(7-0)
CISOC
CUBIT-Pro
CellBus bus
CBD(31-0)
32
CBRC
8 LSB
8 MSB
CICLAV
CIENB
CICLK
CBWC
GFC3
GFC2
GFC1
GFC0
TRA(7-0)
COD(7-0)
COSOC
COCLAV
COENB
COCLK
CBACK
CBF
CBCONG
Outlet
Microprocessor
PHYEN
TRAN
LMODE2
LMODE1
LMODE0
Operating Mode: Inlet
Operating Mode: Outlet
High
X
Low
High
Low
16-Bit: 29 words, cell plus
one word of Tandem
Routing Header, plus one
word of CellBus Bus
Routing Header
16-Bit: 28 words, cell plus
one word of Tandem
Routing Header
High
X
Low
High
High
16-Bit: 29 words, cell plus
one word of Tandem
Routing Header, plus one
word of CellBus Bus
Routing Header
16-Bit: 27-word cell
High
X
High
X
X
16-Bit: 28 words, cell, plus
one word of CellBus Bus
Routing Header
16-Bit: 28 words, cell plus
one word of Tandem
Routing Header
High
X
Low
Low
High
16-Bit: 28 words, cell, plus
one word of CellBus Bus
Routing Header
16-Bit: 27-word cell
High
X
Low
Low
Low
Reserved
Reserved
Figure 10. ATM Layer Emulation 16-Bit Mode Signal Connections and Operating Mode Selection
- 17 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Figure 11. PHY Layer Emulation 16-Bit Mode Signal Connections and Operating Mode Selection
Inlet
8 LSB
8 MSB
TRD(7-0)
CID(7-0)
CISOC
CUBIT-Pro
CellBus bus
CBD(31-0)
32
CBRC
8 LSB
8 MSB
CICLAV
CIENB
CICLK
CBWC
GFC3
GFC2
GFC1
GFC0
TRA(7-0)
COD(7-0)
COSOC
COCLAV
COENB
COCLK
CBACK
CBF
CBCONG
Outlet
Microprocessor
PHYEN
TRAN
LMODE2
LMODE1
LMODE0
Operating Mode: Inlet
Operating Mode: Outlet
Low
X
Low
High
Low
16-Bit: 29 words, cell plus
one word of Tandem
Routing Header, plus one
word of CellBus Bus
Routing Header
16-Bit: 28 words, cell plus
one word of Tandem
Routing Header
Low
X
Low
High
High
16-Bit: 29 words, cell plus
one word of Tandem
Routing Header, plus one
word of CellBus Bus
Routing Header
16-Bit: 27-word cell
Low
X
High
X
X
16-Bit: 28 words, cell, plus
one word of CellBus Bus
Routing Header
16-Bit: 28 words, cell plus
one word of Tandem
Routing Header
Low
X
Low
Low
High
16-Bit: 28 words, cell, plus
one word of CellBus Bus
Routing Header
16-Bit: 27-word cell
Low
X
Low
Low
Low
Reserved
Reserved
TXC-05802B-MB
Ed. 3, February 2001
- 18 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Word Ordering for 16-Bit Cell Interface Mode
The word ordering for 16-Bit mode is shown in Figure 12.
29-Word Inlet
First Word
Transferred
TandemRH MSB
TandemRH LSB
CellBusBusRH MSB CellBusBusRH LSB
Last Word
Transferred
28-Word Outlet
28-Word Inlet
CellBusBusRH MSB CellBusBusRH LSB
27-Word Outlet
TandemRH MSB
TandemRH LSB
GFC, VPI
VPI, VCI
GFC, VPI
VPI, VCI
GFC, VPI
VPI, VCI
GFC, VPI
VPI, VCI
VCI
VCI, PT, CLP
VCI
VCI, PT, CLP
VCI
VCI, PT, CLP
VCI
VCI, PT, CLP
HEC
Undefined
HEC
Undefined
HEC
Undefined
HEC
Undefined
Byte 0
Byte 1
Byte 0
Byte 1
Byte 0
Byte 1
Byte 0
Byte 1
Byte 2
Byte 3
Byte 2
Byte 3
Byte 2
Byte 3
Byte 2
Byte 3
Byte 42
Byte 43
Byte 42
Byte 43
Byte 42
Byte 43
Byte 42
Byte 43
Byte 44
Byte 45
Byte 44
Byte 45
Byte 44
Byte 45
Byte 44
Byte 45
Byte 46
Byte 47
Byte 46
Byte 47
Byte 46
Byte 47
Byte 46
Byte 47
High Byte
Low Byte
High Byte
Low Byte
Low Byte
High Byte
High Byte
Low Byte
Figure 12. Word Ordering on Cell Inlet and Outlet in 16-Bit Mode
TRAFFIC MANAGEMENT FUNCTIONS
Dynamic Generic Flow Control (GFC) Field Insertion
The CUBIT-Pro can insert the value of the first nibble of the ATM cell header in real time. The value of the GFC
nibble is supplied to the CUBIT-Pro via the input pins GFC(3-0). The insertion of the GFC value is enabled via
the control bit GFCENA, as shown in Figure 13.
CUBIT-Pro Cell Outlet Port
GFC Value
Output
Cell Data
4
Cell from
Outlet Queue
8
HEC
Calculation
GFCENA Bit
Figure 13. GFC Insertion on the Outlet Queue (GFCENA = 1)
If control bit GFCENA (Control Register Address 0CH, Bit 1) is set to one, then the state of the four Generic
Flow Control input pins GFC(3-0) will be accepted during the leading rising edge of the clock for the first byte of
- 19 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
the ATM cell header and inserted as an outgoing GFC on the following cell (see timing diagram in Figure 44 for
details). Therefore the GFC value is inserted into the next outgoing cell.
Forward Explicit Congestion Notification (FECN)
The CUBIT-Pro can notify an impending congested state by setting to one the middle bit of the Payload Type
(PT) field in the ATM cell header. This Explicit Forward Congestion Indication bit (EFCI) will be asserted on a
cell if both of two conditions occur at the same time:
a) Bit 0 in register 0CH is set to one (IFECN = 1), and
b) QM (bit 2 in register 0CH) = 0 and VBR Limit reached, or QM=1 and VBR Limit or CBR Limit reached.
The activation of the EFCI bit in the single-queue (QM = 0) and split-queue (QM = 1) modes is illustrated in Figures 14 and 15, respectively.
VBRLIMIT = 2
Sync FIFO
Single Queue
Cell
#1
X0X
Cell
Outlet
Port
Cell
#2
X0X
Cell
#3
X0X
Cell
#4
X1X
Cell
#5
X1X
Cell
#6
X0X
Note: The IFECN control bit is set to 1. The EFCI congestion indication is the middle bit of the PT
sequence (X0X or X1X). Its value is determined when the cell leaves the queue.
Figure 14. Example of Congestion Indication in Single-Queue Mode (QM = 0)
Figure 14 shows a starting condition for the single-queue mode soon after the congestion conditions a) and b)
have both become present, with three cells in the queue when VBRLIMIT is set to 2. Cells #1, #2 and #3
reached the Sync FIFO before the congestion occurred, so they are not marked with a congestion indication
and have a PT value of X0X. The first cell in the queue (cell #4) is marked with a congestion indication (PT =
X1X) and it moves into the Sync FIFO when the outlet link is free and Cell #1 is sent to the cell outlet port. Cells
#5 and #6 then shift to the left, putting Cell #6 at the VBRLIMIT = 2 boundary, so congestion persists and Cell
# 5 is also marked with PT = X1X. When this cell moves into the Sync FIFO, Cell #6 shifts left and it is the only
cell left in the queue, assuming no more cells have joined the queue. Since the queue length of 1 is now less
than VBRLIMIT = 2, condition b) no longer exists and cell #6 carries no congestion marking (PT = X0X).
Figure 15 shows a starting condition for the split-queue mode some time after congestion conditions a) and b)
have both become present, with three cells in the CBR cell queue when CBRLIMIT = 3 and two cells in the
VBR cell queue when VBRLIMIT = 2 (i.e., both queues are at the congestion level).
TXC-05802B-MB
Ed. 3, February 2001
- 20 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Control Data Cell Queue (Priority 1)
CBRLIMIT = 3
CBR Cell Queue (Priority 2)
Cell
#4
CBR
X1X
Sync FIFO
Cell
Outlet
Port
Cell
#1
CBR
X0X
Cell
#2
VBR
X0X
Cell
#3
ABR
X0X
Cell
#5
CBR
X1X
Cell
#6
CBR
X1X
VBRLIMIT = 2
VBR Cell Queue (Priority 3)
Cell
#7
VBR
X1X
Cell
#8
VBR
X0X
ABR Cell Queue (Priority 4)
Note: The IFECN control bit is set to 1. The EFCI congestion indication is the middle bit of the PT
sequence (X0X or X1X). Its value is determined when the cell leaves the queue.
Figure 15. Example of Congestion Indication in Split-Queue Mode (QM=1)
As before, cells #1, #2 and #3 left the queues before the congestion occurred and are not marked for congestion indication (PT = X0X). When the outlet link becomes free and the cells in the Sync FIFO shift to the left,
cells flow in to the Sync FIFO from the four data cell queues in priority order. Since the VBR queue contains
two cells when VBRLIMIT = 2, congestion continues to exist while all cells in the CBR cell queue are moved
into the Sync FIFO, so cells #4, #5 and #6 are marked with congestion indications (PT = X1X). Now, assuming
no more cells are joining the queues, the CBR cell queue is empty but the VBR cell queue is still at the
VBRLIMIT value with two cells, so cell #7 is also marked with a congestion indication. But when it moves to the
Sync FIFO only one cell is left in the VBR cell queue, so conditions a) and b) no longer both exist, and this cell
#8 is not marked with a congestion indication (PT = X0X).
Paralleling Cell Inlet/Outlet Ports for Redundancy
If the control bit ONLINE (control register address 0CH, bit 7) is set to zero, then all of the CUBIT-Pro cell outlet
interface output pins will be taken to the high impedance (Hi-Z) state and the cell inlet data input pins will be
disabled. Thus two CUBIT-Pros may be paralleled for redundancy, each connected to a separate CellBus bus.
Cells will only be accepted from, or sent to, the line by the CUBIT-Pro in which ONLINE = 1.
- 21 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
INLET-SIDE TRANSLATION
Introduction
The translation function on the inlet side operates using information stored in an external static RAM, and can
provide the following functions:
Virtual Path Identifier (VPI) translation or
VPI/VCI translation (where VCI is Virtual Circuit Identifier), and
CellBus Bus Routing Header insertion, and
Tandem Routing Header insertion, and
F4 flow cell routing, and
F5 flow cell routing.
All translation operations start by performing a translation table lookup based on the VPI number of the incoming cell. Within the routing table record for that VPI is control information for that VPI, indicating whether cells
are to be routed based on VPI number alone or on VPI and VCI.
If VPI-only routing is selected, a translated VPI number, accompanied by CellBus Bus and Tandem Routing
Headers, is retrieved from the translation record for that VPI. In this case, the VCI number of the incoming cell
is not changed. If VPI translation is selected, separate routing for F4 OAM flow cells and RM-VPC cells on that
VPI can be programmed, allowing selective handling of these OAM-cells and RM-cells by a CellBus bus system.
If the VPI is instead programmed for VCI translation, then a two-step procedure is used to accomplish the
translation. The VPI record, accessed first, indicates the size and position in memory of the VCI translation
table. Using this information, and the VCI address of the cell, a VCI translation record is accessed. This translation record contains the VPI and VCI numbers to be assigned to the cell, along with the CellBus Bus and Tandem Routing Headers. When VPI/VCI translation is selected, separate routing for F5 OAM flow cells and
RM-VCC cells on that VCI can be programmed, allowing selective handling of these OAM-cells and RM-cells
in a manner similar to that of F4 OAM flow cells and RM-VPC cells.
In both cases, the cells with the translated headers and CellBus Bus and Tandem Routing Headers are forwarded to the bus in sequential order. Translation does not add delay to cells passing through the inlet side to
the CellBus bus.
TXC-05802B-MB
Ed. 3, February 2001
- 22 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Translation RAM Connections
The CUBIT-Pro can address up to 256k bytes of translation SRAM (TRAM). The connections to the TRAM are
shown in Figure 16. The TRAM access time requirement is dependent upon the cell inlet clock speed (i.e., in
ATM Layer mode: CellBus bus clock, or PCLK, or LCLOCK; in PHY Layer mode: CICLK), see Figures 32 and
33. An access time of 35 nanoseconds or less will support the maximum CellBus bus speed.
Translation SRAM
CS
ADDR DATA WE
18
TRA
OE
Chip Select
Generation
Logic
8
TRD TRWE TROE
CUBIT-Pro
Figure 16. Translation RAM Connections
The chip select should be implemented according to the number of SRAM devices used in the design. If a single 256k x 8 SRAM is used, the memory can be permanently selected, or if a low-power application is required
then the memory can be selected only when the CUBIT-Pro needs to access the SRAM (use TROE and
TRWE, as shown in Figure 16).
Translation RAM Control
When the CUBIT-Pro device is configured to perform translation (input pin TRAN low), it replaces received values of VPI or VPI and VCI numbers with new values, and adds Routing Headers to the cells forwarded to the
CellBus bus. The VPI/VCI number and Routing Header information that is inserted comes from translation
record entries in the TRAM. The TRAM is organized into a block of VPI records and a block of VCI records, the
contents of which are established by system control.
Translation RAM Organization
The translation RAM partitioning is shown in Figure 17. The lower portion of the TRAM contains the translation
records for VPIs. When the UNI mode is enabled (control bit UNI=1), the number of VPI entries is 256. When
NNI mode is enabled (UNI=0), 4096 VPI entries are present.
Depending on whether the Tandem Routing Header is enabled the VP Record has: four bytes if the Tandem
Routing Header (TRH) is not used (control bit TRHENA=0), and six bytes if the TRH is used (TRHENA=1). The
size of the VPI memory space in this mode ranges from 1024 bytes (UNI mode, no TRH, 4 x 256) to 24576
bytes (NNI and TRH, 6 x 4096).
The memory space above the VPI section is the VCI translation record storage space, divided into a number of
VCI pages. Each VCI page contains the translation records for 128, 256, 512, or 1024 VCIs.
Depending on whether Tandem Routing Header is enabled the VC Record has: six bytes if the Tandem Routing Header (TRH) is not used (control bit TRHENA=0), and eight bytes if the TRH is used (TRHENA=1).
- 23 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
The number of VCI records per page (VRP) depends on the settings of the VRPS[1,0] control bits in register
0EH as follows:
VRPS[1,0]=0,0: VRP is 256
VRPS[1,0]=0,1: VRP is 512
VRPS[1,0]=1,0: VRP is 1024
VRPS[1,0]=1,1: VRP is 128
The total size of the TRAM which the CUBIT-Pro can support is up to 262,144 bytes (256k). Hence, the number of VCI translation table pages which can be supported is a function of memory size, and the states of control bits UNI and TRHENA. For example, the maximum number (M) of VCI memory pages, for maximum
memory size, is as follows:
VRPS[1,0]=0,0: VRP is 256
if UNI=1, TRHENA = 1; M = (262144-(256*6))/(256*8) = 127 VCI Pages,
if UNI=1, TRHENA = 0; M = (262144-(256*4))/(256*6) = 170 VCI Pages.
VRPS[1,0]=0,1: VRP is 512
if UNI=1, TRHENA = 1; M = (262144-(256*6))/(512*8) = 63 VCI Pages,
if UNI=1, TRHENA = 0; M = (262144-(256*4))/(512*6) = 85 VCI Pages.
VRPS[1,0]=1,0: VRP is 1024
if UNI=1, TRHENA = 1; M = (262144-(256*6))/(1024*8) = 31 VCI Pages,
if UNI=1, TRHENA = 0; M = (262144-(256*4))/(1024*6) = 42 VCI Pages.
VRPS[1,0]=1,1: VRP is 128
if UNI=1, TRHENA = 1; M = (262144-(256*6))/(128*8) = 254 VCI Pages,
if UNI=1, TRHENA = 0; M = Min[(262144-(256*4))/(128*6), 256] = Min [340,256] = 256 VCI Pages.
if VRPS[1,0]=1,1, VRP is 128. The maximum number of addressable pages is 256, even though, theoretically, 340 pages could fit in a SRAM of 256k bytes.
VRPS[1,0] = 1,0
6143
or 8191 VCI 1023 Record
VCI 511 Record
VRPS[1,0] = 0,0
***
***
0
VCI 1 Record
VCI 0 Record
VCI Page M-1
VRPS[1,0] = 0,1
3071
or 4095
0
VCI 1 Record
VCI 0 Record
1535
or 2047
VCI 255 Record
0
***
VCI 1 Record
VCI 0 Record
***
767
or 1023
0
VRPS[1,0] = 1,1
VCI 127 Record
VCI Page 3
***
VCI 0 Record
VCI Page 2
VCI
Translation
Table
VCI Page 1
VRPS[1,0] = 0,0 or 0,1 or 1,0 or 1,1
1023,
1535,
16383
or 24575
0
VPI N-1 Record
***
VPI 3 Record
VPI 2 Record
VPI 1 Record
VPI 0 Record
Figure 17. Translation RAM Organization
TXC-05802B-MB
Ed. 3, February 2001
- 24 of 90 -
VCI Page 0
VPI
Translation
Table
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
VCI Page 0 Organization
This page may optionally be used for OAM-cells routing, RM-cells routing, or data cells routing. For OAM/RM
and reserved VCs, bit OAMRMEN (bit 1 in register 0EH) must be set to 1. If OAM/RM routing is enabled
(OAMRMEN=1) then the organization of VCI Page 0 is as shown in Figure 18.
Last VC Record (127, 255, 511, or 1023)
VCI Page 0
Record 37
Record 36
Record 35
Record 34
Record 33
Record 32
Record 31
Record 6
Record 5
Record 4
Record 3
Record 2
Record 1
Record 0
Reserved VCs
& Special Cells
OAM-F5 Cells (PT= 111) Record
RM-VCC Cells (PT= 110) Record
OAM-F5 Cells (PT= 101) Record
OAM-F5 Cells (PT= 100) Record
RM-VPC Cells Record
OAM-F4 Cells Records
Figure 18. VCI Page 0 Organization (Bit OAMRMEN=1)
If the device is required to operate in CUBIT TXC-05801 applications, then bit OAMRMEN must be set to 0,
which is the power-up/reset default.
Translation Procedure
Translation is performed in a two-step procedure, starting with examining the incoming VPI number. A full 8-bit
(UNI=1) or 12-bit (UNI=0) VPI number may be used. The incoming VPI number is used to address a VPI translation record. If the translation is to be done on VPI only, leaving the VCI number intact, then the VPI number
and routing header are contained in the VPI translation record. If VPI and VCI translation is to be done, then
the VPI record contains a pointer to the location of one or more "pages" of VCI translation records. Each
"page" is a set of translation records for either 128, 256, 512, or 1024 consecutive VCI numbers (depending on
the settings of bits VRPS[1,0] in register 0EH). Up to sixteen such VCI pages may be assigned to any VPI. The
only restriction is that the VCI pages for each VPI must be assigned in consecutive VCI address space from
zero upwards. Within this assigned space, the VCI number of the incoming cell is used to address a particular
VCI translation record containing the new VPI and VCI numbers and the routing header.
OAM/RM cells are routed either from the VP record or VC record that is marked for this special cells routing, as
detailed in the section below entitled “OAM-Cells and RM-Cells Record Format”.
For the translation operation the CUBIT-Pro uses several data structures. These data structures can be of
three different types:
VP Record
VC Record
OAM/RM Record
Each of these records contains one or more control bits in the first byte of the record (byte 0), which determines whether the routing is per VP, per VC, or per OAM/RM cell. The control bits are described next.
- 25 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Translation Records Control Bits
Four control bits, labelled as A, P, E and I, are used in byte 0 of translation records, as described below:
Active (A) Bit:
If the A bit is set to one in a translation record, then that VPI or VCI is active. Cells received with this VPI or
VCI will be translated and forwarded to the bus, unless bit I is set to one. If A=0, then cells received on this
VPI or VCI will be considered misrouted, unless I=1.
VPI Translation Enable Bit (P):
If this bit is one in a VPI translation record, then a VPI-only translation is made. If it is set to zero, a combined VPI and VCI translation is made.
OAM/RM Cell Routing Enable Bit (E):
If bit E is set to one in a VPI record, then VCIs numbered 0 through 31 of that VPI will be routed according
to OAM/RM records contained in record numbers 0 through 31 of VCI page zero. Additionally, if bit E is set
to one in a VPI record, then cells of that VPI with VCI =6 and having the PT = 110 will be routed according
to the OAM translation record contained in record number 32 of VCI page zero. Regular data cells (not
conforming to the above rules) are routed according to the VP and/or VC record. If bit E is set to one in a
VCI record, then cells of that VPI having the PT = 100, 101, 110, and 111(Payload Type Indicator, in ATM
cell header) will be routed according to the OAM translation record contained in record numbers 33, 34,
35, and 36 of VCI page zero, respectively.
Ignore Bit (I):
If the ignore bit is one (I=1) in an active VP or VC (i.e., A=1 in the translation record) then incoming cells
bearing this VP or VC number are discarded, but not counted as misrouted cells. If control bit NOTIGN (bit
5 in register 0EH) is set to 1, then connections with I=1 will be treated as if I=0.
OAM/RM Routing Mode Bits (C1, C0):
These bits are used to determine on which VPI/VCI OAM/RM cells are routed. They are placed in the locations of the P and E bits. The possible combinations are:
C1,C0 = 0,0: the cell header is translated according to the values in the OAM/RM record (this value
and OAMRMEN=0 should be selected for applications supporting CUBIT TXC-05801
functionality)
C1,C0 = 0,1: for F4 flow this virtual path connection (VPC) OAM cells/RM-VPC cells are not routed
according to the OAM/RM record. Instead, these cells are routed according to the VP
record corresponding to the incoming VP.
For F5 flow this virtual circuit connection (VCC) OAM cells/RM-VCC cells are not routed
according to the OAM/RM record. Instead, these cells are routed according to the VC
record corresponding to the incoming VP/VC combination.
C1,C0 = 1,0: attach CellBus Bus Routing Header (CBRH) and Tandem Routing Header (TRH) only,
and preserve the incoming VP/VC combination
C1,C0 = 1,1: reserved
Note: In order to use Tandem Routing Header, TRHENA =1 must be selected regardless of the table values.
CellBus Bus Routing Header
The CellBus Bus Routing Header is a 16-bit structure, which is formatted as described earlier in the CellBus Bus
Cell Routing subsection. Additional detail is provided in Appendix A of "CellBus Bus Technical Manual and
CUBIT-Pro Applications", TranSwitch document number TXC-05802-TM1.
Tandem Routing Header
If the Tandem Routing Header is to be used as a CellBus Bus Routing Header, as when passed through a
CUBIT-Pro in back-to-back mode, it must follow the same construction rules as a CellBus Bus Routing Header.
TXC-05802B-MB
Ed. 3, February 2001
- 26 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
CUBIT-Pro
TXC-05802B
If the Tandem Routing Header is used for some proprietary purposes, its format will follow a different specification.
Translation Record Formats
VPI Translation Record Formats
VPI translation records are four bytes long if TRHENA=0, or six bytes long if TRHENA=1, as shown in
Figure 19. Each VPI may be either idle or busy. If it is busy, then each VPI may be set for VPI-only translation,
or for combined VPI/VCI translation. The control bits (A, P, E and I) and Routing Headers are described in the
preceding sections.
Idle VPI, TRHENA=1
If the VPI is unused, then the MSB (Active
bit, A) of relative address zero is set to
zero, indicating idle. If a cell arrives with
this VPI number, it is discarded and is
counted as a misrouted cell.
5
4
Idle VPI, TRHENA=0
3
3
2
2
1
1
0
0
0
X
X 1/0
A
P
E
0
X
X 1/0
A
P
E
I
I
VPI Translation, TRHENA=1
VPI Translation, TRHENA=0
5
Tandem Routing Header LSB
4
Tandem Routing Header MSB
3
CellBus Bus Routing Header LSB
3
CellBus Bus Routing Header LSB
2
CellBus Bus Routing Header MSB
2
CellBus Bus Routing Header MSB
1
1
VPI, 8 LSB
0
0
1
1
E 1/0
A
P
E
VPI, 4 MSB
VPI, 8 LSB
1
1
E 1/0
A
P
E
VPI, 4 MSB
I
I
VPI and VCI Translation,
TRHENA=1
5
VPI and VCI Translation,
TRHENA=0
3
0
4
3
2
2
1
1
If the VPI is busy and is to have VPI number translation only, then the A bit is set=1,
and the P bit is set=1. In this case, the VPI
to be inserted on the cell is contained in
the 4 LSB of relative address zero (4 MSB
of new VPI), and in relative address one (8
LSB of new VPI). CellBus Bus and Tandem Routing Headers are also contained
in the next two or four bytes.
VCI Page Offset
1
0
E 1/0 VCI Page Size
A
P
E
0
VCI Page Offset
1
0
E 1/0 VCI Page Size
A
P
E
I
I
If the VPI is busy and is set for combined
VPI/VCI number translation, a reference is
generated to a VCI translation record. The
VPI is set active (A=1), and is set for VCI
translation (P=0). The 4 LSB of relative
address zero contain the VCI Page Size,
which is the number of assigned VCI
pages, each of 128, 256, 512, or 1024 VCI
records, allocated to this VPI (range from
1 to 16, where 0H=16). Relative address
one contains the VCI Page Offset, which
indicates where among the VCI pages the
first utilized page starts.
Figure 19. VPI Translation Record Formats
The calculation of the start address for the VP record when there is no Tandem Routing Header (control bit
TRHENA=0) is performed as follows:
VP_Start_Addr = VP# x 4
If TRHENA=1 then:
VP_Start_Addr = VP# x 6
- 27 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
VCI Translation Record Formats
VCI translation records are six bytes long if TRHENA=0, and eight bytes long if TRHENA=1, as shown in
Figure 20. Each VCI may be either idle or busy.
IDLE VCI, TRHENA=1
If the VCI is inactive (A=0) and not
Ignore (I=0), then cells arriving bearing that VCI number are discarded
and counted as misrouted. If I=1,
they are discarded and not counted
as misrouted.
7
IDLE VCI, TRHENA=0
6
5
5
4
4
3
3
2
2
1
0
1
0
-
A
0
E 1/0
E
I
0
-
A
E 1/0
E
I
VPI and VCI Translation,
TRHENA=1
VPI and VCI Translation,
TRHENA=0
7
Tandem Routing Header LSB
6
Tandem Routing Header MSB
5
CellBus Bus Routing Header LSB
5
CellBus Bus Routing Header LSB
4
CellBus Bus Routing Header MSB
4
CellBus Bus Routing Header MSB
3
VCI, 8 LSB
3
VCI, 8 LSB
2
VCI, 8 MSB
2
VCI, 8 MSB
1
VPI, 8 LSB
1
0
1
A
-
E 1/0
E
0
VPI, 4 MSB
I
VPI, 8 LSB
1
A
-
E 1/0
E
VPI, 4 MSB
I
If the VCI is active (A=1), then the VPI
and VCI numbers to be inserted in the
cell, and the CellBus Bus Routing
Header to be used, are read from the
VCI translation record at the positions
indicated.
Figure 20. VCI Translation Record Formats
The calculation of the start address for the VC record uses information from the VP table addressed by the VP
of the incoming cell, as well as information of the VCI of the incoming cell. The information required from the
VP record is the VCI Page Offset (VPO). In the case with no Tandem Header Translation (control bit
TRHENA=0 in register 0AH) and in UNI mode (control bit UNI=1 in register 0AH) the start address of the VC
record corresponding to an incoming VP/VC, assuming a given number of VCI records per page (VRP, determined by the control bits VRPS1 and VRPS0 in register 0EH) is calculated (in decimal format) as follows:
VC_Start_Address = 1024 + VPO x VRP x 6 + VCI x 6
or with TRHENA=1 and UNI=1:
VC_Start_Address = 1536 + VPO x VRP x 8 + VCI x 8
or with TRHENA=0 and UNI=0:
VC_Start_Address =16384 + VPO x VRP x 6 + VCI x 6
or with TRHENA=1 and UNI=0:
VC_Start_Address = 24576 + VPO x VRP x 8 + VCI x 8.
TXC-05802B-MB
Ed. 3, February 2001
- 28 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
OAM-Cells and RM-Cells Record Format
OAM/RM and reserved VC cells routing can be performed on any VP/VC combination with the appropriate programming of the E-bit in the VP or VC translation record, and setting OAMRMEN bit (bit 1 in register 0EH) to 1.
For compatibility with CUBIT TXC-05801 applications, the bit OAMRMEN should be set to 0 (default).
Both F4 and F5 flows are supported in the CUBIT-Pro. Depending on which flow is routed, two algorithms are
used by the CUBIT-Pro (assuming OAMRMEN=1). The algorithm for F5-flow is depicted in Figure 21. The PT
field of the ATM cell header coming in a VP/VC that is set for VP/VC translation (with E-bit set to 1 in the VC
translation record) will be checked for all possible values and routed to VCI Page 0 according to the flow
shown in Figure 21.
For F4 flow a cell coming in any VP will be sent to VCI Page 0 if the VCI is within numbers 0-31 (OAMRMEN=1) according to the algorithm shown in Figure 22.
Incoming Cell
VPI/VCI
Translation?
No
Route According
to VP Translation
No
Route According
to VC # Record
Yes
Yes
ATM Cell Header:
PT = 100?
Yes
Route According
to VC =33
in VC Page 0
VCI Record:
E-Bit = 1?
ATM Cell Header:
PT = 101?
Yes
Route According
to VC =34
in VC Page 0
ATM Cell Header:
PT = 110?
Yes
Route According
to VC =35
in VC Page 0
ATM Cell Header:
PT = 111?
Yes
Route According
to VC =36
in VC Page 0
ATM Cell Header:
PT = 0xx?
Yes
Route According
to VC # Record
Figure 21. OAM F5 and RM-VCC Cell Routing (Bit OAMRMEN=1)
- 29 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Incoming Cell
No
VPI Translation?
Route According
to VP/VC Translation
Yes
No
E-Bit = 1?
Route According
to VP # Record
No
VCI = 0..31?
Yes
VCI = 0..5 or
7..31?
VCI = 6 &
PT = 110?
Yes
No
Yes
Route According
to VC = 0..5 or
7..31
in VC Page 0
Route According
to VC = 32
in VC Page 0
VCI = 6?
Yes
Route According
to VC = 6
in VC Page 0
Figure 22. OAM F4 and RM-VPC Cell Routing (Bit OAMRMEN=1)
The corresponding formats for OAM translation records are shown in Figure 23.
IDLE VCI, TRHENA=1
If the VCI is inactive (A=0) and not
Ignore (I=0), then OAM cells arriving
bearing that VCI number are discarded and counted as misrouted. If
I=1, they are discarded and not
counted as misrouted.
7
IDLE VCI, TRHENA=0
6
5
5
4
4
3
3
2
2
1
1
0
0
0
0
0 1/0
A C1 C0
I
0
0
0 1/0
A C1 C0
I
VPI and VCI Translation
for OAM cells, TRHENA=1
VPI and VCI Translation
for OAM cells, TRHENA=0
7
Tandem Routing Header LSB
6
Tandem Routing Header MSB
5
CellBus Bus Routing Header LSB
5
CellBus Bus Routing Header LSB
4
CellBus Bus Routing Header MSB
4
CellBus Bus Routing Header MSB
3
VCI, 8 LSB
3
VCI, 8 LSB
2
VCI, 8 MSB
2
VCI, 8 MSB
VPI, 8 LSB
1
1
0
1
0
0 1/0
A C1 C0
VPI, 4 MSB
0
VPI, 8 LSB
1
0
0 1/0
A C1 C0
I
VPI, 4 MSB
The C1 and C0 bits determine the
type of translation for OAM/RM cells
received. The coding is explained in
the “Translation Records Control Bits”
section.
If the VCI is active (A=1), then the VPI
and VCI numbers to be inserted in the
cell, and the CellBus Bus Routing
Header to be used, are read from the
OAM translation record at the positions
indicated.
I
Note: OAM/RM Translation Records are optional. They are located in VCI page zero.
Figure 23. OAM/RM-Cells Translation Record Formats
TXC-05802B-MB
Ed. 3, February 2001
- 30 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
MULTICAST NUMBER MEMORY
A multicast address control cell or multicast address data cell can be sent to a number of CUBIT-Pros, and a
single CUBIT-Pro can receive cells with a number of different addresses. This is controlled by the setup of the
Multicast Number Memory (addresses E0H-FFH in the CUBIT-Pro memory map), which is a block of 32 bytes.
Each of the 256 bits in the block maps to one multicast address, as shown in Figure 24. When a bit is set to 1,
the CUBIT-Pro is enabled to receive the corresponding multicast address cell. Each CUBIT-Pro can be set to
receive any or all of the 256 possible multicast addresses.
1 in this bit location enables multicast address 255 (M Field = FFH)
Addresses (32)
FF
FE
FD
1 in this bit location enables multicast address 248 (M Field = F8H)
E2
E1
E0
1 in this bit location enables multicast address 0 (M Field = 00H)
Bit of Byte
MSB
LSB
1 in this bit location enables multicast address 7 (M Field = 07H)
Note: The M Field refers to the CellBus Bus Routing Header for Multicast Address cells (see Figure 5).
Figure 24. Multicast Number Memory
THE CellBus BUS INTERFACE
Thirty-seven lines comprise the CellBus bus interface, as shown in Figure 2. There are thirty-two Data lines,
with Frame, Acknowledge, and Congestion Indicator lines, all sourced by a CUBIT-Pro device, and two Clock
lines sourced by external drivers.
Operation with Internal GTL+ Transceivers
Gunning Transceiver Logic (GTL+) transceivers for CellBus bus Data, Frame, Acknowledge, and Congestion
Indicator lines are contained internally in the CUBIT-Pro, along with two clock line GTL+ receivers. Each of the
drivers has a typical current sink capability of 45 mA and is capable of driving a bus on a card or on a backplane directly. Each of the GTL+ lines is to be pulled-up at each of its ends by a 50 ohm (+/- 5%) resistor (metal
film or carbon composition) to a +1.5 V low-impedance supply. Each end of each line should have a filtering
capacitor connected from the +1.5 V supply to ground, as shown in Figure 25.
0.01µF
+1.5V
+1.5V
50Ω
50Ω
CUBIT-Pro
CUBIT-Pro
0.01µF
CUBIT-Pro
Figure 25. External Circuit Requirements for GTL+ Transceivers
- 31 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
In the CUBIT-Pro pinout, all of the pins involved with the bus interface are aligned along one side of the package between pins 50 and 112. This side of the package must be aligned toward the board connector, or toward
the bus, with as little board trace length as possible between the pins and the connector or bus, to maximize
operating speed.
Clock Source
Two GTL+-level clock signals must be driven to the CellBus bus from an external source. These are the write
clock, CBWC, and the read clock, CBRC. A phase relationship keeping the write clock between 0.5 and 4
nanoseconds behind the read clock is needed to ensure proper synchronous bus operation. When the clock
driver is driven from the center of the backplane (i.e., no greater than half a backplane length from any card) a
minimum phase distance of 1.0 ns or more must be maintained. When the driver is at one of the ends, a more
conservative 2-4 ns minimum is required. In any CellBus bus implementation, on the backplane and on each
card, care must be taken to ensure that these two lines are routed together. The capacitive and inductive loadings of the two lines should be as nearly equal as possible, to maintain performance. At the drive point, a delay
line should be used to maintain a stable delay, and the read and write clock drivers must be units of the same
integrated circuit package. All of these precautions will ensure the most stable clocks and permit the highest
possible operating speed.
Bus Arbiter Selection
One copy of the CellBus Bus Arbiter circuitry is included inside each CUBIT-Pro device. Enabling of the arbiter
on a particular CUBIT-Pro is done by connecting the ENARB pin of that device to ground (VSS). Normally, one
arbiter is turned on and the remaining arbiters on that bus are turned off. It is the responsibility of the overall
system control to decide which CUBIT-Pro will have its arbiter enabled, and to enable it. Failure of an arbiter
can be detected by using the NOGRT indications. If multiple CUBIT-Pros are indicating NOGRT failures, an
arbiter failure is indicated. It is again the responsibility of system control to enable another arbiter.
Upon switching from one arbiter to another, the receiving devices on the bus will automatically re-align to the
new frame position within one CellBus bus frame.
OUTLET-SIDE QUEUE MANAGEMENT
The CUBIT-Pro contains a 123-cell queuing FIFO for data on its outlet side. This FIFO may be operated as a
single 123-cell FIFO, or it may be split into four independent FIFOs.
Single Queue Operation
If control bit QM at Address 0CH, Bit 2 is zero, then the outlet has a single 123-cell FIFO. This mode is appropriate when a single type of traffic is to be switched by the system. In this case cell congestion, for purposes of
causing a FECN (if enabled by control bit IFECN at Address 0CH, Bit 0), is established by the register
VBRLIMIT at Address 12H.
Split-Queue Operation
If QM = 1, the outlet FIFO is split into 4 separate queues. These are, in order of service priority, Control Data
(highest priority), CBR, VBR, and ABR. The Control Data cell queue is fixed in length at 2 cells, and the ABR
queue at 32 cells. The congestion threshold on the ABR queue is set at 28. The size of the CBR queue is set
by the contents of register CBRLEN at Address 10H, and its congestion point by CBRLIMIT at Address 11H.
The remaining FIFO cells are assigned to the VBR queue. The length of the VBR queue is (123-2-32-CBRLEN
= 89-CBRLEN), and its congestion limit is set by VBRLIMIT at Address 12H.
Note the differences between the control data queue section of the split outlet queue, the control cell receive
buffer and the control cell transmit buffer (all referred to as control queue):
TXC-05802B-MB
Ed. 3, February 2001
- 32 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
1. The control data queue section of the split outlet queue accepts cells from the CellBus bus that have a single address data routing header with the Q field set to 00 (see Figure 5).
2. The control cell receive buffer (address 60H-93H) accepts cells from the CellBus bus that have a single
address control routing header (see Figure 5).
3. The control cell transmit buffer is loaded by the microprocessor with a cell to be sent to the CellBus bus. It
can have any of the CellBus Bus Routing Header formats shown in Figure 5.
Multicast and Broadcast cells in split-queue mode are sent to the VBR and CBR queues, respectively.
MICROPROCESSOR INTERFACE
General Description
The CUBIT-Pro Microprocessor Port will support an I/O interface characteristic of either Intel or Motorola
microprocessors, as shown in Figure 26.
CUBIT-Pro
CUBIT-Pro
Intel
Interface
GND
A7
A6
A5
A4
A3
A2
A1
A0
Motorola
Interface
D7
D6
D5
D4
D3
D2
D1
D0
PCLK
SEL
WR
RD
INT
RDY
MOTO
+5V
+5V
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
PCLK
SEL
WR
RD/WR
IRQ
DTACK
MOTO
Figure 26. Microprocessor Port Interface Connections
The connections for address A(7-0), data D(7-0), select (SEL) and processor clock (PCLK) are the same for
both cases. Differences are listed below.
Intel Mode
Enabled when device strap MOTO is connected to VSS (ground). Connections are as shown in Figure 26. The
differences to support Intel mode are:
WR pin is low to execute a write command,
RD pin is low to execute a read command,
Interrupt INT is active high,
Ready RDY is active high. When set low, it requests microprocessor wait time.
- 33 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Motorola Mode
Enabled when device strap MOTO is connected to VDDIO (+5V). Connections are as shown in Figure 26. The
differences to support Motorola mode are:
WR pin is not used and must be pulled up to +5 volts,
RD/WR pin is high to execute a read command or low to execute a write command,
Interrupt IRQ is active low,
Data Transfer Acknowledge DTACK is active low. When inactive, and pulled high by an external
pull-up resistor, it requests microprocessor wait time.
Interrupts
The CUBIT-Pro allows the generation of interrupts based on eleven different events. The events are latched in
two status registers located at addresses 05H and 08H, as shown in Figures 27 and 28. Any of the events will
generate an interrupt provided the corresponding interrupt enable bit, located in registers at addresses 06H
and 09H, is set to one.
If any of the events occurs, the corresponding status bit will be set to one. All the status bits in a register are
cleared when it is read, except for any bits for which the events still persist. Some enabled interrupts may not
be cleared in the absence of the CellBus bus clocks. Such interrupts will persist until the clocks are re-applied.
It is possible, however, to mask any interrupt regardless of the absence or presence of the CellBus bus clocks.
The events reported are explained below:
1. Status register at address 05H:
Bit 0 (LSB)
Bit 7 (MSB)
BIP-8
RESERVED
CBLOF
CBLORC CBLOWC
Figure 27. CUBIT-Pro Status Register at Address 05H
BIP-8 Error:
If the BIP-8 field (Grant cycle) of the CellBus bus cell body in a cell received from the CellBus
bus does not match the calculated BIP-8, this bit is set to 1 (see Figure 3).
CBLOF CellBus Bus Loss of Frame Pulse Error:
In the event that the CellBus bus frame pulse is not present for more than 4 consecutive
16-cycle frames, or if the CellBus Bus Write Clock is not present, this bit is set to 1.
CBLORC CellBus Bus Loss of Read Clock Error:
If the CellBus Bus Read Clock is not present, this bit will be set to 1.
CBLOWC CellBus Bus Loss of Write Clock Error:
If the CellBus Bus Write Clock is not present, this bit will be set to 1.
Note: Please see Note 5 in the Memory Map Reset States section (below) for information related to recovery from loss of
CellBus clocks by use of the hardware reset pin.
TXC-05802B-MB
Ed. 3, February 2001
- 34 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
2. Status register at address 08H:
Bit 0 (LSB)
Bit 7 (MSB)
CRCF
CRQOVF
CRQCAV
INSOC
CTSENT
NOGRT
RESERVED
OCOVF
Figure 28. CUBIT-Pro Status Register at Address 08H
CRCF CRC-4 Error:
If the CRC-4 field H(3-0) of the CellBus Bus Routing Header in a cell received from the CellBus
bus does not match the calculated CRC-4, this bit is set to 1 (see Figure 5).
CRQOVF Control Receive Queue Overflow:
An overflow will occur, and this bit will be set to 1, when more than four cells try to accumulate
in the control receive queue.
CRQCAV Control Receive Queue Cell Available:
When a control cell has been received from the CellBus bus and placed in the receive buffer
(addresses 60H-93H) this bit will be set to 1. This bit is cleared to 0 after the microprocessor
writes a 1 to CRQSENT.
INSOC Inlet Start of Cell:
In the ATM Layer Emulation UTOPIA 8-bit (PHYEN = High) and ATM Layer Emulation 16-Bit
(PHYEN = High) modes and the Back-to-Back mode, if CISOC is not present in the same
clock cycle that CICLAV is asserted, or if CISOC is asserted before the end of the current cell,
the INSOC bit is set to 1.
In the PHY Layer Emulation UTOPIA 8-bit (PHYEN = Low) and PHY Layer Emulation 16-Bit
(PHYEN = Low) modes, if CISOC is not present in the same clock cycle that CIENB is
asserted (after CICLAV has been asserted signaling the transfer of the first byte of the cell), or
if CISOC is asserted before the end of the current cell, the INSOC bit is set to 1. If the ONLINE
bit is set to 0 to disable cell acceptance at the cell inlet, arrival of a cell will cause INSOC to be
set to 1. In order to prevent generation of false interrupts, the interrupt-enable bit for INSOC
(INTEN4) should also be set to 0 when ONLINE is set to 0 in PHY layer emulation mode.
CTSENT Control Cell Sent:
When the microprocessor requests that a control cell be sent to the CellBus bus, this bit will be
set to 1 after the cell has been sent.
NOGRT No Grant:
If the CUBIT-Pro device has requested a CellBus bus grant and has not received it after the
number of frames indicated by the TIME register (address 0FH), this bit will be set to 1.
OCOVF Outlet Cell Overflow:
In the single-queue mode an overflow will occur, and this bit will be set to 1, when more than
123 cells try to accumulate in the outlet queue.
- 35 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
In the split-queue mode this overflow will occur if any of the following events occurs:
a. More than 32 cells try to accumulate in the ABR queue
b. More than CBRLEN (address 10H) cells try to accumulate in the CBR queue
c.
More than (89 minus CBRLEN) cells try to accumulate in the VBR queue
d. More than 2 cells try to accumulate in the control queue.
Control Queue Send and Receive
The formats of send (transmit) and receive control cells are shown in Figure 29. Reference to Figure 1 will be
helpful for understanding how cells are handled by the inlet and outlet control queues.
A cell can be sent from the microprocessor to the CellBus bus by using the control cell transmit buffer (Inlet
Control Queue in Figure 1). This ability allows the microprocessor to send any type of data, control or loopback
cell to any CUBIT-Pro on the CellBus bus. The microprocessor first writes a 56-byte transmit cell with the format shown in Figure 29 to the control cell transmit buffer (Addresses A0H-D7H in the CUBIT-Pro memory
map). Then a 1 is written to control bit CTRDY (Address 0AH, Bit 1). The cell will be sent to the CellBus bus
after any pending data cells, and the CTSENT bit (Address 08H, Bit 3) will then be set to 1 and the CTRDY bit
will be reset to 0. Another such cell send sequence may be started after CTSENT has been received.
A four-cell FIFO buffer (Outlet Control Queue in Figure 1) is provided for reception of control cells from the CellBus bus, since control cells can arrive from several sources and may have to wait for the microprocessor to
accept them from the CUBIT-Pro. The FIFO output is the 52-byte memory segment CRQ(51-0) at Addresses
93H-60H. When this segment acquires a received control cell the CUBIT-Pro sets its interrupt bit CRQCAV to
1 (Address 08H, Bit 5). This bit may be enabled to cause an interrupt to the microprocessor (by setting interrupt enable bit INTEN5 to 1 in Address 09H, Bit 5). When an interrupt or polling process causes the microprocessor to read the interrupt event status register at Address 08H it will detect the CRQCAV indication that a
control cell is available for reading. It must then read CRQ(51-0) and set control bit CRQSENT to 1 upon completion (Address 0AH, Bit 0). This notifies the CUBIT-Pro to reset CRQCAV to 0 and place the next control cell
in CRQ(51-0), either immediately from the adjacent FIFO cell, if occupied, or whenever the next cell arrives in
the FIFO from the CellBus bus. The CUBIT-Pro resets CRQSENT to 0.
Control cell transmission and reception may still be performed regardless of the state of control bit ONLINE
(Address 0CH, Bit 7).
TXC-05802B-MB
Ed. 3, February 2001
- 36 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Byte #
0
CellBusBusRH MSB
1
CellBusBusRH LSB
2
TandemRH MSB
3
TandemRH LSB
4
GFC, VPI
GFC=0, VPI
0
5
VPI, VCI
VPI, VCI
1
6
VCI
VCI
2
7
VCI, PT, CLP
VCI, PT, CLP
3
8
Byte 0
Byte 0
4
9
Byte 1
Byte 1
5
10
Byte 2
Byte 2
6
53
Byte 45
Byte 45
49
54
Byte 46
Byte 46
50
55
Byte 47
Byte 47
51
Transmit
Control Cell
Receive
Control Cell
Figure 29. Transmit and Receive Control Cell Formats
- 37 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
LOOPBACK CELL SEND, RECEIVE AND RELAY
The loopback function is provided for diagnostic purposes. It may be used on-line (ONLINE = 1), or off-line
(ONLINE = 0). A loopback path for a cell from CUBIT-Pro X to CUBIT-Pro Y and back to CUBIT-Pro X can be
set up by loading the LBADDR registers in Addresses 13H and 14H of CUBIT-Pro Y with the single address
control CellBus Bus Routing Header of CUBIT-Pro X, as shown in Figure 30. The microprocessor then writes a
cell with a single address loopback Routing Header for CUBIT-Pro Y into the control transmit buffer
(Addresses A0H-D7H) of CUBIT-Pro X and causes the cell to be sent. When CUBIT-Pro Y receives the cell it
will use the contents of LBADDR to form a new Routing Header for the cell and send it back to CUBIT-Pro X.
CUBIT-Pro X will receive the cell and place it in the control receive buffer where it can be examined by the
microprocessor.
The above description assumes that the loopback cell originates in the control transmit buffer of CUBIT-Pro X,
but it could also be received from the inlet port. Any of the seven Routing Header formats shown in Figure 5
could actually be loaded in the LBADDR register of CUBIT-Pro Y instead of the single address control CellBus
Bus Routing Header of CUBIT-Pro X, with a corresponding change in the final destination of the loopback cell.
address of CUBIT-Pro X
15
0
0 1 - - - - 0 A A A A A H H H H
7
0
- - 0 A A A A A
CellBus Bus Routing Header
(single address control shown, see Figure 5)
LBADDRL (address 13H)
Memory Map of CUBIT-Pro Y
7
0
- - - - 0 1 - -
LBADDRU (address 14H)
Note: - indicates don’t care state
Figure 30. Loading the Loopback Registers
All aspects of system operation are the responsibility of the control system implemented for use of the
CUBIT-Pro devices. Care must be taken to ensure that no more than one CUBIT-Pro is trying to set up a loopback into the same CUBIT-Pro, or mis-routing will ensue.
TXC-05802B-MB
Ed. 3, February 2001
- 38 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
MEMORY MAP RESET STATES
The general conditions for resetting the memory map states are:
1. all input clock signals are present, and
2. the DEVHIZ and TSTMODE input pins are high.
There are two alternative reset conditions that reset the memory map registers 04H through FFH to the values
shown in the following table:
1. power-up, or
2. hardware reset applied via the RESET input pin.
Address (Hex)
0A
17
1E
60 - 93,
A0-D7
E0 - FF
Others
Reset Value (Hex)
40
XX(1)
XX(2)
XX(3)
XX(3)
00(4)
Notes:
1. Reset value depends on content of location 00H in TRAM.
2. Reset value depends on state of pins ABRENA, U32, ENARB and UA(4-0).
3. Undefined value after power-up. Pre-existing value is not affected by hardware reset.
4. Except reserved addresses, which contain undefined values after power-up and hardware reset.
5. It is recommended to provide the control processor an independent means of forcing an external hardware
reset. In order to insure proper device initialization, after the loss of either the CellBus Bus Write Clock or the
CellBus Bus Read Clock, an external hardware reset must be applied via the RESET pin. The hardware reset
must be applied in the presence of all input clock signals. Please note that one cell may remain in the Outlet
Synchronization FIFO after performance of a hardware reset, and it will flow to the Cell Outlet Port ahead of
cells received after the reset. This may occur when, before clock restoration and hardware reset,
a) the device was operating in 16-bit PHY mode, and
b) a loss of CellBus read or write clocks occurred while traffic was flowing into the device and there
were three cells stored in the Outlet Synchronization FIFO.
- 39 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
105
110
115
120
125
130
135
140
145
150
160
100
165
95
170
90
175
85
CUBIT-Pro
180
TXC-05802B
80
Pin Diagram
185
75
(Top View)
190
70
195
65
200
60
205
50
45
40
35
30
25
20
15
10
NC
CBD27VSS
CBD26CBD25VSS
CBD24CBD23VSS
CBD22CBD21VSS
CBD20NC
CBD19VSS
CBD18VDD3
CBD17VSS
CBD16CBD15VSS
CBD14CBD13VSS
CBRCCBWCVSS
CBD12CBD11VSS
CBD10NC
CBD9VSS
CBD8VDD3
CBD7VSS
CBD6CBD5VSS
CBD4CBD3VSS
CBD2CBD1VSS
CBD0CBFCBDISABLE-
U32UA4UA3UA2UA1UA0VSS
FRCABRCNG
VDDIO
A7
A6
VDDIO
A5
A4
VSS
A3
A2
A1
A0
VDDIO
D7
D6
VSS
D5
D4
D3
D2
VSS
D1
D0
VDD3
PCLK
VDD3
SELWRRD- or RD/WRVDDIO
INT/IRQRDY/DTACKMOTO
VSS
RESETVDDIO
TESTINLCLOCK
VSS
TSTOUT
PHYENVSS
CBACKCBCONGVSS
5
55
1
LMODE1LMODE0VSS
TRA15
TRA14
TRA13
TRA12
VDDIO
TRA11
TRA10
TRA9
TRA8
VDDIO
TRA7
TRA6
TRA5
TRA4
VSS
TRA3
TRA2
TRA1
TRA0
VDD3
COD7
COD6
VDDIO
COD5
COD4
VDDIO
COD3
COD2
VSS
COD1
COD0
VDD3
COCLAV
COSOC
VDDIO
COCLK
COENBVSS
GFC3
GFC2
VDDIO
GFC1
GFC0
VSS
SCAN2
SCAN1
TSTMODEDEVHIZENARB-
155
LMODE2NC
TRANABRENATRA16
VDDIO
TRA17
VSS
TRD0
TRD1
TRD2
TRD3
VDD3
TRD4
TRD5
TRD6
TRD7
VSS
TRWEVDDIO
TROEVSS
CID0
CID1
CID2
CID3
VDD3
CID4
CID5
CID6
CID7
VSS
CISOC
VDDIO
CICLK
CIENBCICLAV
VSS
NC
NC
VDD3
NC
NC
VSS
CBD31VSS
CBD30CBD29VSS
CBD28VREF
VDDBOOT
PIN DIAGRAM
Note: Due to space limitations, active low (inverted) or active-on-falling-edge signals are indicated by ‘-’ at the end of their
symbol (e.g., LMODE1- is equivalent to LMODE1).
Figure 31. CUBIT-Pro TXC-05802B Pin Diagram
TXC-05802B-MB
Ed. 3, February 2001
- 40 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
PIN DESCRIPTIONS
POWER SUPPLY, GROUND AND NO CONNECT PINS
Symbol
Pin No.
I/O/P*
Type
Name/Function
VDDIO
9, 12, 20, 37, 43, 123,
137, 151, 164, 169,
182, 185, 194, 200
P
VDDIO: +5 volt supply ±5% for dual-supply operation, or +3.3 volt supply ±5% (for single-supply
operation)
VDD3
31, 33, 67, 87, 116,
130, 144, 179, 191
P
VDD3: +3.3 volt supply, ±5%
VSS
7, 15, 23, 28, 41, 46,
49, 52, 56, 59, 62, 65,
69, 73, 76, 79, 82, 85,
89, 93, 96, 99, 102,
108, 111, 113, 119,
125, 135, 139, 149,
159, 174, 188, 197,
203
P
VSS: Ground, 0 volt reference.
VDDBOOT
105
P
VDDBOOT: This pin must be connected to +5.0
volt ±10% for dual-supply operation or +3.3 volt
±5% for single-supply operation. The voltage
must be present for the CellBus bus disable function to operate.
NC
71, 91, 104, 114, 115,
117, 118, 155
--
No Connect: NC pins are not to be connected,
not even to another NC pin, but must be left
floating. Connection of NC pins may impair performance or cause damage to the device. Some
NC pins may be assigned functions in future
upgrades of the device. Compatibility of the
CUBIT-Pro TXC-05802B device in existing
CUBIT TXC-05801 applications may rely upon
these pins having been left floating.
* Note: I=Input; O=Output; OD=Open Drain Output; P=Power
- 41 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
CELL INLET
Symbol**
Pin No.
I/O/P
Type*
CICLAV
120
I/O
TTL/
Cell Inlet Cell Available: The direction of the CICLAV signal
TTL 4 mA depends on the mode selected:
ATM Layer emulation: An active high input signal from the
PHY Layer device to indicate that it has a complete cell to
transfer. This applies to UTOPIA and 16-Bit modes.
PHY Layer emulation: An active high output signal to indicate
that the CUBIT-Pro has space to receive a cell from the ATM
Layer device. This applies to UTOPIA and 16-Bit modes.
Back-to-Back mode: CICLAV is an active high input signal.
CICLK
122
I/O
TTL/
Cell Inlet Clock: Transfer clock. Rising edge of CICLK is used
TTL 6 mA for data transfer.
ATM Layer emulation: The clock is an output. This applies to
UTOPIA and 16-Bit modes.
PHY Layer emulation: The clock is an input. This applies to
UTOPIA and 16-Bit modes.
Back-to-Back mode: The clock is an output.
Maximum clock speed of 42 MHz with a 40/60 duty cycle.
CID(7-4)
CID(3-0)/
126-129,
131-134
I
CIENB
121
I/O
CISOC
124
I
TTL
Name/Function
Cell Inlet Data: Byte-parallel input data.
TTL/
Cell Inlet Enable: The direction of the CIENB signal depends
TTL 4 mA on the mode selected:
ATM Layer emulation: An active low output signal indicating that
input data and CISOC will be sampled at the end of the next
cycle. This applies to UTOPIA, 16-Bit, and Back-to-Back
modes.
PHY Layer emulation: An active low input signal indicating that
input data and CISOC will be sampled at the end of the next
clock cycle. This applies to UTOPIA and 16-Bit modes.
TTL
Cell Inlet Start of Cell: Start-of-Cell indication for UTOPIA
and 16-Bit modes.
* See Input, Output and Input/Output Parameters section for Type definitions.
** Signals which are active when low or upon their falling edges are shown as negated (overlined).
TXC-05802B-MB
Ed. 3, February 2001
- 42 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
CELL OUTLET
Symbol
Pin No.
I/O/P
Type
Name/Function
COCLAV
192
I/O
TTL/
Cell Outlet Cell Available: The direction of the
TTL 4 mA COCLAV signal depends on the mode selected:
ATM Layer emulation: An active high input from the
PHY layer device to indicate that it can accept the
transfer of a complete cell. This applies to UTOPIA
and 16-Bit modes
PHY Layer emulation: An active high output that the
CUBIT-Pro asserts to indicate that it can transfer a
complete cell to the ATM layer device. This applies to
UTOPIA and 16-Bit modes.
Back-to-Back mode: COCLAV is an active high output signal.
COCLK
195
I/O
TTL/
Cell Outlet Clock: Transfer clock. Rising edge of
TTL 6 mA COCLK is used for data transfer.
ATM Layer emulation: This is an output clock. This
applies to UTOPIA and 16-Bit modes.
PHY Layer emulation: This is an input clock. This
applies to UTOPIA, Back-to-Back, and 16-Bit modes.
Maximum clock speed of 42 MHz with a 40/60 duty
cycle.
COD(7-6)
COD(5-4)
COD(3-2)
COD(1-0)
180, 181,
183, 184,
186, 187,
189, 190
O
TTL 4 mA Cell Outlet Data: Byte-parallel output data.
COENB
196
I/O
TTL/
Cell Outlet Enable: An active low enable signal
TTL 4 mA which occurs during clock cycles when COD(7-0)
data and/or COSOC are active.
ATM Layer emulation: An active low output signal.
This applies to UTOPIA and 16-Bit modes.
PHY Layer emulation: An active low input signal. This
applies to UTOPIA and 16-Bit modes.
Back-to-Back mode: COENB is an active low input
signal.
COSOC
193
O
TTL 4 mA Cell Outlet Start of Cell: Start-of-Cell for UTOPIA
and 16-Bit modes.
GFC(3-2)
GFC(1-0)
198, 199,
201, 202
I
TTLp
Generic Flow Control: Inlet for GFC nibble to be
inserted at cell outlet.
FRCABRCNG
8
I
TTLp
Force ABR Congestion: Active high signal to force a
congestion indication for any ABR cells received.
LCLOCK
45
I
TTLp
Line Clock: Rising edge used for data transfer. This
clock input is used for the cell Inlet/Outlet timing
assuming that CLKS1,CLKS0=0,1 in register 0BH.
- 43 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
CellBus BUS PORT
Symbol
Pin No.
I/O/P
Type
CBACK
50
I/O
GTL+
CellBus Bus Acknowledge: Active low
acknowledge.
CBCONG
51
I/O
GTL+
CellBus Bus Congestion Indicator: Active
low congestion indicator.
CBD(31-24)
112, 110, 109, 107,
103, 101, 100, 98
I/O
GTL+
CellBus Bus Data: Active low 32-bit parallel
data input/output bus.
CBD(23-16)
97, 95, 94, 92,
90, 88, 86, 84
I/O
GTL+
CBD(15-8)
83, 81, 80, 75,
74, 72, 70, 68
I/O
GTL+
CBD(7-0)
66, 64, 63, 61,
60, 58, 57, 55
I/O
GTL+
CBF
54
I/O
GTL+
CellBus Bus Frame: 16-clock cycle structure.
CBRC
78
I
GTL+
CellBus Bus Read Clock: Accepts data from
bus. Falling edge used for data transfer.
CBWC
77
I
GTL+
CellBus Bus Write Clock: Puts data on the
bus. Falling edge used for data transfer.
CBDISABLE
53
I
CMOS
CellBus Bus Disable: Active low signal to
tristate the entire CellBus bus regardless of the
state of the VDD3 and VDDIO power supplies.
(This signal is not part of the CellBus bus.)
VREF
106
I
TXC-05802B-MB
Ed. 3, February 2001
Name/Function
Reference VREF: Reference voltage for GTL+ receivers.
VREF is 2/3 Vtt, where Vtt is the backplane terVoltage
mination voltage (nominally Vtt = +1.5V). The
input connection to this pin is not part of the
CellBus bus.
- 44 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
MICROPROCESSOR PORT
Symbol
Pin No.
I/O/P
Type
Name/Function
A(7-6)
A(5-4)
A(3-0)
10, 11,
13, 14,
16-19
I
TTL
D(7-6)
D(5-2)
D(1-0)
21, 22,
24-27,
29, 30
I/O
TTL/
Data Bus: Bidirectional 8-bit data lines used for transferTTL 8 mA ring data to and from microprocessor. D0 is LSB. High is
logic 1.
INT/IRQ
38
O
TTL 4 mA Interrupt: Active high for Intel, active low for Motorola.
MOTO
40
I
TTL
Motorola Mode: Select Motorola operation if high, Intel if
low.
PCLK
32
I
TTL
Processor Clock: Rising edge used for data transfer.
RD or
RD/WR
36
I
TTL
Read/Write: Data transfer command for CUBIT-Pro memory. Read (low) for Intel. Read (high) / Write (low) for
Motorola.
RDY/DTACK
39
OD
SEL
34
I
TTL
Select: Active low signal to enable data transfer.
WR
35
I
TTL
Write: Active low write command for transferring data to
CUBIT-Pro memory in Intel mode. This input must be held
high in Motorola mode.
Address Bus: 8-bit address lines from microprocessor,
used to address CUBIT-Pro register memory. A0 is LSB.
High is logic 1.
TTL 6 mA Ready or Data Transfer Acknowledge: Active high
Ready for Intel, active low Data Transfer Acknowledge for
Motorola. This output is an open-drain buffer which
requires an external pull-up resistor.
TRANSLATION RAM ACCESS PORT
Symbol
Pin No.
I/O/P
Type
Name/Function
TRA(17-16)
TRA(15-12)
TRA(11-8)
TRA(7-4)
TRA(3-0)
150, 152,
160-163,
165-168,
170-173,
175-178
O
TTL 4 mA Translation RAM Address Bus: 18-bit address output for
up to 256k byte Translation RAM. TRA(7-0) are cell data
outlet 8 LSB if ABRENA is enabled. TRA0 is LSB. High is
logic 1.
TRD (7-4)
TRD (3-0)
140-143,
145-148
I/O
TTL/
Translation RAM Data Bus: Bidirectional 8-bit data bus.
TTL 4 mA TRD(7-0) are cell data inlet 8 LSB if ABRENA is enabled.
TRD0 is LSB. High is logic 1.
TROE
136
O
TTL 4 mA Translation RAM Output Enable: Active low output
enable.
TRWE
138
O
TTL 4 mA Translation RAM Write Enable: Active low write enable.
- 45 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
CONTROL STRAPS
Symbol*
Pin No.
I/O/P
Type
Name/Function
ABRENA
153
I
TTLp
16-Bit Mode Enable: Active low signal to select the
16-Bit operating mode. The additional 8 data bits are
carried by TRD(7-0) acting as the 8 LSB for cell data
inlet and by TRA(7-0) acting as the 8 LSB for cell data
outlet.
DEVHIZ
207
I
TTLp
Device High Impedance: Active low signal to set all
outputs to high-impedance (Hi-Z) state.
ENARB
208
I
TTLp
Enable Arbiter: Active low signal to enable internal
copy of Bus Arbiter and Frame Pulse Generator.
LMODE2
LMODE1
LMODE0
156,
157,
158
I
TTLp
Operating Mode: Three active low signals for selection of CUBIT-Pro cell Inlet/Outlet operating mode.
Please see Figures 6-8, 10, 11 for details.
TRAN
154
I
TTLp
Translation Enable: An active low signal to enable
header translation by the CUBIT-Pro.
UA(4-0)
2-6
I
TTLp
Unit Address: Five active low device identity straps,
used to identify each CUBIT-Pro device in a system
containing up to 32 devices.
U32
1
I
TTLp
Unit 32: Control strap for setting maximum number of
CUBIT-Pros that can be connected to the CellBus
bus. Set low for 32 CUBIT-Pros, high (or floating) for
16.
PHYEN
48
I
TTLp
PHY Layer Enable: a low enables PHY Layer emulation in UTOPIA and 16-Bit modes
* Note: All control straps are active low inputs. They are pulled up internally and will be inactive if left unconnected.
They must be set low to enable the associated function.
RESET AND TEST PINS
Symbol
Pin No.
I/O/P
Type
Name/Function
RESET
42
I
TTL
TSTMODE
206
I
--
Test Mode: Active low signal to enable device test by
manufacturer. Tie to VDDIO.
SCAN1
205
I
--
Scan 1: Internal test function. Tie to VSS.
SCAN2
204
I
--
Scan 2: Internal test function. Tie to VSS.
TSTOUT
47
O
--
Internal Test Pin: Leave floating.
TESTIN
44
I
--
Internal Test Mode Input: Tie to VDDIO.
Reset: Active low device reset (minimum duration
300 nanoseconds). See Note 1.
Note 1: Please see Note 5 on Page 39 regarding information in the Outlet Synchronization FIFO after a hardware reset.
TXC-05802B-MB
Ed. 3, February 2001
- 46 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
ABSOLUTE MAXIMUM RATINGS AND ENVIRONMENTAL LIMITATIONS
Parameter
Symbol
Min
Max
Unit
Conditions
Supply voltage, Input/Output
VDDIO
-0.3
+7.0
V
Note 1
Supply voltage, Core
VDD3
-0.3
+6.0
V
Note 1
DC input voltage
VIN
-0.3
VDDIO +0.3
V
Note 1
Storage temperature range
TS
-55
+150
oC
Note 1
Ambient operating temperature
TA
-40
+85
oC
0 ft/min linear airflow
Moisture Exposure Level
ME
5
Level
per EIA/JEDEC
JESD22-A112-A
Relative Humidity, during assembly
RH
30
60
%
Note 2
Relative Humidity, in-circuit
RH
0
100
%
non-condensing
V
Note 3 and 4
ESD Classification, Human Body Model (HBM)
ESD
absolute value 2000
Notes:
1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max
values for extended periods may impair device reliability.
2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION"
label on the drypack bag in which devices are supplied.
3. Absolute value 500 V only at the VDDIO and VDD3 pins. Meets new JEDEC Charged Device Model (CDM) standard,
JESD22-C101.
4. Test method for ESD per MIL-STD-883D, Method 3015.7.
THERMAL CHARACTERISTICS
Parameter
Min
Thermal resistance - junction to ambient
Typ
Max
29.5
Unit
Test Conditions
oC/W
0 ft/min linear airflow
POWER REQUIREMENTS
Parameter
VDDIO
Min
Typ
Max
4.75
3.15
5.00
3.30
25
125
85
3.30
106
350
5.00
3.30
0.01
0.05
475
435
5.25
3.45
48
250
170
3.45
289
1000
5.50
3.45
0.10
0.55
1250
1170
IDDIO
PDDIO
VDD3
IDD3
PDD3
VDDBOOT
IDDBOOT
PDDBOOT
PTOTAL
3.15
4.50
3.15
Unit
V
mA
mW
V
mA
mW
V
mA
mW
mW
Test Conditions
Dual-supply operation
Single-supply operation
See Notes 1 and 2
Dual-supply operation
Single-supply operation
See Notes 1 and 2
See Notes 1 and 2
Dual-supply operation 5.0 V ±10%
Single-supply operation 3.3 V ±5%
See Note 2
See Note 2
Dual-supply operation
Single-supply operation
Notes:
1. Typical values are based on measurements made with nominal voltages, 25 oC ambient, and 40 MHz UTOPIA and
CellBus bus clocks.
2. All IDD and PDD values are dependent upon VDD and the bus operation.
- 47 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
INPUT, OUTPUT AND INPUT/OUTPUT PARAMETERS
INPUT PARAMETERS FOR CMOS
Parameter
VIH
Min
Typ
Max
Unit
0.7 * VDDIO
V
Test Conditions
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
VIL
0.2 * VDDIO
V
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
Input leakage current
-10
1
Input capacitance
µA
10
5
pF
INPUT PARAMETERS FOR TTL
Parameter
VIH
Min
Typ
Max
Unit
2.0
V
Test Conditions
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
VIL
0.8
V
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
Input leakage current
10
Input capacitance
5
µA
pF
INPUT PARAMETERS FOR TTLP (TTL WITH INTERNAL PULL-UP)
Parameter
VIH
Min
Typ
Max
Unit
2.0
V
Test Conditions
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
VIL
0.8
V
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
Input current
-35
-115
Input leakage current
Input capacitance
-214
µA
VIN=VSS
10
µA
VIN=VDDIO(Max)
5
pF
OUTPUT PARAMETERS FOR TTL 4 MA
Parameter
VOH
Min
Typ
Max
2.4
Unit
Test Conditions
V
IOH = -4.0 mA
0.4
V
IOL = 4.0 mA
10
µA
IOL
4.0
mA
IOH
-4.0
mA
VOL
Tristate leakage current
TXC-05802B-MB
Ed. 3, February 2001
0.2
-10
- 48 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
OUTPUT PARAMETERS FOR 6 MA (OPEN-DRAIN)
Parameter
Min
Typ
Max
Unit
VOL
0.4
V
IOL
6.0
mA
Test Conditions
VDDIO=VDDIO(Min); IOL= 6.0 mA
Note: Open Drain requires use of a 4.7 kΩ external pull-up resistor to VDDIO. If this resistor is not provided the output
behaves as tristate.
OUTPUT PARAMETERS FOR TTL 6 MA
Parameter
Min
Typ
Max
Unit
2.4
Test Conditions
V
IOH = -6.0 mA
0.4
V
IOL = 6.0 mA
10
µA
IOL
6.0
mA
IOH
-6.0
mA
Max
Unit
VOH
VOL
0.2
Tristate leakage current
-10
OUTPUT PARAMETERS FOR TTL 8 MA
Parameter
Min
Typ
2.4
Test Conditions
V
IOH = -8.0 mA
0.4
V
IOL = 8.0 mA
10
µA
IOL
8.0
mA
IOH
-8.0
mA
VOH
VOL
0.2
Tristate leakage current
-10
INPUT/OUTPUT PARAMETERS FOR GTL+
Parameter
VIH
Min
Typ
Max
VREF + 0.1
Unit
V
Test Conditions
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
VIL
VREF - 0.1
V
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
Input leakage current
Input capacitance
5.5
VOL
Tristate leakage current
-10
IOL
45
Slew Rate
0.3
10
µA
6.0
pF
0.5
V
10
µA
0.8
- 49 of 90 -
VIN= VDDIO(Max)
IOL = 50 mA
mA
50Ω Terminations to 1.5 V
V/ns
25Ω, 30 pF Test Load
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
INPUT/OUTPUT PARAMETERS FOR TTL/TTL 4 MA
Parameter
VIH
Min
Typ
Max
Unit
2.0
Test Conditions
V
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
VIL
0.8
V
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
Input leakage current
10
Input capacitance
VOH
7
µA
VIN= VDDIO(Max)
pF
2.4
V
VDDIO = VDDIO(Min); IOH= -4.0
0.4
V
VDDIO = VDDIO(Min); IOL= 4.0
IOL
4.0
mA
IOH
-4.0
mA
VOL
INPUT/OUTPUT PARAMETERS FOR TTL/TTL 6 MA
Parameter
VIH
Min
Typ
Max
2.0
Unit
Test Conditions
V
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
VIL
0.8
V
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
Input leakage current
VOH
µA
10
Input capacitance
7
VIN= VDDIO(Max)
pF
2.4
V
VDDIO = VDDIO(Min); IOH= -6.0
0.4
V
VDDIO = VDDIO(Min); IOL= 6.0
IOL
6.0
mA
IOH
-6.0
mA
VOL
INPUT/OUTPUT PARAMETERS FOR TTL/TTL 8 MA
Parameter
VIH
Min
Typ
Max
2.0
Unit
V
Test Conditions
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
VIL
0.8
V
4.75 < VDDIO < 5.25 (dual-supply)
3.15 < VDDIO < 3.45 (single-supply)
Input leakage current
10
Input capacitance
VOH
7
µA
VIN= VDDIO(Max)
pF
V
VDDIO = VDDIO(Min); IOH= -8.0
0.4
V
VDDIO = VDDIO(Min); IOL= 8.0
IOL
8.0
mA
IOH
-8.0
mA
VOL
TXC-05802B-MB
Ed. 3, February 2001
2.4
- 50 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
TIMING CHARACTERISTICS
Detailed timing diagrams for the CUBIT-Pro device are provided in Figures 32 through 51, with values for the
timing intervals given in tables below the waveform drawings. All output times are measured with a maximum
load capacitance of 25 pF unless otherwise indicated. Timing parameters are measured at voltage levels of
(VIH+VIL)/2 for input signals or (VOH+VOL)/2 for output signals.
DUTY CYCLE OF INPUT CLOCK SIGNALS
The duty cycle of the input clock signals is defined as the ratio of the duration of the high pulse to the clock signal period, express as a percentage. The required duty cycle values are defined in the following table:
Input Clock
Symbol
Input Clock Duty Cycle
Min
Typ
Max
Unit
CICLK
40
60
%
PCLK
40
60
%
COCLK
40
60
%
LCLOCK
40
60
%
CBRC
40
60
%
CBWC
40
60
%
FREQUENCY OF INPUT CLOCK SIGNALS
The required frequency values are defined in the following table:
Input Clock
Symbol
Input Clock Frequency
Min
Typ
Max
Unit
CICLK
42
MHz
PCLK
42
MHz
COCLK
42
MHz
LCLOCK
42
MHz
CBRC
42
MHz
CBWC
42
MHz
CONTROL / TRANSLATION RAM INTERFACE
The timing for the translation RAM interface has to be referenced to the appropriate clock selection for the cell
inlet clock. Therefore, the timing shown in Figures 32 and 33 shows timings with respect to four different
clocks:
CBWC: CLKS[1:0] = 0,0 in UTOPIA/16-Bit (ATM Layer) and Back-to-Back modes
LCLOCK: CLKS[1:0] = 0,1 in UTOPIA/16-Bit (ATM Layer) and Back-to-Back modes
PCLK: CLKS[1:0] = 1,0 in UTOPIA/16-Bit (ATM Layer) and Back-to-Back modes
CICLK: PHYEN = Low only for UTOPIA/16-Bit (PHY Layer)
- 51 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Figure 32. Translation RAM Timing - Read from RAM
CICLK
(Input)
PCLK
(Input)
LCLOCK
(Input)
tD(1a)
tD(2a)
tSU(1a)
tH(1a)
tD(1b)
tD(2b)
tSU(1b)
tH(1b)
tD(1c)
tD(2c)
tSU(1c)
tH(1c)
CBWC
(Input)
tD(1d)
TROE
(Output)
tD(2d)
TRA(17-0)
(Output)
tSU(1d)
TRD(7-0)
(Input)
Data
Valid
Data
Valid
Data
Valid
tH(1d)
Microprocessordirected read cycle
from RAM
Translation RAM read cycle
Parameter
Symbol
Min
TROE output delay after CICLK↑ (PHY Mode)
tD(1a)
TROE output delay after PCLK↑
Typ
Max for VDDIO of
Unit
5V
3.3 V
4.0
14
17
ns
tD(1b)
4.0
16
19
ns
TROE output delay after LCLOCK↑
tD(1c)
4.0
14
17
ns
TROE output delay after CBWC↓
tD(1d)
4.0
20
23
ns
TRA(17-0) output delay after CICLK↑
tD(2a)
4.0
16
19
ns
TRA(17-0) output delay after PCLK↑
tD(2b)
4.0
16
19
ns
TRA(17-0) output delay after LCLOCK↑
tD(2c)
4.0
16
19
ns
TRA(17-0) output delay after CBWC↓
tD(2d)
4.0
21
24
ns
TRD(7-0) setup time before CICLK↑
tSU(1a)
1.0
ns
TRD(7-0) setup time before PCLK↑
tSU(1b)
1.0
ns
TRD(7-0) setup time before LCLOCK↑
tSU(1c)
1.0
ns
TRD(7-0) setup time before CBWC↓
tSU(1d)
1.0
ns
TRD(7-0) hold time after CICLK↑
tH(1a)
6.0
ns
TRD(7-0) hold time after PCLK↑
tH(1b)
6.0
ns
TRD(7-0) hold time after LCLOCK↑
tH(1c)
6.0
ns
TRD(7-0) hold time after CBWC↓
tH(1d)
11
ns
Note: TRWE output is high. All timing parameter values apply to both Microprocessor and Translation RAM read cycles.
TXC-05802B-MB
Ed. 3, February 2001
- 52 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Figure 33. Translation RAM Timing - Write to RAM
CICLK
(Input)
tD(2a)
PCLK
(Input)
tD(2b)
LCLOCK
(Input)
tD(2c)
tD(1a)
tD(3a)
tZ(1a)
tD(1b)
tZ(1b)
tD(3b)
tD(1c)
tD(3c)
tZ(1c)
tD(1d)
tZ(1d)
CBWC
(Input)
TRD(7-0)
(Output)
tD(2d)
TRA(17-0)
(Output)
TROE
(Output)
tD(3d)
TRWE
(Output)
RAM Read
Cycle
Microprocessor-directed
Write Cycle to RAM
Parameter
Symbol
Min
TRD(7-0) delay from tristate after CICLK↑
tD(1a)
TRD(7-0) delay from tristate after PCLK↑
Typ
Max for VDDIO of
Unit
5V
3.3 V
4.0
16
19
ns
tD(1b)
4.0
16
19
ns
TRD(7-0) delay from tristate after LCLOCK↑
tD(1c)
4.0
16
19
ns
TRD(7-0) delay from tristate after CBWC↓
tD(1d)
4.0
21
24
ns
TRD(7-0) delay to tristate after CICLK↑
tZ(1a)
4.0
16
19
ns
TRD(7-0) delay to tristate after PCLK↑
tZ(1b)
4.0
16
19
ns
TRD(7-0) delay to tristate after LCLOCK↑
tZ(1c)
4.0
16
19
ns
TRD(7-0) delay to tristate after CBWC↓
tZ(1d)
4.0
21
24
ns
TRA(17-0) delay after CICLK↑
tD(2a)
4.0
16
19
ns
TRA(17-0) delay after PCLK↑
tD(2b)
4.0
17
20
ns
TRA(17-0) delay after LCLOCK↑
tD(2c)
4.0
16
19
ns
TRA(17-0) delay after CBWC↓
tD(2d)
4.0
21
24
ns
TRWE delay after CICLK↓
tD(3a)
4.0
15
18
ns
TRWE delay after PCLK↓
tD(3b)
4.0
14
17
ns
TRWE delay after LCLOCK↓
tD(3c)
4.0
14
17
ns
TRWE delay after CBWC↑
tD(3d)
4.0
18
21
ns
- 53 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
CELL INTERFACE
Note: For all cell interface timing diagrams, the 48 payload bytes of the cell are labelled as P0 through P47.
This is consistent with Figures 9 and 12, which describe the byte/word ordering of the four cell interface
modes.
Cell Inlet, UTOPIA Mode
ATM Layer Emulation Timing (Receive UTOPIA Interface Timing)
Figure 34. Timing of UTOPIA (ATM Layer Emulation) Cell Inlet Interface
CICLK
(Output)
tSU(1)
tH(1)
CICLAV
(Input)
tD(1)
CIENB
(Output)
tD(1)
Case if there are back-to-back cells (dashed lines above)
CID(7-0)
(Input)
H1
H2
tSU(3)
P46
P47
P46
P47
H1
H2
H3
tH(3)
tSU(2)
tH(2)
CISOC
(Input)
Case if FIFO is full (solid lines above)
CID(7-0)
(Input)
H1
tSU(2)
CISOC
(Input)
Parameter
tSU(3)
H2
H1
H2
tH(3)
tH(2)
Unit
Min
CICLAV setup time before CICLK↑
tSU(1)
10.5
ns
CICLAV hold time after CICLK↑
tH(1)
1.0
ns
CIENB delay after CICLK↑
tD(1)
1.0
CISOC setup time before CICLK↑
tSU(2)
9.5
ns
CISOC hold time after CICLK↑
tH(2)
1.0
ns
CID(7-0) setup time before CICLK↑
tSU(3)
10.0
ns
CID(7-0) hold time after CICLK↑
tH(3)
1.0
ns
TXC-05802B-MB
Ed. 3, February 2001
- 54 of 90 -
Typ
Max for VDDIO of
Symbol
5V
9.0
3.3 V
12
ns
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
PHY Layer Emulation Timing (Transmit UTOPIA Interface Timing)
Figure 35. Timing of UTOPIA (PHY Layer Emulation) Cell Inlet Interface
CICLK
(Input)
tD(1)
CICLAV
(Output)
tH(1)
tSU(1)
CIENB
(Input)
Case if there are back-to-back cells (dashed lines above)
CID(7-0)
(Input)
H1
H2
H3
tSU(3)
P43
P44
P45
P46
P47
P45
P46
P47
H1
H2
tH(3)
tSU(2)
CISOC
(Input)
tH(2)
Case if FIFO is full (solid lines above)
CID(7-0)
(Input)
H1
tSU(3)
H2
H3
P43
tSU(2)
CISOC
(Input)
Parameter
P44
tH(3)
tH(2)
Min
CICLAV delay from CICLK↑
tD(1)
1.0
CIENB setup time before CICLK↑
tSU(1)
6.0
ns
CIENB hold time after CICLK↑
tH(1)
0.0
ns
CISOC setup time before CICLK↑
tSU(2)
6.0
ns
CISOC hold time after CICLK↑
tH(2)
1.0
ns
CID(7-0) setup time before CICLK↑
tSU(3)
6.0
ns
CID(7-0) hold time after CICLK↑
tH(3)
1.0
ns
- 55 of 90 -
Typ
Max for VDDIO of
Symbol
5V
3.3 V
18
21
Unit
ns
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Cell Outlet, UTOPIA Mode
ATM Layer Emulation Timing (Transmit UTOPIA Interface Timing)
Figure 36. Timing of UTOPIA (ATM Layer Emulation) Cell Outlet Interface
COCLK
(Output)
tSU(1)
tH(1)
COCLAV
(Input)
COENB
(Output)
tD(1)
Case if COCLAV is solid line, one cell
tD(2)
COD(7-0)
(Output)
H1
H2
P43
P44
P45
P46
P47
P45
P46
P47
X
X
Case if COCLAV is dotted line, two consecutive cells
COD(7-0)
(Output)
COSOC
(Output)
H1
H2
P43
P44
H1
tD(3)
Parameter
Unit
Min
COCLAV setup time before COCLK↑
tSU(1)
6.0
ns
COCLAV hold time after COCLK↑
tH(1)
1.0
ns
COENB delay after COCLK↑
tD(1)
1.0
6.0
9.0
ns
COD(7-0) delay after COCLK↑
tD(2)
1.0
8.0
11
ns
COSOC delay after COCLK↑
tD(3)
1.0
7.0
10
ns
TXC-05802B-MB
Ed. 3, February 2001
- 56 of 90 -
Typ
Max for VDDIO of
Symbol
5V
3.3 V
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
PHY Layer Emulation Timing (Receive UTOPIA Interface Timing)
Figure 37. Timing of UTOPIA (PHY Layer Emulation) Cell Outlet Interface
COCLK
(Input)
tD(1)
COCLAV
(Output)
tH(1)
COENB
(Input)
tSU(1)
Case if COCLAV is solid line, one cell
tD(2)
COD(7-0)*
(Output)
H1
H2
P44
P45
X
P46
P47
X
P46
P47
X
X
Case if COCLAV is dotted line, two consecutive cells
COD(7-0)*
(Output)
COSOC*
(Output)
H1
H2
P44
P45
H1
X
H2
tD(3)
* Note: The COD(7-0) and COSOC outputs are tristated if the COENB input is changed to high.
Parameter
Unit
Min
COCLAV delay after COCLK↑
tD(1)
1.0
COENB setup time before COCLK↑
tSU(1)
9.0
ns
COENB hold time after COCLK↑
tH(1)
1.0
ns
COD(7-0) delay after COCLK↑
tD(2)
1.0
15
18
ns
COSOC delay after COCLK↑
tD(3)
1.0
15
18
ns
- 57 of 90 -
Typ
Max for VDDIO of
Symbol
5V
3.3 V
12
15
ns
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Cell Inlet, 16-Bit Cell Interface Mode
ATM Layer Emulation Timing (Receive UTOPIA Interface Timing)
Figure 38. Timing of 16-Bit (ATM Layer Emulation) Cell Inlet Interface
CICLK
(Output)
tSU(1)
tH(1)
CICLAV
(Input)
tD(1)
CIENB
(Output)
tD(1)
Case if there are back-to-back cells (dashed lines above)
TRD(7-0)
(Input)
H2*
H4
tSU(4)
P45
tH(4)
CID(7-0)
(Input)
H1*
H3
P47
H2
H4
H1
H3
tSU(3)
P44
P46
P45
P47
H2
H4
P44
P46
H1
H3
tH(3)
tSU(2)
tH(2)
CISOC
(Input)
Case if FIFO is full (solid lines above)
TRD(7-0)
(Input)
H2*
CID(7-0)
(Input)
H1*
tSU(4)
H4
tH(4)
tSU(3)
tSU(2)
CISOC
(Input)
Parameter
H3
tH(3)
tH(2)
Min
CICLAV setup time before CICLK↑
tSU(1)
10.5
ns
CICLAV hold time after CICLK↑
tH(1)
1.0
ns
CIENB delay after CICLK↑
tD(1)
1.0
CISOC setup time before CICLK↑
tSU(2)
9.5
ns
CISOC hold time after CICLK↑
tH(2)
1.0
ns
CID(7-0) setup time before CICLK↑
tSU(3)
10.0
ns
CID(7-0) hold time after CICLK↑
tH(3)
1.0
ns
TRD(7-0) setup time before CICLK↑
tSU(4)
6.0
ns
TRD(7-0) hold time after CICLK↑
tH(4)
1.0
ns
TXC-05802B-MB
Ed. 3, February 2001
- 58 of 90 -
Typ
Max for VDDIO of
Symbol
5V
9.0
3.3 V
12
Unit
ns
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
PHY Layer Emulation Timing (Transmit UTOPIA Interface Timing)
Figure 39. Timing of 16-Bit (PHY Layer Emulation) Cell Inlet Interface
CICLK
(Input)
tD(1)
CICLAV
(Output)
tH(1)
tSU(1)
CIENB
(Input)
Case if there are back-to-back cells (dashed lines above)
TRD(7-0)
(Input)
H2*
H4
UDF
tSU(4)
P39
P41
P43
P45
P47
H2
H4
P42
P44
P46
H1
H2
P43
P45
P47
P42
P44
P46
tH(4)
tSU(3)
CID(7-0)
(Input)
H1*
H3
H5
P38
P40
tH(3)
tSU(2)
CISOC
(Input)
tH(2)
Case if FIFO is full (solid lines above)
TRD(7-0)
(Input)
H2
CID(7-0)
(Input)
H1
tSU(4)
H4
UDF
P39
P41
tH(4)
tSU(3)
H3
H5
P38
P40
tH(3)
tSU(2)
CISOC
(Input)
Parameter
tH(2)
Unit
Min
CICLAV delay from CICLK↑
tD(1)
1.0
CIENB setup time before CICLK↑
tSU(1)
6.0
ns
CIENB hold time after CICLK↑
tH(1)
0.0
ns
CISOC setup time before CICLK↑
tSU(2)
6.0
ns
CISOC hold time after CICLK↑
tH(2)
1.0
ns
CID(7-0) setup time before CICLK↑
tSU(3)
6.0
ns
CID(7-0) hold time after CICLK↑
tH(3)
1.0
ns
TRD(7-0) setup time before CICLK↑
tSU(4)
6.0
ns
TRD(7-0) hold time after CICLK↑
tH(4)
1.0
ns
- 59 of 90 -
Typ
Max for VDDIO of
Symbol
5V
3.3 V
18
21
ns
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Cell Outlet, 16-Bit Cell Interface Mode
ATM Layer Emulation Timing (Transmit UTOPIA Interface Timing)
Figure 40. Timing of 16-Bit (ATM Layer Emulation) Cell Outlet Interface
COCLK
(Output)
tSU(1)
tH(1)
COCLAV
(Input)
COENB
(Output)
tD(1)
Case if COCLAV is solid line, one cell
tD(4)
TRA(7-0)
(Output)
H2*
H4
COD(7-0)
(Output)
H1*
H3
P39
P41
P43
P45
P47
X
X
P38
P40
P42
P44
P46
X
X
tD(3)
Case if COCLAV is dotted line, two consecutive cells
tD(4)
TRA(7-0)
(Output)
H2
COD(7-0)
(Output)
H1
COSOC
(Output)
H4
P39
P41
P43
P45
P47
X
H2
P38
P40
P42
P44
P46
X
H1
tD(3)
H3
tD(2)
Parameter
Min
COCLAV setup time before COCLK↑
tSU(1)
6.0
ns
COCLAV hold time after COCLK↑
tH(1)
1.0
ns
COENB delay after COCLK↑
tD(1)
1.0
6.0
9.0
ns
COSOC delay after COCLK↑
tD(2)
1.0
7.0
10
ns
COD(7-0) delay after COCLK↑
tD(3)
1.0
8.0
11
ns
TRA(7-0) delay after COCLK↑
tD(4)
1.0
7.0
10
ns
TXC-05802B-MB
Ed. 3, February 2001
- 60 of 90 -
Typ
Max for VDDIO of
Symbol
5V
3.3 V
Unit
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
PHY Layer Emulation Timing (Receive UTOPIA Interface Timing)
Figure 41. Timing of 16-Bit (PHY Layer Emulation) Cell Outlet Interface
COCLK
(Input)
tD(1)
COCLAV
(Output)
tH(1)
COENB
(Input)
tSU(1)
Case if COCLAV is solid line, one cell
tD(4)
TRA(7-0)*
(Output)
H2*
H4
COD(7-0)*
(Output)
H1*
H3
P41
P43
X
P45
P47
X
X
P40
P42
X
P44
P46
X
X
tD(3)
Case if COCLAV is dotted line, two consecutive cells
tD(4)
TRA(7-0)*
(Output)
H2
H4
COD(7-0)*
(Output)
H1
H3
COSOC*
(Output)
P41
P43
X
P45
P47
X
H2
H4
P40
P42
X
P44
P46
X
H1
H3
tD(3)
tD(2)
* Note: The TRA(7-0), COD(7-0) and COSOC outputs are tristated if the COENB input is changed to high.
Parameter
Unit
Min
COCLAV delay after COCLK↑
tD(1)
1.0
COENB setup time before COCLK↑
tSU(1)
9.0
ns
COENB hold time after COCLK↑
tH(1)
1.0
ns
COSOC delay after COCLK↑
tD(2)
1.0
15
18
ns
COD(7-0) delay after COCLK↑
tD(3)
1.0
16
19
ns
TRA(7-0) delay after COCLK↑
tD(4)
1.0
15
18
ns
- 61 of 90 -
Typ
Max for VDDIO of
Symbol
5V
3.3 V
12
15
ns
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Cell Inlet, Back-to-Back Mode
Figure 42. Timing of Back-to-Back Cell Receive Interface
CICLK
(Output)
tH(1)
tSU(1)
CICLAV
(Input)
tD(1)
CIENB
(Output)
CID(7-0)
(Input)
tSU(2)
H1
tSU(3)
CISOC
(Input)
Parameter
H2
P46
P47
tH(2)
tH(3)
Unit
Min
CICLAV setup time before CICLK↑
tSU(1)
10
ns
CICLAV hold time after CICLK↑
tH(1)
0.0
ns
CIENB delay after CICLK↑
tD(1)
1.0
CID(7-0) setup time before CICLK↑
tSU(2)
9.0
ns
CID(7-0) hold time after CICLK↑
tH(2)
0.0
ns
CISOC setup time before CICLK↑
tSU(3)
9.0
ns
CISOC hold time after CICLK↑
tH(3)
0.0
ns
TXC-05802B-MB
Ed. 3, February 2001
- 62 of 90 -
Typ
Max for VDDIO of
Symbol
5V
9.0
3.3 V
12
ns
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Cell Outlet, Back-to-Back Mode
Figure 43. Timing of Back-to-Back Cell Transmit Interface
COCLK
(Input)
tD(1)
tD(1)
COCLAV
(Output)
tSU(1)
tH(1)
COENB
(Input)
tD(2)
COD(7-0)
(Output)
H1
H2
P46
P47
tD(3)
COSOC
(Output)
Parameter
Symbol
Min
Typ
Max for VDDIO of
5V
3.3 V
16
19
Unit
ns
COCLAV delay after COCLK↑
tD(1)
COENB setup time before COCLK↑
tSU(1)
18
ns
COENB hold time after COCLK↑
tH(1)
0.0
ns
COD(7-0) delay after COCLK↑
tD(2)
15
18
ns
COSOC delay after COCLK↑
tD(3)
15
18
ns
- 63 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
GFC Field Insertion
Figure 44. GFC Field Insertion Timing
COCLK
(Input or Output)*
COD(7-0)
(Output)
H1
H2
H3
H4
H5
P0
tSU(1)
tSU(2)
GFC(3-0)
(Input)
tH(1)
tH(2)
* Note: Output signal for UTOPIA and 16-Bit ATM Layer emulation modes.
Input signal for UTOPIA and 16-Bit PHY Layer emulation modes and Back-to-Back mode.
ATM Mode
Parameter
Symbol
Min
Typ
Max
Unit
GFC(3-0) setup time before COCLK↑
tSU(1)
4.0
ns
GFC(3-0) hold time after COCLK↑
tH(1)
0.0
ns
Symbol
Min
GFC(3-0) setup time before COCLK↑
tSU(2)
0.0
ns
GFC(3-0) hold time after COCLK↑
tH(2)
4.0
ns
PHY Mode
Parameter
TXC-05802B-MB
Ed. 3, February 2001
- 64 of 90 -
Typ
Max
Unit
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
CellBus BUS PORT
Figure 45. CellBus Bus Timing
CBRC
(Input)
Data inputs from bus
tSU(1)
CBD(31-0)
CBF
CBACK
CBCONG
tH(1)
CBWC
(Input)
Data outputs to bus
tD(1)
CBD(31-0)
CBF
CBACK
CBCONG
Parameter
Symbol
Min
Typ
Max
CellBus bus inputs setup time before
CBRC↓
tSU(1)
0.0
ns
CellBus bus inputs hold time after CBRC↓
tH(1)
6.0
ns
CellBus bus outputs delay after CBWC↓
tD(1)
5.0
See note
Unit
ns
Note:
The CUBIT-Pro CellBus write clock to CellBus data out time delay tD(1) has two components, internal delay and GTL+
driver delay. The internal delay consists of the delay from the CBWC input, through the GTL+ receiver, internal CUBIT-Pro
circuitry and into the (internal) input pin of the GTL+ driver. This internal delay is dependent solely on temperature and process variation and has minimum and maximum values of 5.0 ns and 11 ns, respectively. The GTL+ driver delay includes
the effects of the (internal) GTL+ driver and all external loading, from the chip bond wire inductance onwards. For the purposes of specification, a test load is used which consists of a 13 nH bond wire inductance from the VLSI device output pad
to the package output pin, and a 50 ohm resistor to +1.5 volts with a 1.0 pF capacitor to ground from the package output
pin. The total value of tD(1) is increased to 5.0 ns minimum and 18 ns maximum when using this load.
These output delay values by themselves may be inadequate to complete a system design. TranSwitch strongly recommends that all CellBus applications should be analyzed by high speed backplane and simulation specialists, using such
tools as HSpice® analog circuit simulation.
These simulations can model timing from one CUBIT-Pro, through various levels of system interconnect, to another
CUBIT-Pro, and include the effects of the device package, printed circuit board, connectors and backplane. The results of
these simulations, when added to the internal delay, will provide the actual value of tD(1) for a given system. TranSwitch is
able to support simulations by providing up-to-date models of the GTL+ transceiver used within the CUBIT-Pro.
Please contact the TranSwitch Applications Engineering Department for additional information, a list of proven high speed
simulation consultants and support.
Note: HSpice is a registered trademark of Meta-Software, Inc.
- 65 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Figure 46. CellBus Bus Frame Position, 16-User and 32-User Applications
CBRC
(Input)
CBWC
(Input)
CBF*
(U32 pin at VDDIO, 16-user)
CBF*
(U32 pin at VSS, 32-user)
*Note: Output from the CUBIT-Pro that is selected to perform the bus arbitration function.
Input to all other CUBIT-Pros on the CellBus bus.
TXC-05802B-MB
Ed. 3, February 2001
- 66 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Microprocessor Interface
Intel Mode: Read Cycle
Figure 47. Intel Microprocessor Read Cycle Timing
A(7-0)
(Input)
D(7-0)
(Output)
tD(1)
tF
tSU(1)
SEL
(Input)
tSU(2)
tH(1)
RD
(Input)
tH(2)
tD(2)
RDY
(Output)
(Note 2)
tPW(1)
Parameter
Unit
Min
A(7-0) setup time to SEL↓
tSU(1)
0.0
ns
D(7-0) valid delay after RDY↑
tD(1)
-10
ns
tF
1.0
SEL setup time to RD↓
tSU(2)
0.0
ns
SEL hold time after RD↑
tH(1)
0.0
ns
RD hold time after RDY↑
tH(2)
0.0
ns
RDY delay after RD↓
tD(2)
0.0
12
tPW(1)
0.0
Note 1
D(7-0) float time to tristate after RD↑
RDY pulse width
Typ
Max for VDDIO of
Symbol
5V
5.0
3.3 V
8.0
15
ns
ns
ns
Notes:
1. The CUBIT-Pro will hold off the microprocessor for a period of up to 32 periods of the CellBus bus, LCLOCK or PCLK
clock selected by the settings of control bits CLKS1 and CLKS0 (bits 5 and 4 in register 0BH). This occurs only during
accesses to the external Translation RAM.
2. RDY is an open drain output signal pin that requires a pull-up resistor to VDDIO for proper operation.
- 67 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Intel Mode: Write Cycle
Figure 48. Intel Microprocessor Write Cycle Timing
A(7-0)
(Input)
tSU(2)
tH(1)
D(7-0)
(Input)
tSU(1)
SEL
(Input)
tSU(3)
WR
(Input)
tH(2)
tD(1)
RDY
(Output)
(Note 2)
tPW(1)
Parameter
Unit
Min
A(7-0) setup time to SEL↓
tSU(2)
0.0
ns
D(7-0) hold time after WR↑
tH(1)
5.0
ns
WR hold after RDY↑
tH(2)
0.0
ns
D(7-0) valid setup time to WR↓
tSU(1)
0.0
ns
SEL setup time to WR↓
tSU(3)
0.0
ns
RDY delay after WR↓
tD(1)
0.0
tPW(1)
0.0
RDY pulse width
Typ
Max for VDDIO of
Symbol
5V
3.3 V
12
15
Note 1
ns
ns
Notes:
1. The CUBIT-Pro will hold off the microprocessor for a period of up to 32 periods of the CellBus bus, LCLOCK or PCLK
clock selected by the settings of control bits CLKS1 and CLKS0 (bits 5 and 4 in register 0BH). This occurs only during
accesses to the external Translation RAM.
2. RDY is an open drain output signal pin that requires a pull-up resistor to VDDIO for proper operation.
TXC-05802B-MB
Ed. 3, February 2001
- 68 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Motorola Mode: Read Cycle
Figure 49. Motorola Microprocessor Read Cycle Timing
A(7-0)
(Input)
D(7-0)
(Output)
tSU(1)
tH(1)
SEL
(Input)
tSU(2)
RD/WR
(Input)
tD(1)
tH(2)
DTACK
(Output)
tF
tD(2)
Parameter
Typ
Max for VDDIO of
Unit
Symbol
Min
A(7-0) valid setup time to SEL↓
tSU(1)
0.0
D(7-0) hold time after SEL↑
tH(1)
1.0
D(7-0) output delay after DTACK↓
tD(1)
SEL hold time after DTACK↓
tH(2)
5.0
ns
RD/WR setup time to SEL↓
tSU(2)
0.0
ns
DTACK↓ delay time from SEL↓
tD(2)
2*PCLK
Note 1
DTACK↓ float time after SEL↑
tF
1.0
10
5V
3.3 V
ns
5.0
8.0
0.0
ns
ns
ns
13
ns
Note 1: The CUBIT-Pro will hold off the microprocessor for a period of up to 32 periods of the CellBus bus, LCLOCK or
PCLK clock selected by the settings of control bits CLKS1 and CLKS0 (bits 5 and 4 in register 0BH). This occurs only during accesses to the external Translation RAM.
- 69 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Motorola Mode: Write Cycle
Figure 50. Motorola Microprocessor Write Cycle Timing
A(7-0)
(Input)
tSU(2)
D(7-0)
(Input)
tH(1)
tSU(1)
tH(2)
SEL
(Input)
tSU(3)
RD/WR
(Input)
tF
DTACK
(Output)
tD(1)
Parameter
Unit
Min
A(7-0) valid setup time to SEL↓
tSU(2)
0.0
ns
D(7-0) valid setup time to SEL↓
tSU(1)
0.0
ns
D(7-0) hold time after SEL↑
tH(1)
0.0
ns
SEL hold time after DTACK↓
tH(2)
0.0
ns
RD/WR↓ setup time to SEL↓
tSU(3)
0.0
ns
DTACK¦ delay after SEL↓
tD(1)
Note 1
tF
1.0
DTACK float time after SEL↑
Typ
Max for VDDIO of
Symbol
5V
3.3 V
Note 2
10
ns
13
ns
Notes:
1. Two cycles of clock PCLK.
2. The CUBIT-Pro will hold off the microprocessor for a period of up to 32 periods of the CellBus bus, LCLOCK or PCLK
clock selected by the settings of control bits CLKS1 and CLKS0 (bits 5 and 4 in register 0BH). This occurs only during
accesses to the external Translation RAM.
TXC-05802B-MB
Ed. 3, February 2001
- 70 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Microprocessor Interrupt Generation
Figure 51. Microprocessor Interrupt Timing
PCLK
(Input)
tD(1)
Intel Interface: INT
(Output)
Motorola Interface: IRQ
(Output)
Parameter
INT/IRQ delay after PCLK↑
Symbol
Min
tD(1)
0.0
- 71 of 90 -
Typ
Max for VDDIO of
5V
3.3 V
15
18
Unit
ns
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
MEMORY MAP
Address
Mode*
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
R
1
1
0
1
0
1
1
1
01
R
1
1
0
0
0
0
0
0
02
R
0
1
0
0
0
0
1
1
03
R
0
0
0
1
0
0
0
1
04
R
Mask Rev Mask Rev Mask Rev Mask Rev
(0)
(0)
(0)
(1)
05
RC
Reserved**
06
R/W
Reserved**
07
W
08
RC
CRCF
09
R/W
INTEN7
INTEN6
0A
R/W
P1
P0
0B
R/W
0C
R/W
0D
R/W
0E
R/W
0F
R/W
10
R/W
0/X
CBRLEN(6-0)
11
R/W
0/X
CBRLIMIT(6-0)
12
R/W
0/X
VBRLIMIT(6-0)
13
R/W
14
R/W
15
R/W
TRAL(7-0)
16
R/W
TRAU(7-0)
17
R/W
TRADATA(7-0)
Reserved**
BIP-8
CBLOF
CBLORC CBLOWC
INTENA3 INTENA2 INTENA1 INTENA0
Reserved**
CRQOVF CRQCAV
Reserved**
ONLINE
RESET
INSOC
CTSENT
NOGRT
Reserved**
OCOVF
INTEN5
INTEN4
INTEN3
INTEN2
Reserved**
INTEN0
UNI
TRHENA
CTRDY
CRQSENT
CLKS1
CLKS0
TRHIZ
Reserved**
LINEDIV(3-0)
Reserved**
QM
GFCENA
Reserved**
VRPS1
VRPS0
NOTIGN
CRC4I
IFECN
MRCIN
CRC4EN
Reserved** OAMRMEN
Reserved**
TIME(7-0)
LBADDRL(7-0)
Reserved**
LBADDRU(3-0)
* R = Read-Only; W = Write-Only; RC = Read and Clear (individual bits remain set to 1 if their causative condition persists); R/W = Read/Write.
** Note: Reserved addresses should not be accessed by the microprocessor. Reserved bit positions within used
addresses may contain random values; in writable addresses, these bits should be set to 0.
TXC-05802B-MB
Ed. 3, February 2001
- 72 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Address
Mode*
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
18
Reg
DISCCTR(7-0)
19
Reg
MRCCTR(7-0)
1A
Reg
HECERCTR(7-0)
1B
Reg
INCELLL(7-0) (Lower Byte)
1C
Reg
INCELLM(7-0) (Middle Byte)
1D
Reg
INCELLU(7-0) (Upper Byte)
1E
R
1F
Reg
Reserved**
20
R
MRCHEAD0(7-0)
21
R
MRCHEAD1(7-0)
22
R
MRCHEAD2(7-0)
23
R
MRCHEAD3(7-0)
24
R/W
25-5F
16BMODE 32USER
MASTER
Bit 1
Bit 0
CUBIT-ID(4-0)
Reserved**
TRAMSB(1-0)
Reserved**
60
R
CRQ0(7-0)
61-92
R
CRQ1(7-0) (61H) through CRQ50(7-0) (92H)
93
R
CRQ51(7-0)
94-9F
Reserved**
A0
R/W
CTQ0(7-0)
A1-D6
R/W
CTQ1(7-0) (A1H) through CTQ54(7-0) (D6H)
D7
R/W
CTQ55(7-0)
D8-DF
Reserved**
E0
R/W
MCASTN00(7-0)
E1-FE
R/W
MCASTN01(7-0) (E1H) through MCASTN1E(7-0) (FEH)
FF
R/W
MCASTN1F(7-0)
* R = Read-Only; R/W = Read/Write; Reg = Register.
** Note: Reserved addresses should not be accessed by the microprocessor. Reserved bit positions within used
addresses may contain random values; in writable addresses, these bits should be set to 0.
- 73 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
MEMORY MAP DESCRIPTIONS
DEVICE DESCRIPTOR AND RESET BITS
Address *
Bit
Symbol
00-02
03
7-0
3-0
DEVID
03
7-4
Version number.
04
7-4
Mask revision level.
07
Description
Device identification code (28 bits).
3-0
--
Reserved bits.
7-1
--
Reserved bits.
0
RESET
When set to 1, this bit clears the counters DISCCTR, MRCCTR,
HECERCTR and INCELL (L, M and U) in addresses 18H through
1DH. This bit clears to 0 automatically.
* All addresses in memory map description tables are hexadecimal. Reserved addresses are not listed.
STATUS AND INTERRUPT-ENABLE BITS
Address
Bit
Symbol
05
7-4
--
3
BIP-8
Bit is set to 1 when a BIP-8 error is detected in the receiver. It will generate a microprocessor interrupt if bit 3 (INTENA3) is set to one in the
interrupt enable location at address 06H.
2
CBLOF
Bit is set to 1 if the CellBus bus frame pulse is not present for two consecutive frame pulse times (U32 = low) or four consecutive frame
pulse times (U32 = high).
1
CBLORC
Bit is set to 1 if the CellBus bus read clock is not present for more than
the equivalent of 32 PCLK cycles.
0
CBLOWC
Bit is set to 1 if the CellBus bus write clock is not present for more than
the equivalent of 32 PCLK cycles.
7-4
--
3
INTENA3
Interrupt enabled for BIP-8, if = 1.
2
INTENA2
Interrupt enabled for CBLOF, if = 1.
1
INTENA1
Interrupt enabled for CBLORC, if = 1.
0
INTENA0
Interrupt enabled for CBLOWC, if = 1.
06
TXC-05802B-MB
Ed. 3, February 2001
Description
Reserved bits.
Reserved bits.
- 74 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Address
Bit
Symbol
Description
08
7
CRCF
Bit is set to 1 to indicate a CRC check error on cell from CellBus bus.
6
CRQOVF
Bit is set to 1 to indicate loss of an incoming control cell, due to overflow of the internal 4-cell control cell receive queue.
5
CRQCAV
Bit is set to 1 to indicate that a control cell is present in the control cell
receive queue, CRQ.
4
INSOC
3
CTSENT
Bit is set to 1 to indicate that a control cell has been sent to the CellBus
bus from the control cell transmit buffer.
2
NOGRT
Bit is set to 1 to indicate that no bus access grant has been received
by the inlet side, after a bus access request, within a time established
by register TIME.
1
--
0
OCOVF
Bit is set to 1 to indicate a cell discarded due to overflow of outlet
FIFO.
7
INTEN7
Interrupt enabled for CRCF, if = 1.
6
INTEN6
Interrupt enabled for CRQOVF, if = 1.
5
INTEN5
Interrupt enabled for CRQCAV, if = 1.
4
INTEN4
Interrupt enabled for INSOC, if = 1.
3
INTEN3
Interrupt enabled for CTSENT, if = 1.
2
INTEN2
Interrupt enabled for NOGRT, if = 1.
1
--
0
INTEN0
7
16BMODE
Bit is set to 1 if ABRENA is high. A 0 indicates that the CUBIT-Pro is
operated in 16-Bit mode.
6
32USER
Bit is set to 1 if U32 is high. A 0 indicates that the CUBIT-Pro is operated in 32-user mode.
5
MASTER
Bit is set to 1 if ENARB is high. A 0 indicates that the CUBIT-Pro is the
master arbiter of the CellBus bus.
4-0
CUBIT-ID
(4-0)
Contains the address ID set at pins UA(4-0). These pin states are
detected at power-up and if any of the UA(4-0) inputs change state.
For example, CUBIT-ID is 1FH if the UA(4-0) pins are all high.
09
1E
Bit is set to 1 to indicate a cell inlet Start-of-Cell error occurrence.
Reserved bit.
Reserved bit.
Interrupt enabled for OCOVF, if = 1.
- 75 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
DEVICE MODE CONTROL BITS
Address
Bit
Symbol
Description
0A
7, 6
P1, P0
Set bus access priority of this CUBIT-Pro device. Possible values are:
high-priority, P1=1, P0=1; medium-priority, P1=1, P0=0; low-priority, P1=0,
P0=1; no request, P1=0, P0=0.
5
UNI
If = 1, UNI operation, VPI filled width = 8 bits. If = 0, NNI operation, VPI
filled width = 12 bits.
4
TRHENA
Enable insertion of Tandem Routing Header during address translation.
3, 2
--
1
CTRDY
0
0B
Reserved bits.
Set to 1 by microprocessor to indicate that a control cell is ready to be
sent. Cleared by CUBIT-Pro when cell has been sent.
CRQSENT Set to 1 by the microprocessor to indicate that a control cell has been read
from the CUBIT-Pro’s control cell receive buffer. Cleared to 0 automatically
by CUBIT-Pro.
7,6
--
5
CLKS1
Reserved bits.
Clock source selection bit 1 for the cell inlet/outlet clock. This bit works in
conjunction with CLKS0. The coding followed is:
CLKS1, CLKS0 = 0,0: Cell interface clock = CellBus bus clock divided by 2LINEDIV
CLKS1, CLKS0 = 0,1: Cell interface clock = LCLOCK clock divided by 2LINEDIV
CLKS1, CLKS0 = 1,0: Cell interface clock = PCLK clock divided by 2LINEDIV
CLKS1, CLKS0 = 1,1: Reserved, do not use
0C
4
CLKS0
Clock source selection bit 0 for the cell inlet/outlet clock. This bit works in
conjunction with CLKS1.
3-0
LINEDIV
(3-0)
Cell inlet clock frequency control. Frequency will be equal to the frequency
of the selected clock source, divided by 2-to-the-power-LINEDIV.
7
ONLINE
Operational status. If = 1, the CUBIT-Pro is on-line and all functions are
operating. If = 0, the CUBIT-Pro is off-line. In off-line condition, no cells are
accepted from the cell inlet, the interface outputs are tristated, and only
control and loopback cells are accepted from the CellBus bus.
6
TRHIZ
Translation RAM interface tristate bit. When set to 1 and the ONLINE bit is
0, the translation RAM interface is put in Hi-Z mode.
5, 4, 3
--
2
QM
1
GFCENA
Enable insertion of the state of pins GFC(3-0) into the GFC field of outgoing cells if = 1. State of GFC(3-0) is sampled on the rising edge of COCLK
that precedes the first byte of the ATM cell header (see Figure 44).
0
IFECN
Enable insertion of FECN if = 1. The EFCI bit (middle bit of PT field) will be
set =1 if the CBR or VBR FIFO length equals or exceeds the congestion
limits, and IFECN = 1.
TXC-05802B-MB
Ed. 3, February 2001
Reserved bits.
Outlet cell queue structure. One single 123-cell queue if QM=0. Split
queue (Control Data, CBR, VBR, ABR) if QM = 1.
- 76 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Address
Bit
Symbol
0D
7-1
--
0
MRCIN
Bit is set to 1 to indicate that a misrouted cell has been received. Cleared
by a write operation.
7
VRPS1
VCI Records per Page Selection bit 1. In conjunction with VRPS0, this bit
selects the number of VCI records per page (VRP) to be either 256, 512,
1024 or 128.
VRPS1,VRPS0= 0,0: VRP is 256
VRPS1,VRPS0= 0,1: VRP is 512
VRPS1,VRPS0= 1,0: VRP is 1024
VRPS1,VRPS0= 1,1: VRP is 128
6
VRPS0
VCI Records per Page Selection bit 0. In conjunction with VRPS1, this bit
selects the number of VCI records per page (VRP) to be either 256, 512,
1024 or 128.
5
NOTIGN
Ignore translation record I-bit. When set to 1, connections marked as
I-bit=1 in the translation records will be treated as if I-bit=0.
4
CRC4I
CRC-4 calculation is inverted to produce an incorrect CRC-4 value for the
CellBus Bus Routing Header. This bit is intended for test purposes.
3
CRC4EN
When set to 1, this bit enables CUBIT-Pro to compute the CRC-4 field
H3-H0 in the CellBus Bus Routing Header for all cells going into the cell
inlet FIFO. If set to 0, then CRC-4 is computed only for loopback cells. The
default at power-up is CRC4EN=0.
2
--
0E
1
0F
Description
Reserved bits.
Reserved bit.
OAMRMEN When set to 1, this bit enables the routing of OAM/RM and reserved VCs
cells. If set to 0, the CUBIT-Pro TXC-05802B uses CUBIT TXC-05801
OAM routing. The default at power-up is OAMRMEN=0.
0
--
7-0
TIME
Reserved bit.
Time-out counter preset value for bus access watchdog timer. If timer
expires after a request is made, and before a grant is received, alarm bit
NOGRT is set. Each count represents one bus frame cycle.
OUTLET CELL FIFO SIZE AND LIMIT CONTROL REGISTERS
Address
Bit
Symbol
Description
10
6-0
CBRLEN
Length, in cells, of the CBR section of the cell outlet FIFO. Valid values are zero through 89.
11
6-0
CBRLIMIT
Congestion size for CBR FIFO. FECN may be set if CBR FIFO length
is greater than or equal to this value and IFECN = 1.
12
6-0
VBRLIMIT
Congestion size for VBR FIFO. FECN may be set if VBR FIFO length
is greater than or equal to this value and IFECN = 1.
- 77 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
LOOPBACK CONTROL ADDRESS REGISTER
Address
Bit
Symbol
Description
13
7-0
LBADDRL
8 LSB of Loopback Routing Header, bits 11-4 of CellBus Bus Routing
Header (see Figure 30).
14
7-4
--
3-0
LBADDRU
Reserved bits.
4 MSB of Loopback Routing Header, bits 15-12 of CellBus Bus Routing Header (see Figure 30).
TRANSLATION RAM READ/WRITE CONTROL
Address
Bit
Symbol
Description
15
7-0
TRAL
8 LSB of the translation RAM address [pins TRA(7-0)].
16
7-0
TRAU
Middle 8 bits of the translation RAM address [pins TRA(15-8)].
17
7-0
TRADATA
Data read from, or to be written into, the translation RAM at the
address defined by pins TRA(17-0) [pins TRD(7-0)].
24
7-2
--
1-0
TRAMSB
Reserved bits.
2 MSB of the translation RAM address [pins TRA(17-16)]
COUNTERS AND MISROUTED CELL HEADERS
Address
Bit
Symbol
Description
18
7-0
DISCCTR
Count of cells discarded at input to outlet-side FIFO. See Note 1.
19
7-0
MRCCTR
Count of cell inlet mis-routed cells received. See Note 1.
1A
7-0
1B
7-0
INCELLL
Bits 7-0 (8 LSB) of count of incoming cells. See Note 1.
1C
7-0
INCELLM
Bits 15-8 of count of incoming cells. See Note 1.
1D
7-0
INCELLU
Bits 23-16 (8 MSB) of count of incoming cells. See Note 1.
20
7-0
MRCHEAD0 First (least significant) byte of the header of the first misrouted cell
received after this buffer was last cleared. This least significant byte of
the ATM cell corresponds to VCI[3-0] (LSB), PT and CLP of the ATM
cell header.
21
7-0
MRCHEAD1 Second byte of above header.
22
7-0
MRCHEAD2 Third byte of above header.
23
7-0
MRCHEAD3 Fourth (most significant) byte of above header.
HECERCTR Count of cells at cell inlet having a HEC error indication. See Note 1.
Note 1: These registers are reset to 00H by the RESET bit in address 07H, bit 0.
TXC-05802B-MB
Ed. 3, February 2001
- 78 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
CONTROL CELL SEND AND RECEIVE QUEUES
Address
Bit
Symbol
Description
60-93
7-0
CRQi
Control cell receive buffer, 52 bytes (i = 0 - 51).
A0-D7
7-0
CTQi
Control cell transmit buffer, 56 bytes (i = 0 - 55).
MULTICAST NUMBER MEMORY
Address
Bit
Symbol
Description
E0
7-0
MCASTN00 Multicast session RX enable bits, channels 7-0 (relative address zero
decimal, bits 7-0).
E1-FE
7-0
MCASTN01- Multicast session RX enable bits for channels 15-8, 23-16, . . . ,
MCASTN1E 247-240 (relative addresses 1 to 30 decimal, bits 7-0).
FF
7-0
MCASTN1F Multicast session RX enable bits, channels 255-248 (relative address
31 decimal, bits 7-0).
- 79 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
PACKAGE INFORMATION
The CUBIT-Pro device is available in a 208-pin plastic quad flat package (PQFP) suitable for surface mounting, as shown in Figure 52.
156
105
104
157
See Details “B” and “C”
0.50 (TYP)
TRANSWITCH
Detail “B”
TXC-05802BIPQ
0.28 MAX (TYP)
0.17 MIN (TYP)
Detail “C”
PIN #1
INDEX
208
53
1
52
25.50 REF (SQ)
28.00 ± 0.10 (SQ)
4.20 MAX
3.67 MAX
3.17 MIN
30.60 ± 0.25 (SQ)
SEE DETAIL “A”
Notes:
1. All linear dimensions are shown in millimeters and are
nominal unless otherwise indicated.
2. Coplanarity of 0.08 millimeters maximum is the difference
between the highest lead and the seating plane.
0.60 ± 0.20
0.25 MIN
(Note 2)
DETAIL “A”
Figure 52. CUBIT-Pro TXC-05802B 208-Pin Plastic Quad Flat Package
TXC-05802B-MB
Ed. 3, February 2001
- 80 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
CUBIT-Pro
TXC-05802B
ORDERING INFORMATION
Part Number:
TXC-05802BIPQ
208-pin Plastic Quad Flat Package (PQFP)
RELATED PRODUCTS
Figure 53 illustrates typical applications of the CUBIT-Pro CellBus Bus Switch device in a generic architecture
for ATM access switching. The other TranSwitch devices included in this diagram are briefly described below:
TXC-03003B, SOT-3 VLSI Device (STM-1, STS-3, STS-3c Overhead Terminator). This device performs
all the functions for section, line and path overhead processing of STM-1, STS-3 or STS-3c signals, providing access to all overhead bytes. It performs pointer justification and payload tracking, alarm detection
and generation, and performance monitoring.
TXC-03103, QT1F-Plus VLSI Device (Quad T1 Framer-Plus). A 4-channel DS1 (1.544 Mbit/s) framer
designed with extended features for voice and data communications applications.
TXC-05150, CDB VLSI Device (Cell Delineation Block). Extracts/inserts ATM cells from/to DS1, DS3, E1,
STS-1, STS-3c or STM-1 line interface signals. Serial, byte and nibble interfaces operate from 1.544 to
155.52 Mbit/s.
TXC-05501B and TXC-05601B, SARA-S and SARA-R VLSI Devices (Segmentation and Reassembly).
A two-chip set for implementation of the ATM Adaptation Layers (AAL) 3, 4, and 5 at line rates from DS1
(1.544 Mbit/s) up to STS-3c/STM-1 (155.52 Mbit/s).
TXC-05801, CUBIT Device (ATM CellBus Bus Switch). Implements cost effective ATM multiplexing and
switching systems, based on the 32-bit CellBus bus architecture. A single-chip solution, the CUBIT has the
ability to send and also receive cells for control purposes over the same CellBus bus. CellBus bus technology works at aggregate rates of up to 1 gigabit per second and provides header translation, multiplexing,
concentration and switching functions for a wide variety of small-to-medium size ATM systems. This
device is not recommended for use in new designs, which should use CUBIT-Pro, TXC-05802B.
TXC-05804, CUBIT-3 VLSI Device (Multi-PHY CellBus Switch Access Device). A single-chip solution for
implementing low-cost ATM multiplexing and switching systems, based on the CellBus architecture. Such
systems are constructed from a number of CUBIT-3 devices, all interconnected by a 37-line common bus,
the CellBus. CUBIT-3 supports unicast, broadcast and spatial multicast transfers, and has all necessary
functions for implementing a switch: cell address translation, cell routing and outlet cell queuing. This
device interfaces with CUBIT-Pro devices.
TXC-05810, ASPEN VLSI Device (CellBus Access Processor). A revolutionary, RISC-based processor
designed to support the requirements of next generation multi-service access systems. ASPEN supports
CellBus bus operation in both cell and packet modes via two independent CellBus bus ports.
TXC-07625, SALI-25C VLSI Device (Six ATM Line Interface at 25 Mbit/s). Six channel 25.6 Mbit/s ATM
transmission convergence function for twisted pair cable. Supports UTOPIA Level 1 and 2. Provides multicasting capability and 4 level priority queuing.
- 81 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
Figure 53. CUBIT-Pro TXC-05802B and Related Product Applications in ATM Access Switching
ATM Cell
Interface
SONET
Ring
SOT-3
SOT-3
CDB
SOT-3
CUBIT-Pro
SOT-3
SONET
Cell Link
SOT-3
SOT-3
CDB
SOT-3
CUBIT-Pro
SOT-3
T1
Cell Link
QT1F-Plus
SOT-3
CDB
SOT-3
CUBIT-Pro
SOT-3
Data
Packets
SARA-S/R
SOT-3
xDSL
Line
6
Physical
ATM
25 Mbps
Line Interface
TXC-05802B-MB
Ed. 3, February 2001
CUBIT-Pro
SOT-3
CDB
SOT-3
CUBIT-Pro
SOT-3
SALI-25C
SOT-3
CUBIT-Pro
SOT-3
PROC
SOT-3
CUBIT-Pro
Medium
SOT-3
Interface
- 82 of 90 -
CellBus bus:
37 lines on
backplane
or card
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
STANDARDS DOCUMENTATION SOURCES
Telecommunication technical standards and reference documentation may be obtained from the following
organizations:
ANSI (U.S.A.):
American National Standards Institute
11 West 42nd Street
New York, New York 10036
Tel: (212) 642-4900
Fax: (212) 302-1286
Web: www.ansi.org
The ATM Forum (U.S.A., Europe, Asia):
2570 West El Camino Real
Suite 304
Mountain View, CA 94040
Tel: (650) 949-6700
Fax: (650) 949-6705
Web: www.atmforum.com
ATM Forum Europe Office
Av. De Tervueren 402
1150 Brussels
Belgium
Tel: 2 761 66 77
Fax: 2 761 66 79
ATM Forum Asia-Pacific Office
Hamamatsu-cho Suzuki Building 3F
1-2-11, Hamamatsu-cho, Minato-ku
Tokyo 105-0013, Japan
Tel: 3 3438 3694
Fax: 3 3438 3698
Bellcore (See Telcordia)
CCITT (See ITU-T)
EIA (U.S.A.):
Electronic Industries Association
Global Engineering Documents
7730 Carondelet Avenue, Suite 407
Clayton, MO 63105-3329
Tel: (800) 854-7179 (within U.S.A.)
Tel: (314) 726-0444 (outside U.S.A.)
Fax: (314) 726-6418
Web: www.global.ihs.com
ETSI (Europe):
European Telecommunications Standards Institute
650 route des Lucioles
06921 Sophia Antipolis Cedex
France
- 83 of 90 -
Tel: 4 92 94 42 22
Fax: 4 92 94 43 33
Web: www.etsi.org
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
GO-MVIP (U.S.A.):
The Global Organization for Multi-Vendor Integration
Protocol (GO-MVIP)
3220 N Street NW, Suite 360
Washington, DC 20007
Tel: (800) 669-6857 (within U.S.A.)
Tel: (903) 769-3717 (outside U.S.A.)
Fax: (508) 650-1375
Web: www.mvip.org
ITU-T (International):
Publication Services of International Telecommunication Tel: 22 730 5111
Union
Telecommunication Standardization Sector
Fax: 22 733 7256
Place des Nations, CH 1211
Web: www.itu.int
Geneve 20, Switzerland
MIL-STD (U.S.A.):
DODSSP Standardization Documents Ordering Desk
Building 4 / Section D
700 Robbins Avenue
Philadelphia, PA 19111-5094
Tel: (215) 697-2179
Fax: (215) 697-1462
Web: www.dodssp.daps.mil
PCI SIG (U.S.A.):
PCI Special Interest Group
2575 NE Kathryn Street #17
Hillsboro, OR 97124
Tel: (800) 433-5177 (within U.S.A.)
Tel: (503) 693-6232 (outside U.S.A.)
Fax: (503) 693-8344
Web: www.pcisig.com
Telcordia (U.S.A.):
Telcordia Technologies, Inc.
Attention - Customer Service
8 Corporate Place
Piscataway, NJ 08854
Tel: (800) 521-CORE (within U.S.A.)
Tel: (908) 699-5800 (outside U.S.A.)
Fax: (908) 336-2559
Web: www.telcordia.com
TTC (Japan):
TTC Standard Publishing Group of the
Telecommunications Technology Committee
2nd Floor, Hamamatsu-cho Suzuki Building,
1 2-11, Hamamatsu-cho, Minato-ku, Tokyo
TXC-05802B-MB
Ed. 3, February 2001
- 84 of 90 -
Tel: 3 3432 1551
Fax: 3 3432 1553
Web: www.ttc.or.jp
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
CUBIT-Pro
TXC-05802B
LIST OF DATA SHEET CHANGES
This list of changes identifies areas within this updated CUBIT-Pro TXC-05802B Data Sheet that have significant differences relative to the previous, and now superseded, CUBIT-Pro TXC-05802B Data Sheet:
Updated CUBIT-Pro TXC-05802B Data Sheet:
Edition 3, February 2001
Previous CUBIT-Pro TXC-05802B Data Sheet:
Edition 2, November 1999
Most of these changes are related to the addition of the option for single-supply +3.3 volt operation.
The page numbers indicated below of this updated Data Sheet include changes relative to the previous Data
Sheet.
Page Number of
Updated Data Sheet
Summary of the Change
All
Added TranSwitch document proprietary markings. Changed edition number
and date.
All
Changed the pin symbol ‘VDD5’ to ‘VDDIO’ throughout document.
1
Modified the next to last bullet item of Features list. Added last sentence in
second paragraph under Description section.
2-4
Updated Table of Contents and List of Figures.
26
Added second sentence to first paragraph under leading ‘OAM/RM Routing
Mode Bits (C1, C0)’.
34
Modified the Note on bottom of page.
39
Added last two sentences in Note 5.
41
Modified Name/Function column for Symbols VDDIO and VDDBOOT.
46
Added ‘See Note 1’ in Name/Function column for Symbol RESET. Added
Note 1 at the bottom of page.
47
Added Note 4. Modified Conditions column for Symbol ESD and replaced ‘±’
with ‘absolute value’ for Min and Max column as well as beginning of
sentence in Note 3. Made extensive changes to ‘Power Requirements’ table
for the Single-supply option.
48
Made extensive changes to Test Conditions column for first, second and third
tables.
49
Made extensive changes to Test Conditions column for first and last tables.
50
Made extensive changes to Test Conditions column for all three tables.
52-63
Changed table cell heading ‘Max’ to ‘Max for VDDIO of’ and added new
columns for ‘Max for VDDIO of’ value 3.3 V for tables in Figures 32-43.
67-71
Changed table cell heading ‘Max’ to ‘Max for VDDIO of’ and added new
columns for ‘Max for VDDIO of’ value 3.3 V for tables in Figures 47-51.
81
Updated ‘Related Products’ section to include CUBIT-3, TXC-05804 and
ASPEN, TXC-05810 devices.
82
Deleted SARA-Lite from Figure 53.
- 85 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
Page Number of
Updated Data Sheet
83
85-86
89
TXC-05802B-MB
Ed. 3, February 2001
DATA SHEET
Summary of the Change
Updated ‘Standard Documentation Sources’ section.
Replaced ‘List of Data Sheet Changes’ section.
Updated ‘Documentation Update Registration Form’ section.
- 86 of 90 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
CUBIT-Pro
TXC-05802B
- NOTES -
TranSwitch reserves the right to make changes to the product(s) or
circuit(s) described herein without notice. No liability is assumed as a
result of their use or application. TranSwitch assumes no liability for
TranSwitch applications assistance, customer product design, software performance, or infringement of patents or services described
herein. Nor does TranSwitch warrant or represent that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TranSwitch covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
- 87 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
TranSwitch Corporation
•
3 Enterprise Drive
•
Shelton, CT 06484 USA
•
Tel: 203-929-8810
•
Fax: 203-926-9453
•
www.transwitch.com
Proprietary TranSwitch Corporation Information for use Solely by its Customers
CUBIT-Pro
TXC-05802B
DATA SHEET
DOCUMENTATION UPDATE REGISTRATION FORM
If you would like to receive updated documentation for selected devices as it becomes available, please provide
the information requested below (print clearly or type) then tear out this page, fold and mail it to the Marketing
Communications Department at TranSwitch. Marketing Communications will ensure that the relevant Product
Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you.
You may also choose to provide the same information by fax (203.926.9453), or by e-mail ([email protected]), or
by telephone (203.929.8810). Most of these documents will also be made immediately available for direct
download as Adobe PDF files from the TranSwitch World Wide Web Site (www.transwitch.com).
Name: _________________________________________________________________________________
Company: __________________________________________ Title: ______________________________
Dept./Mailstop: __________________________________________________________________________
Street: _________________________________________________________________________________
City/State/Zip: ___________________________________________________________________________
If located outside U.S.A., please add - Country: ________________
Postal Code: ____________________
Telephone: _______________________
Fax: __________________________
Ext.: ____________
E-mail: _______________________________________________
Please provide the following details for the managers in charge of the following departments at your company
location.
Department
Title
Name
Company/Division
__________________
__________________
Engineering
__________________
__________________
Marketing
__________________
__________________
Please describe briefly your intended application(s) and indicate whether you would like to have a TranSwitch
applications engineer contact you to provide further assistance:
_____________________________________________________________________________________________
_____________________________________________________________________________________________
_____________________________________________________________________________________________
_____________________________________________________________________________________________
If you are also interested in receiving updated documentation for other TranSwitch device types, please list them below
rather than submitting separate registration forms:
__________
__________
__________
__________
__________
__________
__________
__________
__________
__________
__________
__________
__________
__________
Please fold, tape and mail this page (see other side) or fax it to Marketing Communications at 203.926.9453.
- 89 of 90 -
TXC-05802B-MB
Ed. 3, February 2001
(Fold back on this line second, then tape closed, stamp and mail.)
First
Class
Postage
Required
3 Enterprise Drive
Shelton, CT 06484-4694
TranSwitch Corporation
Attention: Marketing Communications Dept.
3 Enterprise Drive
(Fold back on this line first.)
Please complete the registration form on this back cover sheet, and mail or fax it, if you wish to
receive updated documentation on selected TranSwitch products as it becomes available.
TranSwitch Corporation
•
3 Enterprise Drive
•
Shelton, CT 06484 USA
•
Tel: 203-929-8810
•
Fax: 203-926-9453
•
www.transwitch.com