MRT Two Terminal Side interfaces are provided, a positive and negative rail (RP and RN) or NRZ (RD) interface. The selection is determined by the state placed on the signal lead labeled PNENB. When a low is applied to the signal lead, the HDB3 Decoder and HDB3 Encoder Blocks are bypassed, and the terminal side I/O is a positive and negative rail interface. When a high is applied to the signal lead, an NRZ interface is provided. Data is clocked out of the MRT on negative edges of the clock signal (CLKO). Receive data and the clock signals are disabled, and forced to a high impedance state by placing a low on the receive disable lead (RXDIS). For a receive positive and negative rail interface, an inverted clock (CLKO) is also provided. The terminal side interface for the transmitter can either be positive and negative rail (TP and TN) or NRZ (TD) data depending on the state of the common control lead PNENB. Data is clocked into the MRT on positive transitions of the clock signal (CLKI). The input clock is monitored for the loss of clock. When the input clock remains high or low, TXLOC will be set low. The MRT also provides the capability to generate and insert AIS (all ones signal), independent of the transmit data. A low placed on the TXAIS lead enables the transmit AIS generator. Two loopbacks are provided, transmit loopback and receive loopback. Transmit loopback connects the data path from the transmitter output driver stage to the clock recovery, and disables the external receiver input. Transmit loopback is activated by placing a low on the LBKTX signal lead. Receive loopback connects the receive data path to the transmit output circuits and disables the transmit input. Receive loopback is activated by placing a low on the LBKRX signal lead. For 6 Mbps operation, the MRT should be operated in the P and N rail mode, bypassing the HDB3 Decoder/ Encoder. TP/TD 40 TN VDD TXAIS 42 44 GND 8 38 CLKI 10 36 VCOC PNENB GND GND TXLOC 2 RXAIS BERCK 4 GND 6 LQLTY PIN DIAGRAM VDD DCK VDD RN MRT PIN DIAGRAM (Top View) 12 RP/RD CLKO 34 32 14 GND GNDA 30 DI2 28 DI1 EQB0 EQB1 26 LOW LBKTX 24 LBKRX VAGC 22 AGFIL 20 RXDIS RXLOS CV 18 16 VDD PLLC TPO TNO CLKO GND GND VDD GND Figure 2. MRT Pin Diagram With Names and Numbers -3- TXC-02050-MB Ed. 3, April 1994 MRT PIN DESCRIPTIONS Power Supply and Ground Symbol Pin No. I/O/P* Type Name/Function VDD 10,18,35, 37,42 P VDD: 5-volt supply, ± 5%. GND 1,6,11,16,32, 36,39,44 P Ground: 0 volts reference. VAGC 23 P AGC VDD: Isolate from VDD using 1N914 or 1N4148 diode. GNDA 31 P AGC Ground: 0 volts reference. *Note: I = Input; O = Output; P = Power Line Side I/O Symbol Pin No. I/O/P Type Name/Function DI1 29 I Analog Data In 1: HDB3 or B8ZS encoded bipolar receive data input. DI2 30 O Analog Data In 2: DC Voltage Reference for Data Input DI1. The MRT uses an internally generated voltage reference as an AC ground for the received data input. An external 0.1 µF capacitor, in parallel with a 10 µF/6.3 V tantalum capacitor, is connected between this pin and ground. No other connection should be made to this pin. TNO 33 O TTL24mA Transmit Negative Out: Line transmit negative; output is an active low. TPO 34 O TTL24mA Transmit Positive Out: Line transmit positive; output is an active low. Symbol Pin No. I/O/P Type Name/Function RN 12 O TTL4mA Receive Negative: When PNENB is low, the HDB3 codec is bypassed and N-rail (RN) data is provided on this pin. When PNENB is high, the output is forced to a high impedance state. RP/RD 13 O TTL4mA Receive Positive/Receive Data: When PNENB is low, the HDB3 codec is bypassed and P-Rail (RP) data is provided on this pin. When PNENB is high, NRZ data (RD) is provided. CLKO 14 O CMOS8mA Terminal Side I/O Clock Out Inverted: Receive inverted clock output. Positive and negative rail receive data is clocked out on the rising edge. Disabled in the NRZ mode. -4- TXC-02050-MB Ed. 3, April 1994 MRT Symbol Pin No. I/O/P Type Name/Function CLKO 15 O CMOS8mA Clock Out: Receive clock output. Receive positive and negative rail and NRZ data is clocked out on the falling edge. CLKI 38 I TTLr Clock In: Transmit clock input for P and N rail and NRZ data. Transmit data is clocked into the MRT on the rising edge. This clock must have a frequency of ± 20 ppm for the 34368 kbit/s operation and ± 30 ppm for the 6312/8448 kbit/s operation (ref: CCITT recommendation G.703). The duty cycle requirement for this clock signal is 50% ± 5%, measured at the 1.4V TTL threshold level. TP/TD 40 I TTL Transmit Positive/Transmit Data: When PNENB is low, the HDB3 codec is bypassed and transmit P-rail (TP) data is applied to this pin. When PNENB is high, NRZ transmit data (TD) is applied. TN 41 I TTL Transmit Negative: When PNENB is low, the HDB3 codec is bypassed and transmit N-Rail (TN) is applied to this pin. When PNENB is high, this input is disabled. Alarm Signal Outputs Symbol Pin No. I/O/P Type Name/Function TXLOC 2 O TTL2mA Transmit Loss Of Clock: Active low output. A transmit loss of clock alarm occurs when the transmit clock input (CKLI) is stuck high or low for 20-32 clock cycles. Recovery occurs on the first input clock transition. LQLTY 5 O TTL2mA Line Quality: This signal represents a gross estimate of the line quality which is determined by counting coding violations for 34 (8) Mbit/s operation. If the line error rate exceeds a 10-6 threshold during a 10 (40) second interval, LQLTY goes active high. LQLTY is active low when coding violations do not exceed the 10-6 threshold in a 10 (40) second interval. The output on this pin is only valid when the appropriate clock signal is applied to BERCK. It should be disregarded in the P and N mode of operation. CV 19 O TTL2mA Coding Violation: Active high output. A coding violation pulse occurs when an HDB3 coding violation is detected in the received line data input. A coding violation is not part of the HDB3 zero-substitution code. A coding violation occurs because of noise or other impairments affecting the line signal. The output of this pin should be disregarded in the P and N mode. RXLOS 20 O TTL2mA Receive Loss Of Signal: Active low output. A receive loss of signal occurs when the input data is zero for 20-32 clock cycles. Recovery occurs when the receive signal returns. -5- TXC-02050-MB Ed. 3, April 1994 MRT MRT Control Leads Symbol Pin No. I/O/P Type Name/Function RXAIS 3 I CMOSr Receive Alarm Indication Signal: When RXAIS is low, the MRT generates AIS (all ones signal) for the terminal side receive output data. The line side receive data path is disabled. The reference clock (DCK) provides the clock source required for generating AIS. BERCK 4 I TTLr Bit Error Rate Clock: This clock establishes the time base for estimating the coding violation error rate. For 34 Mbit/s operation the clock frequency must be 6 kHz, and for 8 Mbit/s operation the clock frequency must be 1.5 kHz. This pin should be left open for P and N mode operation. PNENB 8 I CMOSr P And N Enable: When PNENB is low, the P and N rail interface is enabled, and the HDB3 codec is bypassed. When PNENB is high, the terminal side I/O data is NRZ and the HDB3 codec is enabled. This pin must be held low for 6 Mbit/s operation. DCK 9 I TTL Reference Clock: Operating frequency reference clock. For receive signal clock recovery, ± 200 ppm frequency accuracy is adequate. If the transmit and receive AIS features are used, the frequency accuracy must be ± 20 ppm for 34368 kbit/s and ± 30 ppm for 8448 and 6312 kbit/s operation. The duty cycle requirement for this clock signal is 50% ± 5% as measured at the 1.4V TTL threshold level. RXDIS 21 I CMOSr Receive Disable: When RXDIS is low, the receive side of the MRT is disabled and the RN, RP/RD, CLKO and CLKO output leads are forced to a high impedance state. LBKRX 24 I CMOSr Loopback Receive: When LBKRX is low, the MRT loops back receive data as transmit data. The receive data is also sent to the terminal side, but the transmit data input on the terminal side is disabled. (Note 1) LBKTX 25 I CMOSr Loopback Transmit: When LBKTX is low, the MRT loops back transmit data as receive data. The transmit data is sent on the line side, but the receive data input on the line side is disabled. (Note 1) LOW 26 I CMOSr Low Frequency: When LOW is low, the MRT enables equalization and input attenuator settings for 6312 or 8448 kbit/s operation. This lead also controls the clock recovery high/low frequency range circuit. Note 1: Setting LBKTX and LBKRX low simultaneously will cause invalid outputs at the receive terminal and transmit line ports. -6- TXC-02050-MB Ed. 3, April 1994 MRT Symbol Pin No. I/O/P Type Name/Function EQB1 EQB0 27 28 I I CMOSr Equalizer Bit 1: MSB of equalizer setting. Equalizer Bit 0: LSB of equalizer setting. Equalization is as follows for 34 Mbit/s operation: EQB1 EQB0 CABLE EQUALIZATION √f * 1 1 0dB< cable <3.5dB 1 0 2.6dB<cable<8dB 0 0 6dB<cable<9.9dB 0 1 8.6dB<cable<13.2dB For 8 or 6 Mbit/s operation: 1 1 0dB< cable< 4.1dB 1 0 2.5dB<cable<6.5dB * f = 1/2 the bit rate TXAIS 43 I CMOSr Transmit AIS: When TXAIS is low, the MRT sends an AIS (all ones signal) for the line side transmit output data. The terminal side transmit data path is disabled. The reference clock (DCK) provides the clock required for generating AIS. Pins With External Components Symbol Pin No. I/O/P Type Name/Function VCOC 7 I/O Analog Voltage Controlled Oscillator Capacitor: For 6, 8, and 34 Mbit/s operation, a 470Ω ± 5%, 1/8 watt resistor is connected in series with a 0.1 µF ± 10% capacitor to ground. These components are used in the phase-locked loop filter. PLLC 17 I/O Analog Phase-Locked Loop Capacitor: 0.1 µF ± 10% ceramic disk capacitor connected to ground. AGFIL 22 I/O Analog Automatic Gain Filter: For 6/8 MHz mode, 0.01 µF ± 10% ceramic disk capacitor connected to ground. For 34 Mbit/s mode, open. -7- TXC-02050-MB Ed. 3, April 1994 MRT ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Min Max Unit Supply voltage VDD -0.3 7.0 V AGC Supply Voltage VAGC -0.5 6.5 V DC input voltage VIN -0.5 VDD + 0.5 V Continuous power dissipation PC 750 mW Ambient operating temperature TA 85 oC Operating junction temperature TJ 150 oC Storage temperature range TS 150 oC -40 -55 *Note: Operating conditions exceeding those listed in Absolute Maximum Ratings may cause permanent failure. Exposure to absolute maximum ratings for extended periods may impair device reliability. THERMAL CHARACTERISTICS Parameter Min Typ Thermal Resistance: Junction to Ambient Max Unit 46 oC/W Test Conditions POWER REQUIREMENTS Parameter Min Typ Max Unit VDD 4.75 5.0 5.25 V VAGC VDD - 0.7 VDD - 0.5 V IDD 100 mA VDD = 5.25V IAGC 20 mA VAGC = 4.75V PDD 525 mW VDD = 5.25V PAGC 95 mW VAGC = 4.75V -8- Test Conditions Isolated from VDD via a IN4148 or 1N914 diode. TXC-02050-MB Ed. 3, April 1994 MRT INPUT, OUTPUT, AND I/O PARAMETERS Input Parameters For TTL Parameter Min VIH Typ Max 2.0 Unit Test Conditions V 4.75 <VDD < 5.25 VIL 0.8 V 4.75 <VDD < 5.25 Input leakage current 10 µA VDD = 5.25 Input capacitance 5.5 pF Input Parameters For TTLr Parameter Min Typ Max 2.0 VIH VIL Input leakage current 50 Input capacitance 5.5 Unit Test Conditions V 4.75 <VDD < 5.25 0.8 V 4.75 <VDD < 5.25 120 µA VDD = 5.25 pF Note: Input has a 100K (nominal) internal pull-up resistor. Input Parameters For CMOSr Parameter VIH Min Typ Max 2.0 VIL Input leakage current 50 Input capacitance 5.5 Unit Test Conditions V 4.75 <VDD < 5.25 0.8 V 4.75 <VDD < 5.25 120 µA VDD = 5.25 pF Note: Input has a 100K (nominal) internal pull-up resistor. Output Parameters For TTL2mA Parameter VOH Min Typ Max VDD - 0.5 Unit Test Conditions V VDD = 4.75; IOH = -1.0 mA VDD = 4.75; IOL = 2.0 mA VOL 0.4 V IOL 2.0 mA IOH -1.0 mA tRISE 5.5 12.5 18.2 ns CLOAD = 15pF tFALL 2.3 4.4 6.5 ns CLOAD = 15pF -9- TXC-02050-MB Ed. 3, April 1994 MRT Output Parameters For TTL4mA Parameter VOH Min Typ Max VDD - 0.5 Unit Test Conditions V VDD = 4.75; IOH = -2.0 mA VDD = 4.75; IOL = 4.0 mA VOL 0.4 V IOL 4.0 mA IOH -2.0 mA tRISE 2.8 6.5 9.2 ns CLOAD = 15 pF tFALL 1.3 2.3 3.4 ns CLOAD = 15 pF Typ Max Unit Output Parameters For TTL24mA Parameter Min VDD - 0.5 VOH Test Conditions V VDD = 4.75; IOH = -12.0 mA VDD = 4.75; IOL = 24.0 mA VOL 0.4 V IOL 24.0 mA IOH -12.0 mA tRISE 0.8 1.4 1.8 ns CLOAD = 25 pF tFALL 0.5 0.8 1.0 ns CLOAD = 25 pF Typ Max Unit Output Parameters For CMOS8mA Parameter VOH Min VDD - 0.5 Test Conditions V VDD = 4.75; IOH = -8.0 mA VDD = 4.75; IOL = 8.0 mA VOL 0.4 V IOL 8.0 mA IOH -8.0 mA tRISE 1.3 2.4 3.8 ns CLOAD = 25 pF tFALL 1.1 1.8 2.5 ns CLOAD = 25 pF - 10 - TXC-02050-MB Ed. 3, April 1994 MRT TIMING CHARACTERISTICS Detailed timing diagrams for the MRT are illustrated in Figures 3 through 9. All output times are measured with maximum load capacitance appropriate for the pin type. Timing parameters are measured at (VOH - VOL)/2 or (VIH - VIL)/2 as applicable. Line Side Timing Characteristics The line side timing characteristics of the MRT are designed so that the line output mask at the transformer output meets the wave shapes specified in CCITT recommendation G.703 for 34 and 8 Mbit/s operation and the NTT Technical Reference for High Speed Digital Leased Circuit Service for 6 Mbit/s operation. The pulse masks for each of the three modes of operation are shown in Figures 3, 4, and 5. Refer to the corresponding standard cited in each case for further details regarding the interface. Figure 3. Pulse Mask at the 34368 kbit/s Interface 17 ns (14.55 + 2.45) 0.1 0.2 V 1.0 0.2 0.1 8.65 ns (14.55 - 5.90) Nominal pulse 14.55 ns 0.5 12.1 ns (14.55 - 2.45) 0.1 0.1 0 0.1 0.1 24.5 ns (14.55 + 9.95) 29.1 ns (14.55 + 14.55) Reference: CCITT Recommendation G.703 - 11 - TXC-02050-MB Ed. 3, April 1994 MRT Figure 4. Pulse Mask at the 8448 kbit/s Interface 69 ns (59 + 10) 0.474 0.237 V 35 ns 0.474 0.237 2.370 (59 - 24) Nominal pulse 59 ns 1.185 49 ns (59 - 10) 0.237 0.237 0.237 0.237 0 100 ns (59 + 41) 118 ns (59 + 59) Reference: CCITT Recommendation G.703 Figure 5. Pulse Mask at the 6312 kbit/s Interface Horizontal axis 20 ns/div Vertical axis 1 V/div Pulse amplitude B A (0,2) F Nominal pulse shape G (0,1) H I Coordinates of each point A : ( 0, 2.3) F : ( 0, 1.7) B : (2.4, 2.3) G : (0.4, 1.7) C : (2.4, 1.0) H : (1.6, 0.9) D : (3.2, 0.3) I : (1.6, 0.3) E : (4.0, 0.3) (0,0) C D E (4,0) Time Reference: NTT Technical Reference for High-Speed Digital Leased Circuit Services - 12 - TXC-02050-MB Ed. 3, April 1994 MRT Terminal Side Timing Characteristics Figure 6. NRZ Transmit Input tPWH tCYC CLKI 1.4V tSU TP,TD DATA VALID tH DATA VALID Parameter Symbol CLKI clock period DATA VALID Min tCYC Typ Max Unit Note 2 ns CLKI duty cycle (tPWH/tCYC) -- 45 55 % TP,TD set-up time to CLKI↑ tSU 3 ns TP,TD hold time after CLKI↑ tH 2 ns Note 1: CLKI symmetry is measured about the 1.4VDC threshold in order to assure symmetric output waveforms. Note 2: The clock input can be 6, 8, or 34 MHz (refer to page 5). Figure 7. NRZ Receive Output tPWH tCYC CLKO tOD(1) RP,RD tOD(2) CV Parameter CLKO clock period CLKO duty cycle (tPWH/tCYC) Symbol Min tCYC Typ Max Note 2 Unit ns -- 45 55 % RP,RD output delay after CLKO↓ tOD(1) -5 5 ns CV output delay after CLKO↓ tOD(2) -5 5 ns Note 1: CKLO symmetry is measured about the 50% amplitude point. Note 2: The clock output can be 6, 8, or 34 MHz (refer to page 4). - 13 - TXC-02050-MB Ed. 3, April 1994 MRT Figure 8. P and N Rail Transmit Input tPWH tCYC CLKI 1.4V tSU tH TP,TD DATA VALID DATA VALID DATA VALID TN DATA VALID DATA VALID DATA VALID Parameter Symbol CLKI clock period Min Typ tCYC CLKI duty cycle (tPWH/tCYC) Max Note 2 Unit ns -- 45 55 % TP,TD & TN set-up time to CLKI↑ tSU 3 ns TP,TD & TN hold time after CLKI↑ tH 2 ns Note 1: CLKI symmetry is measured about the 1.4VDC threshold. Note 2: The clock input can be 6, 8, or 34 MHz (refer to page 5). tOD(1) Figure 9. P and N Rail Receive Timing tCYC tPWH CLKO CLKO RP,RD tOD(2) RN Parameter CLKO clock period CLKO duty cycle (tPWH/tCYC) Symbol Min tCYC -- CLKO output delay after CLKO↑ tOD(1) RP, RD and RN output delay after CLKO↓ tOD(2) Typ Max Note 2 45 -5 Unit ns 55 % 2 ns 6 ns Note 1: CLKO symmetry is measured about the 50% amplitude point. Note 2: The clock output can be 6, 8, or 34 MHz (refer to page 4). - 14 - TXC-02050-MB Ed. 3, April 1994 MRT OPERATION POWER SUPPLY IN914 or IN4148 10/6.3v Ferrite Bead Fair Rite 2743002111 23 VAGC A VDD VDD 31 GNDA VDD A VDD A 10 10/6.3v 18 D 35 D 37 +5V A + D D D 42 D VDD GND GND GND GND GND GND GND GND + 1 6 11 16 32 36 39 44 D All capacitors are 0.1 microfarad unless otherwise specified D TXC-02050 Figure 10. MRT Power Supply Connections The MRT device has separate power supply pins labeled VDD and VAGC. The VAGC supply pin is connected to the internal AGC amplifier and requires isolation from the VDD supply as indicated in Figure 10. Separate bypass networks must be used for connecting the VDD and VAGC supply pins on the MRT to +5V. The bypass network on the VAGC pin consists of an IN4148 or IN914 diode, and a 10/6.3 volt microfarad (tantalum) capacitor connected in parallel with a 0.1 microfarad capacitor, as shown in Figure 10. TranSwitch recommends that the 0.1 microfarad decoupling capacitors be of RF quality and that they be connected in close proximity to the device. - 15 - TXC-02050-MB Ed. 3, April 1994 MRT OVERVIEW Line Side Input Impedance The input impedance of the MRT is a function of the state of the LOW lead and the operating rate. Table 1 lists the input impedance of the MRT at the operating line rates (which are 1/2 the bit rates). Table 1. MRT Input Impedance Condition Minimum Input Impedance, | Z | LOW = 1, line rate = 17184 kbit/s 1260 ohms LOW = 0, line rate = 4224 kbit/s 2390 ohms LOW = 0, line rate = 3156 kbit/s 3670 ohms Line Side Input Sensitivity The input voltage sensitivity of the MRT depends on the state of the LOW lead as shown in Table 2 below. Table 2. MRT Input Sensitivity Input Sensitivity (peak volts) Min Max LOW Lead 0 0.5 2.7 (6 & 8 Mbit/s) 1 0.15 1.1 (34 Mbit/s) Line Side Input Circuit The circuit shown in Figure 11 illustrates the component required for operating the MRT device for 34368, 8448 or 6312 kbit/s. The transformer should have a frequency response of 0.2 to 80 MHz with an insertion loss of 1 dB, maximum. TranSwitch recommends the use of a Coilcraft transformer (part no. WB-1010) or equivalent). This gives return loss and isolation voltage values that meet or exceed requirements. 1:1 29 Receive Data Input 75 5% + 10/6.3 30 + 0.1 10/6.3 TXC-02050 MRT Device 0.1 Figure 11. Line Side Input Circuit Line Side Output Characteristics The line side output of the MRT switches from “rail to rail” on both of its output leads, TPO and TNO. This provides the maximum voltage swing, and makes the output voltage depend on the +5 volt power supply input to the chip. The external circuit design must therefore be done with care in order to assure the meeting of the amplitude requirements. - 16 - TXC-02050-MB Ed. 3, April 1994 MRT Line Side Output Circuits Figure 12 illustrates the output circuit required for operating the MRT device for a 34368 kbit/s application. The transformer and resistors shown assure that the output waveform meets the CCITT mask for 34368 kbit/s transmission and that the MRT device is operated within the current limits of the TTL24mA output parameters on page 10. The transformer should have a frequency response of 0.1 - 100 MHz with an insertion loss of 1dB, maximum. 1:2 150 Transmit Data Output 34 33 TXC-02050 MRT Device 150 Figure 12. Line Side Output Circuit Outline (34368 kbit/s) Figure 13 shows a variation of the circuit in Figure 12. This circuit improves performance in applications when a plastic device is mounted in a socket. The additional low-pass filter compensates for possible overshoot caused by inductance created by the device/socket interface. The transformer should have a frequency response of 0.1 - 100 MHz with an insertion loss of 1dB, maximum. 1:2 75 100 Transmit Data Output 34 18 pf 100 33 TXC-02050 MRT Device 75 18 pf Figure 13. Line Side Output Circuit Outline (34368 kbit/s) The peak voltage and current output requirements for 6312 and 8448 kbit/s operation are different from that required for 34368 kbit/s operation. The output circuit in Figure 14 illustrates the output circuit required for 6312 kbit/s and 8448 kbit/s operation. The transformer should have a frequency response of .01 - 50 MHz with an insertion loss of 1dB, maximum. The transformer, drivers and resistors assure that the output waveform meets the CCITT masks for these rates and that the MRT device is operated within the current limits of the TTL24mA output parameters on page 10. 1:1 R1 Transmit Data Output 34 33 TXC-02050 MRT Device R2 ACT11034 For 8448 kbit/s operation: R1 and R2 = 27Ω For 6312 kbit/s operation: R1 and R2 = 36Ω Figure 14. Line Side Output Circuit Outline (8448 and 6312 kbit/s) - 17 - TXC-02050-MB Ed. 3, April 1994 MRT Jitter Tolerance CCITT Recommendation G.823 specifies that network equipment must be able to accommodate and tolerate levels of jitter up to certain specified limits. The MRT accommodates and tolerates more input jitter than the level of input jitter specified by the CCITT. With input jitter applied to the MRT line side receive input DI1 (pin 29), the MRT properly recovers clock, decodes the HDB3, and outputs error-free NRZ data over (and beyond) the CCITT specified jitter input and frequency ranges. Performance characteristics are shown below in Figure 15 (34.368 Mbit/s operation) and Figure 16 (8.448 Mbit/s operation). LOG SCALE Measured 10.0 30 kHz INPUT JITTER UI (PEAK- PEAK) Minimum Requirement Acceptance Range 1.0 CCITT Rec. G.823 Limit 0.1 10Hz 100Hz 10kHz 1kHz Frequency 100kHz 1MHz LOG SCALE Figure 15. MRT Jitter Tolerance at34.368 Mbit/s (VDD = 5V, TA = 25oC) LOG SCALE Measured 10.0 10 kHz INPUT JITTER UI (PEAK- PEAK) Minimum Requirement 1.0 Acceptance Range CCITT Rec. G.823 Limit 0.1 10Hz 100Hz 10kHz 1kHz Frequency 100kHz 1MHz Figure 16. MRT Jitter Tolerance at 8.448 Mbit/s (VDD = 5V, TA = 25oC) - 18 - TXC-02050-MB Ed. 3, April 1994 MRT Maximum Output Jitter In Absence of Input Jitter CCITT Recommendation G.823 specifies that it is necessary to restrict the amount of jitter generated by individual equipments. The actual limits depend on the type of equipment (and application). In the absence of applied jitter, the receive path of the MRT introduces a maximum 0.05 Unit Intervals (UIs) peak-to-peak jitter over the following frequency ranges: At 8.448 Mbit/s: 20 Hz to 400 kHz At 34.368 Mbit/s: 100 Hz to 800 kHz This operation is with the MRT terminated by the external components (and component values) specified in the Pin Description Table for pin 7 (VCOC), pin 17 (PLLC), and pin 22 (AGFIL). Jitter Transfer Transfer of jitter through an individual equipment is characterized by the relationship between the applied input jitter and the resulting output jitter as a function of frequency. CCITT Recommendation G.823 specifies that it is important to restrict jitter gain. With applied input jitter at the MRT receive terminals, the maximum MRT output jitter is not greater than the level of input jitter plus 0.05 UI peak-to-peak jitter. This operation is over the same CCITT specified frequency ranges and MRT external terminations as described in the above Maximum Output Jitter section. Interfering Tone Tolerance The MRT will properly recover clock and present error-free output to the receive terminal side interface in the presence of a PRBS interfering tone with the same data sequence as the data input for the following line rates: Table 3. Interfering Tone Tolerance Data Rate (Mbit/s) Tone Rate (Mbit/s) Maximum Tone Level Data Sequence 34.368 34.368 ± 100ppm -18 dB 223-1 8.448 8.448 ± 100ppm -4 dB 215 - 1 6.312 6.312 ± 100ppm -4 dB 215 - 1 *PRBS = Pseudo-Random Binary Sequence - 19 - TXC-02050-MB Ed. 3, April 1994 MRT PACKAGING The MRT device is packaged in a 44-pin plastic leaded chip carrier suitable for socket or surface mounting. All dimensions shown are in inches and are nominal unless otherwise noted. .170 nom. .650 (nom) SQ. .500 (nom) SQ. .075 6 1 .690 (nom) SQ. .149 nom. 40 40 1 6 .050 typ 7 39 7 39 TRANSWITCH .015 typ 17 29 18 17 29 28 28 18 BOTTOM VIEW TOP VIEW Figure 17. MRT 44-Pin Plastic Leaded Chip Carrier - 20 - TXC-02050-MB Ed. 3, April 1994 MRT ORDERING INFORMATION Part Number: TXC-02050-AIPL 44-pin Plastic Leaded Chip Carrier RELATED PRODUCTS TXC-03701 E2/E3F Framer VLSI device. The E2/E3 Framer directly interfaces with the MRT and provides multi-mode framing for CCITT G.751/G.753 (34368 kbit/s) or CCITT G.742/ G.745 (8448 kbit/s) signals. TXC-03702 JT2F Framer VLSI device. The JT2F Framer directly interfaces with the MRT and provides framing for CCITT G.704 (6312 kbit/s) signals. TXC-21055 MRT Evaluation Board. A complete ready-to-use single board that demonstrates the functions and features of the MRT line interface VLSI device. - 21 - TXC-02050-MB Ed. 3, April 1994 MRT STANDARDS DOCUMENTATION SOURCES Telecommunication technical standards and reference documentation may be obtain from the following organizations: ANSI (U.S.A.): American National Standards Institute (ANSI) 11 West 42nd Street New York, New York 10036 Tel: 212-642-4900 Fax: 212-302-1286 Bellcore (U.S.A.): Bellcore Attention - Customer Service 8 Corporate Place Piscataway, NJ 08854 Tel: 800-521-CORE (In U.S.A.) Tel: 908-699-5800 Fax: 908-336-2559 CCITT: Publication Services of ITU Place des Nations CH 1211 Geneve 20, Switzerland Tel: 41-22-730-5285 Fax: 41-22-730-5991 TTC (Japan): TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsucho - Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 81-3-3432-1551 Fax: 81-3-3432-1553 - 22 - TXC-02050-MB Ed. 3, April 1994 MRT LIST OF DATA SHEET CHANGES This change list identifies those areas within the updated MRT Data Sheet that have technical differences relative to the superseded MRT Data Sheet: Updated MRT Data Sheet: Edition 3, April 1994 Superseded MRT Data Sheet: Edition 2, February 1992 The page numbers indicated below of the updated data sheet include changes relative to the superseded data sheet. Page Number of Updated Data Sheet Summary of the Change All Changed edition number and date on all pages. All Removed “Preliminary” designation. 2 Changed direction of DI2 pin in Figure 1, Block Diagram. 2-3 Made minor edits to Block Diagram Description. 4 Replaced description of pin 30, DI2. 5 Edited descriptions of pins 5 (LQLTY) and 38 (CLKI). 6 Made minor edits to descriptions of pins 4 (BERCK), 24 (LBKRX) and 25 (LBKTX). Also added Note 1 at bottom of page. 7 Added value for f in description of pins 27 and 28 (EQB1 and EQB0), and replaced description of pin 7 (VCOC). 8 Added values to first row of Thermal Characteristics table and removed second row. 11-12 Made minor clarifications to second paragraph of text and to Figures 3, 4, and 5. 13 Deleted Note 3 below Figure 7. 14 Deleted Note 3 below Figure 9. 15 Made minor changes to Figure 10. 16 Added two sentences to Line Side Input Circuit text. 17 Made minor edits to Figure 13 and to the paragraph of text below it. 17 Made minor changes to Figure 14. 18 Added Jitter Generation paragraph. 18 Changed Jitter Transfer text at bottom of page. 19 Changed Interfering Tone Tolerance text, added the Data Sequence column to Table 3, and removed Table 4. 20 Removed ceramic packaging diagram and added measurements to Figure 17, plastic packaging diagram. 22 Added Standards Documentation Sources. - 23 - TXC-02050-MB Ed. 3, April 1994 MRT - NOTES - - 24 - TXC-02050-MB Ed. 3, April 1994 MRT - NOTES - TranSwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. TranSwitch assumes no liability for TranSwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TranSwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TranSwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. - 25 - TXC-02050-MB Ed. 3, April 1994 TranSwitch VLSI: Powering Communication Innovation TranSwitch Corporation • 8 Progress Drive • Shelton, CT 06484 • USA • Tel: 203-929-8810 • Fax: 203-926-9453 MRT DOCUMENTATION UPDATE REGISTRATION FORM If you would like be added to our database of customers who have registered to receive updated documentation for this device as it becomes available, please provide your name and address below, and fax or mail this page to Mary Koch at TranSwitch. Mary will ensure that relevant Product Information Sheets, Data Sheets, Application Notes and Technical Bulletins are sent to you. Please print or type the information requested below, or attach a business card. Name: ________________________________________________________________________ Title: _________________________________________________________________________ Company: _____________________________________________________________________ Dept./Mailstop: ________________________________________________________________ Street: _______________________________________________________________________ City/State/Zip: _________________________________________________________________ If located outside U.S.A., please add - Postal Code: ___________ Country: ______________ Telephone:______________________________________________ Ext.: _________________ Fax: __________________________________ E-Mail: _______________________________ Purchasing Dept. Location: _______________________________________________________ Please describe briefly your intended application for this device, and indicate whether you would care to have a TranSwitch applications engineer contact you to provide assistance: ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ If you are also interested in receiving updated documentation for other TranSwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ Please fax this page to Mary Koch at (203) 926-9453 or fold, tape and mail it (see other side) - 27 - TXC-02050-MB Ed. 3, April 1994 TranSwitch VLSI: Powering Communication Innovation (Fold back on this line second, then tape closed, stamp and mail.) First Class Postage Required TranSwitch Corporation Attention: Mary Koch 8 Progress Drive Shelton, CT 06484 U.S.A. (Fold back on this line first.) Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available. TranSwitch Corporation • 8 Progress Drive • Shelton, CT 06484 • USA • Tel: 203-929-8810 • Fax: 203-926-9453