W741C250 4-BIT MICROCONTROLLER Table of Contents-GENERAL DESCRIPTION .........................................................................................................................2 FEATURES.................................................................................................................................................2 PIN CONFIGURATION ...............................................................................................................................3 PIN DESCRIPTION.....................................................................................................................................4 BLOCK DIAGRAM ......................................................................................................................................5 FUNCTIONAL DESCRIPTION ...................................................................................................................6 ABSOLUTE MAXIMUM RATINGS .............................................................................................................32 DC CHARACTERISTICS............................................................................................................................32 AC CHARACTERISTICS ............................................................................................................................33 PAD ASSIGNMENT & POSITIONS............................................................................................................34 TYPICAL APPLICATION CIRCUIT.............................................................................................................36 INSTRUCTION SET TABLE .......................................................................................................................37 PACKAGE DIMENSIONS...........................................................................................................................85 -1- Publication Release Date: March 1998 Revision A4 W741C250 GENERAL DESCRIPTION The W741C250 is a high-performance 4-bit microcontroller (µC) that provides an LCD driver. The device contains a 4-bit ALU, two 8-bit timers, a divider, a 24 × 4 LCD driver, and five 4-bit I/O ports (including 1 output port for LED driving). There are also five interrupt sources and 8-level subroutine nesting for interrupt applications. The W741C250 operates on low voltage and very low current and has two power reduction modes, hold mode and stop mode, which help to minimize power dissipation. The W741C250 is suitable for remote controllers, watches and clocks, multiple I/O products, keyboard controllers, speech synthesis LSI controllers, and other products. FEATURES • Operating voltage: 2.2V to 5.5V (LCD drive voltage: 3.0V or 4.5V) • Operating frequency up to 4 MHz • Crystal/RC oscillation circuit selectable by code option for system clock • High-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32.768 KHz) for crystal mode by code option • Memory − 2048 × 16 bit program ROM (including 2K × 4 bit look-up table) − 128 × 4 bit data RAM (including 16 working registers) − 24 × 4 LCD data RAM • 21 input/output pins − Ports for input only: 2 ports/8 pins − Input/output ports: 2 ports/8 pins − Port for output only: 1 port /4 pins (high sink current for LED driving) − MFP output pin: 1 pin (MFP) • Power-down mode − Hold function: no operation (except for oscillator) − Stop function: no operation (including oscillator) • Five types of interrupts − Three internal interrupts (Divider 0, Timer 0, Timer 1) − Two external interrupts (Port RC and INT pin) • LCD driver output − 24 segment × 4 common − Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) driving mode can be selected − LCD driver output pins can be used as DC output port by code option -2- W741C250 • MFP output pin − Output is software selectable as modulating or nonmodulating frequency − Works as frequency output specified by Timer 1 • Built-in 14-bit clock frequency divider circuit • Two built-in 8-bit programmable countdown timers − Timer 0: One of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected • • • • • − Timer 1: Offers auto-reload function and one of two internal clock frequencies (FOSC or FOSC/64) can be selected or falling edge of pin RC.0 can be selected (output through MFP pin) Built-in 18/14-bit watchdog timer selectable for system reset Powerful instruction set: 116 instructions 8-level subroutine (include interrupt) nesting Up to 1 µS instruction cycle (with 4 MHz operating frequency) Packaged in 64-pin QFP PIN CONFIGURATION S S S S S X R M / I A F N 0 P T V V V E E E E E / X O V D D D D D G G G G G R E I U D N N H H D D D 2 2 2 2 1 S N T D C C 1 2 1 2 3 3 2 1 0 9 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RA1 52 32 SEG18 RA2 RA3 53 31 SEG17 54 55 30 SEG16 SEG15 RB0 RB1 29 28 56 RB2 RB3 57 58 RC0 RC1 RC2 59 60 61 24 RC3 62 RD0 RD1 63 64 22 21 27 26 25 23 20 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 R R R R R R V N N C C C C S S S S S S D D E E E E S C C O O O O E E E E E E 2 3 0 1 2 3 S M M M M G G G G G G 3 2 1 0 0 1 2 3 4 5 -3- Publication Release Date: March 1998 Revision A4 W741C250 PIN DESCRIPTION SYMBOL I/O FUNCTION XIN I Input pin for oscillator. Connected to crystal or resistor to generate system clock by code option. XOUT O Output pin for oscillator. Connected to crystal or resistor to generate system clock by code option. RA0−RA3 I/O Input/Output port. Input/output mode specified by port mode 1 register (PM1). RB0−RB3 I/O Input/Output port. Input/output mode specified by port mode 2 register (PM2). RC0−RC3 I 4-bit port for input only. Each pin has an independent interrupt capability. RD0−RD3 I 4-bit port for input only. RE0−RE3 O Output port only. This port provides high sink current to drive LED. MFP O Output pin only. This pin can output modulating or nonmodulating frequency, or Timer 1 clock output specified by mode register 1 (MR1). INT I External interrupt pin with pull-high resistor. RES I System reset pin with pull-high resistor. SEG0−SEG23 O LCD segment output pins. Also can be used as DC output ports specified by code option. COM0−COM3 O LCD common signal output pins. COM0 Static 1/2 Duty 1/3 Duty 1/4 Duty Used Used Used Used Used Used Used Used Used COM1 Not Used COM2 Not Used Not Used COM3 Not Used Not Used Not Used Used The LCD alternating frequency can be selected by code option. -4- W741C250 Pin Description, continued SYMBOL I/O FUNCTION DH1, DH2 I Connection terminals for voltage doubler (halver) capacitor. VDD1, VDD2, VDD3 I Refer to Functional Description. VDD I Positive power supply (+). VSS I Negative power supply (-). Positive (+) supply voltage terminal. BLOCK DIAGRAM SEG0 to SEG23 COM0 to COM3 VDD1 to 3 DH1 to 2 LCD DRIVER RAM (128*4) PORT RA RA0 to 3 PORT RB RB0 to 3 PORT RD RD0 to 3 PORT RC RC0 to 3 PORT RE RE0 to 3 ACC ROM (2048*16) ALU (look_up table 2K*4) +1(+2) PC Central Control Unit STACK (8 Levels) IEF HEF PEF HCF EVF SEF PSR0 PR MR1 . Timer 0 (8 Bit) Watchdog Timer (4 Bit) . . Timer 1 (8 Bit) Modulation Frequency Pulse SEL MUX MFP VDD VSS Divider 0 (14 Bit) Timing Generator INT RES XIN -5- XOUT Publication Release Date: March 1998 Revision A4 W741C250 FUNCTIONAL DESCRIPTION Program Counter (PC) Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses of the 2048 × 16 on-chip ROM containing the program instruction words. When jump or subroutine call instructions or interrupt or initial reset conditions are to be executed, the address corresponding to the instruction will be loaded into the program counter. The format used is shown below. ITEM ADDRESS INTERRUPT PRIORITY Initial Reset 000H - INT 0 (Divider 0) 004H 1st INT 1 (Timer 0) 008H 2nd INT 2 (Port RC) 00CH 3rd INT 4 ( INT pin) 014H 4th INT 7 (Timer 1) 020H 5th JP Instruction XXXH - Subroutine Call XXXH - Stack Register (STACK) The stack register is organized as 11 bits × 8 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. When the stack register is pushed over the eighth level, the contents of the first level will be lost. In other words, the stack register is always eight levels deep. Program Memory (ROM) The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048 × 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements. There are two registers (TABL and TABH) to be used in look-up table addressing and they are controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is executed, the contents of the look-up table location address specified by TABH, TABL and ACC will be read and transfered to the data RAM. Refer to the instruction table for more details. The organization of the program memory is shown in Figure 1. -6- W741C250 16 bits 000H TABH - x x x 2048 address TABL x x x x ACC x x y y Offset 0 1 1 x x x x x x x x x ROM address = 600H + Offset/4 600H 3 2 1 0 This area can be used to store both instruction cod and look-up table Each element (4 bits) of the look-up table 7FFH 2048 x 16-bit Figure 1. Program Memory Organization Data Memory (RAM) 1. Architecture The static data memory (RAM) used to store data is arranged as 128 × 4 bits. The data memory can be addressed directly or indirectly. The organization of the data memory is shown in Figure 2. 4 bits 00H : 0FH Working Register 128 address 7FH 128 x 4-bit Figure 2. Data Memory Organization The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers (WR). The other data memory is used as general memory and cannot operate directly with immediate data. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next section. -7- Publication Release Date: March 1998 Revision A4 W741C250 2. Page Register (PAGE) The page register is organized as a 4-bit binary register. The bit descriptions are as follows: PAGE 3 _ 2 1 0 R/W R/W R/W Note: R/W means read/write available. Bit 3 is reserved. Bit 2, Bit 1, Bit 0 are indirect addressing mode preselect bits: 000 = Page 0 (00H−0FH) 001 = Page 1 (10H−1FH) 010 = Page 2 (20H−2FH) 011 = Page 3 (30H−3FH) 100 = Page 4 (40H−4FH) 101 = Page 5 (50H−5FH) 110 = Page 6 (60H−6FH) 111 = Page 7 (70H−7FH) Accumulator (ACC) The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers. Arithmetic and Logic Unit (ALU) This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions: • Logic operations: ANL, XRL, ORL • Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3 • Shift operations: SHRC, RRC, SHLC, RLC • Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOVA R, CF. Clock Generator The W741C250 provides a crystal or RC oscillation circuit selected by option codes to generate the system clock through external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be connected to XIN and XOUT, and the capacitor must be connected if an accurate frequency is needed. When a crystal oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32 KHz) can be selected for the system clock by means of option codes. If the RC oscillator is used, a resistor in the range of 20 KΩ to 1.6 MΩ must be connected to XIN and XOUT, as shown in Figure 3. The system clock frequency range is from 32 KHz to 4 MHz. One machine cycle consists of a four-phase system clock sequence and can run up to 1 µS with a 4 MHz system clock. XIN XIN Crystal 32 KHz or 400K to 4MHz or Resistor XOUT XOUT Figure 3. Oscillator Configuration -8- W741C250 Divider 0 Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as shown in Figure 4. When the system starts, the divider is incremented by each system clock (FOSC). When an overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. In addition, the 4 MSB of the divider can be reset by executing the CLR DIVR0 instruction. Watchdog Timer (WDT) The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset. The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, the WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4. Fosc Q1 Q2 Divider0 ...Q9 Q10 HEF.0 Q11 Q12 Q13 Q14 R R R R EVF.0 S Q IEF.0 R Hold mode release (HCF.0) Divider0 interrupt (INT0) 1. Reset 2. CLR EVF, #01H 3. CLR DIVR0 WDT PMF.3 Fosc/16384 Fosc/1024 Qw1 Qw2 Qw3 Qw4 R Enable /Disable Mask Option R R Overflow signal R System Reset 1. Reset 2. CLR WDT Figure 4. Organization of Divider 0 and Watchdog Timer Timer/Counter 1. Timer 0 (TM0) Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L (TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting), the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1 has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting -9- Publication Release Date: March 1998 Revision A4 W741C250 MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure 5. If the Timer 0 clock input is FOSC/4: Desired Timer 0 interval = (preset value +1) × 4 × 1/FOSC If the Timer 0 clock input is FOSC/1024: Desired Timer 0 interval = (preset value +1) × 1024 × 1/FOSC Preset value: Decimal number of Timer 0 preset value FOSC: Clock oscillation frequency 1. Reset 2. CLR EVF, #02H 3. Reset MR0.3 to 0 4. MOV TM0L, R or MOV TM0H, R MR0.0 Disable Fosc/1024 HEF.1 8-bit Binary Down Counter (Timer 0) Fosc/4 Enable R Hold mode release (HCF.1) Q IEF.1 EVF.1 8 MOV TM0H, R Timer 0 interrupt (INT1) 4 4 1. Set MR0.3 to 1 2. MOV TM0, #I S MOV TM0L, R 1. Reset 2. CLR EVF, #02H 3. Set MR0.3 to 1 4. MOV TM0, #I MOV TM0, #I Figure 5. Organization of Timer 0 2. Timer 1 (TM1) Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6. Timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: FOSC/64, FOSC, or an external clock from the RC.0 input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is FOSC. If an external clock is selected as the clock source of Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L, R or MOV TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set (MR1.3 = 1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into autoreload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting. - 10 - W741C250 If the Timer 1 clock input is FT, then: Desired Timer 1 interval = (preset value +1)/FT Desired frequency for MFP output pin = FT ÷ (preset value + 1) ÷ 2 (Hz) Preset value: Decimal number of Timer 1 preset value, and FOSC: Clock oscillation frequency MOV TM1, #I MOV TM1L, R MOV TM1H, R 8 Underflow signal 1. MR1.3 = 1 2. MOV TM1, #I 4 4 S MR1.1 8 bits Enable FT 8-bit Binary Down Counter (Timer 1) Fosc/64 2 circuit Disable Reset Set MR1.3 to 1 MOV TM1, #I Fosc MR1.0 EVF.7 1. Reset 2. INT 7 accept 3. CLR EVF, #80H 4. Set MR1.3 to 1 5. MOV TM1, #I Auto-reload buffer External clock via RC.0 Q R MFP output pin Reset MR1.2 MFP signal 1. MR1.3 = 0 Figure 6. Organization of Timer 1 For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below. 3 Tone frequency 4 TM1 preset value & MFP frequency Tone frequency 5 TM1 preset value & MFP frequency Tone frequency TM1 preset value & MFP frequency C 130.81 7CH 131.07 261.63 3EH 260.06 523.25 1EH 528.51 C# 138.59 75H 138.84 277.18 3AH 277.69 554.37 1CH 564.96 D 146.83 6FH 146.28 293.66 37H 292.57 587.33 1BH 585.14 D# 155.56 68H 156.03 311.13 34H 309.13 622.25 19H 630.15 O E 164.81 62H 165.49 329.63 31H 327.68 659.26 18H 655.36 F 174.61 5DH 174.30 349.23 2EH 372.36 698.46 16H 712.34 N F# 185.00 58H 184.09 369.99 2BH 390.09 739.99 15H 744.72 G 196.00 53H 195.04 392.00 29H 420.10 783.99 14H 780.19 G# 207.65 4EH 207.39 415.30 26H 443.81 830.61 13H 819.20 A 220.00 49H 221.40 440.00 24H 442.81 880.00 12H 862.84 A# 233.08 45H 234.05 466.16 22H 468.11 932.23 11H 910.22 B 246.94 41H 248.24 493.88 20H 496.48 987.77 10H 963.76 T E Note: Central tone is A4 (440 Hz). - 11 - Publication Release Date: March 1998 Revision A4 W741C250 Mode Register 0 (MR0) Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows: 3 MR0 2 1 W 0 W Note: W means write only. Bit 0 = 0 The internal fundamental frequency of Timer 0 is FOSC/4. = 1 The internal fundamental frequency of Timer 0 is FOSC/1024. Bit 1 Reserved Bit 2 Reserved Bit 3 = 0 Timer 0 stops down-counting. = 1 Timer 0 starts down-counting. Mode Register 1 (MR1) Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows: MR1 3 2 1 0 W W W W Note: W means write only. Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC. = 1 The internal fundamental frequency of Timer 1 is FOSC/64. Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock. = 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin. Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin. = 1 The specified frequency of Timer 1 is delivered at the MFP output pin. Bit 3 = 0 Timer 1 stops down-counting. = 1 Timer 1 starts down-counting. Interrupts The W741C250 provides three internal interrupt sources (Divider 0, Timer 0, Timer 1) and two external interrupt sources ( INT , port RC). Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the - 12 - W741C250 interrupts are inhibited until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily and the interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt subroutine, the µC will enter hold mode again. The operation flow chart is shown in Figure 8. The control diagram is shown below. Interrupt Event Control Diagram Divider 0 overflow signal Timer 0 underflow signal EN INT MOV IEF, #I S R S Q Q INT pin falling edge signal S R S IEF.0 EVF.1 IEF.1 Q Q EVF.2 IEF.2 S Interrupt Process Circuit Interrupt Vector Generator 008H 00CH 014H 020H IEF.4 Q R 004H EVF.4 R Timer 1 underflow signal Enable EVF.0 R Port RC signal change Initial Reset EVF.7 IEF.7 Initial Reset Disable CLR EVF, #I instruction DIS INT instruction Figure 7. Interrupt Event Control Diagram Stop Mode Operation In stop mode, all operations of the µC cease (including the operation of the oscillator). The µC enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated (by a low level on the INT pin or a falling signal on the RC port). When the designated signal is accepted, the µC awakens and executes the next instruction (if the corresponding bits of IEF and PEF have been set, It will enter the interrupt service routine after stop mode released). To prevent erroneous execution, the NOP instruction should follow the STOP command. Hold Mode Operation In hold mode, all operations of the µC cease, except for the operation of the oscillator, timer, and LCD driver. The µC enters hold mode when the HOLD instruction is executed. The hold mode can be released in one of five ways: by the action of Timer 0, Timer 1, Divider 0, the INT pin, or the RC port. - 13 - Publication Release Date: March 1998 Revision A4 W741C250 Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release conditions. For more details, refer to the instruction-set table and the following flow chart. Divider 0, Timer 0, Timer 1, INT, Signal Change on Port RC In HOLD Mode? Yes No No Interrupt Enable? No Interrupt Enable? Yes Yes No IEF Flag Set? No IEF Flag Set? Yes Yes Reset EVF.n Flag Execute Interrupt Service Routine Reset EVF.n Flag Execute Interrupt Service Routine HEF Flag Set? (Note) No Yes (Note) Disable interrupt Disable interrupt HOLD PC <- (PC+1) Note : The bit of EVF corresponding to the interrupt request signal will be reset. Figure 8. Hold Mode and Interrupt Operation Flow Chart Hold Mode Release Enable Flag (HEF) The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I instruction. The bit descriptions are as follows: 7 HEF w 6 5 4 3 w 2 1 0 w w w Note: W means write only. HEF.0 = 1 Overflow from Divider 0 causes hold mode to be released. HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released. HEF.2 = 1 Signal change at port RC causes hold mode to be released. - 14 - W741C250 HEF.3 Reserved HEF.4 = 1 Falling edge signal at the INT pin causes hold mode to be released. HEF.5 & HEF.6 are reserved. HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released. Interrupt Enable Flag (IEF) The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or EN INT is executed again. Besides, these interrupts can be disabled by executing DIS INT instruction. The bit descriptions are as follows: 7 IEF 6 5 4 w 3 w 2 1 0 w w w Note: W means write only. IEF.0 = 1 IEF.1 = 1 IEF.2 = 1 IEF.3 Interrupt 0 is accepted by overflow from Divider 0. Interrupt 1 is accepted by underflow from Timer 0. Interrupt 2 is accepted by a signal change on port RC. Reserved IEF.4 = 1 Interrupt 4 is accepted by a falling edge signal on the INT pin. IEF.5 & IEF.6 are reserved. IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1. Port Enable Flag (PEF) The port enable flag is organized as a 4-bit binary register (PEF.0 to PEF.3). Before port RC may be used to release the hold mode or perform an interrupt function, the content of the PEF must be set first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows: PEF 3 2 1 0 w w w w Note: W means write only. PEF.0: Enable/disable the signal change on pin RC.0 to release hold mode or perform interrupt. PEF.1: Enable/disable the signal change on pin RC.1 to release hold mode or perform interrupt. PEF.2: Enable/disable the signal change on pin RC.2 to release hold mode or perform interrupt. PEF.3: Enable/disable the signal change on pin RC.3 to release hold mode or perform interrupt. Stop Mode Wake-up Enable Flag for Port RC (SEF) The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3). Before port RC may be used to make the device exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows: - 15 - Publication Release Date: March 1998 Revision A4 W741C250 SEF 3 2 1 0 w w w w Note: W means write only. SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0. SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1. SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2. SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3. Hold Mode Release Condition Flag (HCF) The hold mode release condition flag is organized as an 8-bit binary register (HCF0 to HCF7). It indicates by which interrupt source the hold mode has been released, and it is loaded by hardware. The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset by the CLR EVF, #I (EVF.n = 0) or MOV HEF, #I (HEF.n = 0) instructions. When EVF or HEF has been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows: 7 6 HCF 5 4 R R 3 2 1 0 R R R Note: R means read only. HCF.0 = 1 Hold mode was released by overflow from Divider 0. HCF.1 = 1 Hold mode was released by underflow from Timer 0. HCF.2 = 1 Hold mode was released by a signal change on port RC. HCF.3 Reservsd HCF.4 = 1 Hold mode was released by a falling edge signal on the INT pin. HCF.5 = 1 Hold mode was released by underflow from Timer 1. HCF.6 & HCF.7 are reserved. Event Flag (EVF) The event flag is organized as a 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset by the CLR EVF, #I instruction or the occurrence of an interrupt. The bit descriptions are as follows: 7 EVF R 6 5 4 3 R Note: R means read only. EVF.0 = 1 Overflow from Divider 0 occurred. EVF.1 = 1 Underflow from Timer 0 occurred. EVF.2 = 1 Signal change on port RC occurred. - 16 - 2 1 0 R R R W741C250 EVF.3 Reserved EVF.4 = 1 Falling edge signal on the INT pin occurred. EVF.5 & EVF.6 are reserved. EVF.7 = 1 Underflow from Timer 1 occurred. Parameter Flag (PMF) The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows: 3 PMF 2 1 0 W Note: W means write only. Bit 0, Bit1, Bit2 Reserved Bit 3 = 0 The fundamental frequency of the watchdog timer is FOSC/1024. = 1 The fundamental frequency of the watchdog timer is FOSC/16384. Port Mode 0 Register (PM0) The port mode 0 register is organized as a 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction. The bit descriptions are as follows: PM0 3 2 1 0 w w w w Note: W means write only. Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type. Bit 1 = 0 RB port is CMOS output type. Bit 1 = 1 RB port is NMOS open drain output type. Bit 2 = 0 RC port pull-high resistor is disabled. Bit 2 = 1 RC port pull-high resistor is enabled. Bit 3 = 0 RD port pull-high resistor is disabled. Bit 3 = 1 RD port pull-high resistor is enabled. Port Mode 1 Register (PM1) The port mode 1 register is organized as a 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit descriptions are as follows: - 17 - Publication Release Date: March 1998 Revision A4 W741C250 PM1 3 2 1 0 w w w w Note: W means write only. Bit 0 = 0 RA.0 works as output pin. Bit 0 = 1 RA.0 works as input pin. Bit 1 = 0 RA.1 works as output pin. Bit 1 = 1 RA.1 works as input pin. Bit 2 = 0 RA.2 works as output pin. Bit 2 = 1 RA.2 works as input pin. Bit 3 = 0 RA.3 works as output pin. Bit 3 = 1 RA.3 works as input pin. After initial reset, port RA is in input mode (PM1 = 1111B). Port Mode 2 Register (PM2) The port mode 2 register is organized as a 4-bit binary register (PM2.0 to PM2.3). PM2 can be used to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit descriptions are as follows: PM2 3 2 1 0 w w w w Note: W means write only. Bit 0 = 0 RB.0 works as output pin. Bit 0 = 1 RB.0 works as input pin. Bit 1 = 0 RB.1 works as output pin. Bit 1 = 1 RB.1 works as input pin. Bit 2 = 0 RB.2 works as output pin. Bit 2 = 1 RB.2 works as input pin. Bit 3 = 0 RB.3 works as output pin. Bit 3 = 1 RB.3 works as input pin. After initial reset, port RB is in input mode (PM2 = 1111B). Reset Function The W741C250 is reset either by a power-on reset or by using the external RES pin. The initial state of the W741C250 after the reset function is executed is described below. Program Counter (PC) 000H TM0, TM1 Reset MR0, MR1, PM0, PAGE, PMF registers Reset PM1, PM2 registers Set (1111B) PSR0 register Reset IEF, HEF, HCF, PEF, EVF, SEF flags Reset Timer 0 input clock FOSC/4 Timer 1 input clock FOSC MFP output Low Input/output ports RA, RB Input mode - 18 - W741C250 Reset Function, continued Output port RE High RA & RB ports output type CMOS type RC & RD ports pull-high resistors Disabled Input clock of the watchdog timer FOSC/1024 LCD display OFF Segment output mode LCD drive output External INT The external interrupt INT pin contains a pull-up resistor. When the HEF.4 or IEF.4 flag is set, the falling edge of the INT pin will execute the hold mode release or interrupt subroutine. A low level on the INT pin will release the stop mode. Input/Output Ports RA, RB Port RA consists of pins RA.0 to RA.3 and port RB consists of pins RB.0 to RB.3. After initial reset, input/output ports RA and RB are both in input mode. When RA and RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or RB can be specified as input or output mode independently by the PM1 and PM2 registers. The MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV RB, R operate the output functions. For more details, refer to the instruction table and Figure 9. Input/Output Pin of the RA(RB) VDD PM0.0 (or PM0.1) Output Buffer DATA BUS I/O PIN RA.n(RB.n) Enable MOV RA, R (or MOV RB, R) Instruction PM1.n (or PM2.n) Enable MOVA R, RA (or MOVA R, RB) instruction Figure 9. Architecture of Input/Output Pins Input Ports RC, RD Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. Each pin of port RC and port RD can be connected to a pull-up resistor, which is controlled by the port mode 0 register (PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change on the specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register 0 (PSR0) records the status of ports RC, i.e., any signal changes on the pins that make up the port. PSR0 can be read out and cleared by the MOV R, PSR0, and CLR PSR0 instructions. In addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will - 19 - Publication Release Date: March 1998 Revision A4 W741C250 cause the device to exit the stop mode. Refer to Figure 10 and the instruction table for more details. The RD port is used as input port only, it has no hold mode release, wake-up stop mode or interrupt functions. DATA BUS PEF.0 PM0.2 D ck Signal change detector RC.0 Q PSR0.0 R HEF.2 EVF.2 PEF.1 PM0.2 D ck Signal change detector RC.1 Q D ck PSR0.1 HCF.2 Q R R IEF.2 INT 2 PEF.2 PM0.2 D ck Signal change detector RC.2 Q PSR0.2 CLR EVF, #I R Reset PEF.3 PM0.2 D ck Signal change detector RC.3 Q PSR0.3 R Reset MOV PEF, #I CLR PSR0 SEF.0 Falling edge detector SEF.1 Falling edge detector Wake up from STOP mode SEF.2 Falling edge detector SEF.3 Falling edge detector Figure 10. Architecture of Input Ports RC Output Port RE When the MOV RE, R instruction is executed, the data in the RAM will be output to port RE. Port RE (RE.0 to RE.3) also provides high sink current output to drive LEDs. Port Status Register 0 (PSR0) Port status register 0 is organized as a 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows: PSR0 3 2 1 0 R R R R Note: R means read only. - 20 - W741C250 Bit 0 = 1 Signal change on RC.0. Bit 1 = 1 Signal change on RC.1. Bit 2 = 1 Signal change on RC.2. Bit 3 = 1 Signal change on RC.3. MFP Output Pin (MFP) The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal from among DC, 4096 Hz, 2048 Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (when using a 32.768 KHz system clock). The MOV MFP, #I instruction is used to specify the modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown as below: (FOSC = 32.768 KHz) R7 R6 0 0 0 1 1 0 R5 R4 R3 R2 R1 R0 FUNCTION 0 0 0 0 0 0 0 0 0 0 0 1 128 Hz 0 0 0 0 1 0 64 Hz 0 0 0 1 0 0 8 Hz 0 0 1 0 0 0 4 Hz 0 1 0 0 0 0 2 Hz 1 0 0 0 0 0 1 Hz 0 0 0 0 0 0 High level 0 0 0 0 0 1 128 Hz Low level 0 0 0 0 1 0 64 Hz 0 0 0 1 0 0 8 Hz 0 0 1 0 0 0 4 Hz 0 1 0 0 0 0 2 Hz 1 0 0 0 0 0 1 Hz 0 0 0 0 0 0 2048 Hz 0 0 0 0 0 1 2048 Hz * 128 Hz 0 0 0 0 1 0 2048 Hz * 64 Hz 0 0 0 1 0 0 2048 Hz * 8 Hz 0 0 1 0 0 0 2048 Hz * 4 Hz 0 1 0 0 0 0 2048 Hz * 2 Hz 1 0 0 0 0 0 2048 Hz * 1 Hz - 21 - Publication Release Date: March 1998 Revision A4 W741C250 ( MFP output table, continued) 1 1 0 0 0 0 0 0 4096 Hz 0 0 0 0 0 1 4096 Hz * 128 Hz 0 0 0 0 1 0 4096 Hz * 64 Hz 0 0 0 1 0 0 4096 Hz * 8 Hz 0 0 1 0 0 0 4096 Hz * 4 Hz 0 1 0 0 0 0 4096 Hz * 2 Hz 1 0 0 0 0 0 4096 Hz * 1 Hz LCD Controller/Driver The W741C250 can directly drive an LCD with 24 segment output pins and 4 common output pins for a total of 24 × 4 dots. Option codes can be used to select one of five options for the LCD driving mode: static, 1/2 bias 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/3 duty, or 1/3 bias 1/4 duty (see Figure 12). The alternating frequency of the LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. In addition, option codes can also be used to set up four of the LCD driver output pins (segment 0 to segment 23) as a DC output port. The structure of the LCD alternating frequency (FLCD) is shown in the figure below. Divider 0 Fosc Timing Generator Q1 Q2 Q3 Q4 Q5 Fw Q1 Q2 Q14 Fosc/32 High frequency clock Low frequency clock ... Q6 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Fw/64 Fw/128 Fw/256 Fw/512 Selector Figure 11. LCD Alternating Frequency (FLCD) Circuit Diagram - 22 - FLCD W741C250 Data Bus Option Codes LCD Frequency Selection Fw Clock Generator LCD Data RAM (24 x 4 bits) LCD Drive Mode Selection LCD Mode Controller MOV LCDM, # Instruction LCD Duty & Bias FLCD DH1 DH2 LCD Voltage Controller VDD VSS VDD1 to 3 LCD Waveform Common Driver Segment Driver/Controller SEG0 to 23 COM0 to 3 Figure 12. LCD Driver/Controller Circuit Diagram When Fw = 32.768 KHz, the LCD frequency is as shown in the table below. LCD FREQUENCY STATIC Fw/512 (64 Hz) Fw/256 (128 Hz) Fw/128 (256 Hz) Fw/64 (512 Hz) 64 128 256 512 1/2 DUTY 1/3 DUTY 1/4 DUTY 32 64 128 256 21 43 85 171 16 32 64 128 Corresponding to the 24 LCD drive output pins, there are 24 LCD data RAM segments (LCDR00 to LCDR17). Instructions such as MOV LCDR, #I; MOV WR, LCDR; MOV LCDR, WR; and MOV LCDR, ACC are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the segment output pins automatically without program control. When the bit value of the LCD data RAM is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," the LCD is turned off. The contents of the LCD data RAM (LCDR) are sent out through the segment 0 to segment 23 pins by a direct memory access. The relationship between the LCD data RAM and segment/common pins is shown below. LCD data RAM LCDR00 LCDR01 . . . LCDR16 LCDR17 Output pin SEG0 SEG1 . . . SEG22 SEG23 COM3 COM2 COM1 COM0 bit 3 0/1 0/1 bit 2 0/1 0/1 bit 1 0/1 0/1 bit 0 0/1 0/1 . . . . . . . . . . . . 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 - 23 - Publication Release Date: March 1998 Revision A4 W741C250 The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction turns the LCD display off. At initial reset, all the LCD segments are lit. When the initial reset state ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON must be executed. When the drive output pins are used as DC output ports (set by option codes, please refer the user's manual of ASM741S assembler for more detail), CMOS output type or NMOS output type can be selected by executing the instruction MOV LCDM, #I. The relation between the LCD data RAM and segment/common pins is shown below. The data in LCDR00 are transferred to the corresponding segment output port (SEG3 to SEG0) by a direct memory access. The other LCD data RAM segments can be used as normal data RAM to store data. LCD DATA RAM LCDR00 LCDR03−LCDR01 LCDR04 LCDR07−LCDR05 OUTPUT PIN BIT 3 BIT 2 BIT 1 BIT 0 SEG3 SEG7 - SEG2 SEG6 - SEG1 SEG5 - SEG0 SEG4 - . . . . . . . . . . . . . . . SEG23−SEG20 - SEG23 - SEG22 - SEG21 - SEG20 - SEG3−SEG0 SEG7−SEG4 - . . . LCDR14 LCDR17−LCDR15 The relationship between the LCD drive mode and the maximum number of drivable LCD segments is shown below. LCD DRIVE MODE MAX. NUMBER OF DRIVABLE LCD SEGMENTS CONNECTION AT POWER INPUT Static 1/2 bias 1/2 duty 24 (COM1) 48 (COM1−COM2) Connect VDD3, VDD2 to VDD1 Connect VDD3 to VDD2 1/2 bias 1/3 duty 72 (COM1−COM3) Connect VDD3 to VDD2 1/3 bias 1/3 duty 72 (COM1−COM3) - 1/3 bias 1/4 duty 96 (COM1−COM4) - LCD Output Mode Type Flag (LCDM) The LCD output mode type flag is organized as a 6-bit binary register (LCDM.0 to LCDM.5). These bits are used to control the LCD output pin architecture. When the LCD output pins are set to DC output mode by option codes, the architecture of these output pins (segment 0 to segment 23) can be selected as CMOS or NMOS type by the MOV LCDM, #I instruction. The bit descriptions are as follows: LCDM 5 4 3 2 1 0 w w w w w w Note: W means write only. - 24 - W741C250 LCDM.0 = 0 SEG0 to SEG3 work as CMOS output type. = 1 SEG0 to SEG3 work as NMOS output type. LCDM.1 = 0 SEG4 to SEG7 work as CMOS output type. = 1 SEG4 to SEG7 work as NMOS output type. LCDM.2 = 0 SEG8 to SEG11 work as CMOS output type. = 1 SEG8 to SEG11 work as NMOS output type. LCDM.3 = 0 SEG12 to SEG15 work as CMOS output type. = 1 SEG12 to SEG15 work as NMOS output type. LCDM.4 = 0 SEG16 to SEG19 work as CMOS output type. = 1 SEG16 to SEG19 work as NMOS output type. LCDM.5 = 0 SEG20 to SEG23 work as CMOS output type. = 1 SEG20 to SEG23 work as NMOS output type. The output waveforms for the five LCD driving modes are shown below. Static Lighting System (Example) Normal Operating Mode VDD2 VDD1 VSS COM0 VDD2 VDD1 VSS Unlit LCD driver outputs VDD2 VDD1 VSS Lit LCD driver outputs - 25 - Publication Release Date: March 1998 Revision A4 W741C250 1/2 Bias 1/2 Duty Lighting System (Example) Normal Operating Mode VDD2 VDD1 VSS COM0 VDD2 VDD1 VSS COM1 LCD driver outputs for seg. on COM0, COM1 sides being unlit VDD2 VDD1 VSS LCD driver outputs for only seg. on COM0 side being lit VDD2 VDD1 VSS LCD driver outputs for only seg. on COM1 side being lit VDD2 VDD1 VSS LCD driver outputs for seg. on COM0, COM1 sides being lit VDD2 VDD1 VSS - 26 - W741C250 1/2 Bias 1/3 Duty Lighting System (Example) Normal Operating Mode VDD2 VDD1 VSS COM0 COM1 VDD2 VDD1 VSS COM2 VDD2 VDD1 VSS VDD2 VDD1 VSS LCD driver outputs for all seg. on COM0,1,2 sides being unlit LCD driver outputs for only seg. on COM0 side being lit VDD2 VDD1 VSS LCD driver outputs for only seg. on COM1 side being lit VDD2 VDD1 VSS LCD driver outputs for only seg. on COM0,1 sides being lit VDD2 VDD1 VSS LCD driver outputs for only seg. on COM2 side being lit VDD2 VDD1 VSS LCD driver outputs for only seg. on COM0,2 sides being lit VDD2 VDD1 VSS - 27 - Publication Release Date: March 1998 Revision A4 W741C250 1/3 Bias 1/3 Duty Lighting System (Example) Normal Operating Mode VDD3 VDD2 VDD1 VSS COM0 VDD3 VDD2 VDD1 VSS COM1 VDD3 VDD2 VDD1 VSS COM2 VDD3 VDD2 VDD1 VSS LCD driver outputs for all seg. on COM0,1,2 sides being unlit LCD driver outputs for only seg. on COM0 side being lit VDD3 VDD2 VDD1 VSS LCD driver outputs for only seg. on COM1 side being lit VDD3 VDD2 VDD1 VSS LCD driver outputs for seg. on COM0,2 sides being lit VDD3 VDD2 VDD1 VSS LCD driver outputs for seg. on COM1,2 sides being lit VDD3 VDD2 VDD1 VSS LCD driver outputs for seg. on COM0,1,2 sides being lit VDD3 VDD2 VDD1 VSS - 28 - W741C250 1/3 Bias 1/4 Duty Lighting System (Example) Normal Operating Mode VDD3 VDD2 VDD1 VSS COM0 VDD3 VDD2 VDD1 VSS COM1 VDD3 VDD2 VDD1 VSS COM2 VDD3 VDD2 VDD1 VSS COM3 LCD driver outputs for only seg. on COM0 side being lit VDD3 VDD2 VDD1 VSS LCD driver outputs for only seg. on COM1 side being lit VDD3 VDD2 VDD1 VSS LCD driver outputs for seg. on COM0, COM1 sides being lit VDD3 VDD2 VDD1 VSS LCD driver outputs for seg. on COM1, COM2,3 sides being lit VDD3 VDD2 VDD1 VSS - 29 - Publication Release Date: March 1998 Revision A4 W741C250 1/3 Bias 1/4 Duty Normal Lighting System, continued LCD driver outputs for seg. on COM1 COM2 sides being lit VDD3 VDD2 VDD1 VSS LCD driver outputs for seg. on COM0 COM2,3 sides being lit VDD3 VDD2 VDD1 VSS LCD driver outputs for seg. on COM0 COM1,2,3 sides being lit VDD3 VDD2 VDD1 VSS The power connections for each LCD driving mode, which are determined by a mask option, are shown below. 1/2 Bias LCD Configuration Static LCD Configuration DH1 DH1 0.1uF DH1, DH2 floating DH2 DH2 VSS C H I P VSS VDD VDD C H I P VDD VDD 0.1uF VDD1 VDD1 VDD2 VDD2 VDD3 VDD3 VDD1 = 1/2 VDD, VDD2 = VDD3 = VDD VDD1 = VDD2 = VDD3 = VDD - 30 - W741C250 LCD Configuration, continued 1/3 Bias LCD Configuration DH1 0.1uF DH2 VSS C H I P VDD VDD 0.1uF VDD1 VDD2 VDD3 VDD1 = 1/2 VDD, VDD2 = VDD, VDD3 = 3/2 VDD 1/3 Bias LCD Configuration DH1 0.1uF DH2 VSS C H I P VDD VDD 0.1uF VDD1 VDD2 VDD3 VDD1 = 1/3 VDD, VDD2 = 2/3 VDD, VDD3 = VDD - 31 - Publication Release Date: March 1998 Revision A4 W741C250 ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Supply Voltage to Ground Potential -0.3 to +7.0 V Applied Input/Output Voltage -0.3 to +7.0 V 120 mW 0 to +70 °C -55 to +150 °C Power Dissipation Ambient Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC CHARACTERISTICS (VDD−VSS = 3.0V, FOSC. = 32.768 KHz, TA = 25° C; unless otherwise specified) PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Op. Voltage VDD - 2.2 - 5.5 V Op. Current (Crystal type) IOP1 No load (Ext-V) - 8 20 µA Op. Current (RC type) IOP2 No load (Ext-V) - 35 65 µA Hold Current (Crystal type) IHM1 Hold mode No load (Ext-V) - 4 6 µA Hold Current (RC type) IHM2 Hold mode No load (Ext-V) - 16 40 µA Stop Current (Crystal type) ISM1 Stop mode No load (Ext-V) - 0.1 2 µA Stop Current (RC type) ISM2 Stop mode No load (Ext-V) - 0.1 2 µA Input Low Voltage VIL - VSS - 0.3 VDD V Input High Voltage VIH - 0.7 VDD - VDD V MFP Output Low Voltage VML IOL = 3.5 mA - - 0.4 V MFP Output High Voltage VMH IOH = -3.5 mA 2.4 - - V Port RA, RB Output Low Voltage VABL IOL = 2.0 mA - - 0.4 V Port RA, RB Output high Voltage VABH IOH = -2.0 mA 2.4 - - V LCD Supply Current ILCD All Seg. On - - 10 µA SEG0−SEG23 Sink Current (work as LCD output pins) IOL VOL = 0.4V VLCD = 0.0V 0.4 - - µA SEG0−SEG23 Drive Current (work as LCD output pins) IOH VOH = 2.4V VLCD = 3.0V 0.3 - - µA - 32 - W741C250 DC Characteristics, continued PARAMETER SYM. SEG0−SEG23 Output Low Voltage (work as DC output pins) VSL SEG0−SEG23 Output High Voltage (work as DC output pins) CONDITIONS MIN. TYP. MAX. UNIT IOL = 0.6 mA - - 0.4 V VSH IOH = -0.3 µA 2.4 - - V Port RE Sink Current IEL VOL = 0.9V 9 - - mA Port RE Source Current IEH VOH = 2.4V 0.4 1.2 - mA Input Port Pull-up Resistor RCD Port RC, RD 100 350 1000 KΩ INT Pull-up Resistor RINT - 50 250 1000 KΩ RES Pull-up Resistor RRES - 20 100 500 KΩ MIN. TYP. MAX. UNIT RC type - - 4000 Crystal type 1 (Option low-speed type) - 32.768 - Crystal type 2 (Option high-speed type) 400 - 4190 AC CHARACTERISTICS (VDD−VSS = 3.0V, TA = 25° C; unless otherwise specified) PARAMETER Op. Frequency SYM. FOSC CONDITIONS KHz Frequency Deviation by Voltage Drop for RC Oscillator ∆f f f(3V) − f(2.4V) f(3V) - - 10 % Instruction Cycle Time TI One machine cycle - 4/FOSC - mS Reset Active Width TRAW FOSC = 32.768 KHz 1 - - µS Interrupt Active Width TIAW FOSC = 32.768 KHz 1 - - µS - 33 - Publication Release Date: March 1998 Revision A4 W741C250 PAD ASSIGNMENT & POSITIONS 2810 µm 1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 2 46 3 45 44 4 5 6 43 42 Y 7 8 3020 µm 41 40 X (0,0) 9 39 10 11 12 38 13 14 35 15 33 37 36 34 16 32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Note: The chip substrate must be connected to system ground (VSS). PAD NO. PAD NAME X 1 RD2 -912.10 2 RD3 3 Y PAD NO. PAD NAME X 1297.50 11 COM0 -1209.00 -414.00 -1209.00 756.00 12 SEG0 -1209.00 -544.00 RE0 -1209.00 626.00 13 SEG1 -1209.00 -674.00 4 RE1 -1209.00 496.00 14 SEG2 -1209.00 -804.00 5 RE2 -1209.00 366.00 15 SEG3 -1209.00 -934.00 6 RE3 -1209.00 236.00 16 SEG4 -1209.00 -1064.00 7 VSS -1209.00 106.00 17 SEG5 -912.10 -1314.00 8 COM3 -1209.00 -24.00 18 SEG6 -782.10 -1314.00 9 COM2 -1209.00 -154.00 19 SEG7 -652.10 -1314.00 10 COM1 -1209.00 -284.00 20 SEG8 -522.10 -1314.00 - 34 - Y W741C250 Pad positions, continued PAD NO. PAD NAME X 21 SEG9 -392.10 22 SEG10 23 Y PAD NO. PAD NAME X Y -1314.00 41 VDD 1201.50 106.00 -262.10 -1314.00 42 XOUT 1201.50 236.00 SEG11 -132.10 -1314.00 43 XIN 1201.50 366.00 24 SEG12 -2.10 -1314.00 44 RES 1201.50 496.00 25 SEG13 127.90 -1314.00 45 INT 1201.50 626.00 26 SEG14 257.90 -1314.00 46 MFP 1201.50 756.00 27 SEG15 387.90 -1314.00 47 RA0 907.90 1297.50 28 SEG16 517.90 -1314.00 48 RA1 777.90 1297.50 29 SEG17 647.90 -1314.00 49 RA2 647.90 1297.50 30 SEG18 777.90 -1314.00 50 RA3 517.90 1297.50 31 SEG19 907.90 -1314.00 51 RB0 387.90 1297.50 32 SEG20 1201.50 -1064.00 52 RB1 257.90 1297.50 33 SEG21 1201.50 -934.00 53 RB2 127.90 1297.50 34 SEG22 1201.50 -804.00 54 RB3 -2.10 1297.50 35 SEG23 1201.50 -674.00 55 RC0 -132.10 1297.50 36 VDD3 1201.50 -544.00 56 RC1 -262.10 1297.50 37 VDD2 1201.50 -414.00 57 RC2 -392.10 1297.50 38 VDD1 1201.50 -284.00 58 RC3 -522.10 1297.50 39 DH2 1201.50 -154.00 59 RD0 -652.10 1297.50 40 DH1 1201.50 -24.00 60 RD1 -782.10 1297.50 - 35 - Publication Release Date: March 1998 Revision A4 W741C250 TYPICAL APPLICATION CIRCUIT Vcc VDD COM0 RA0 Output Signal RA3 COM3 SEG0 RB0 RB1 RB2 RB3 LCD PANEL (1/3 Bias 1/4 Duty) SEG23 DH1 RC0 RC1 RC2 RC3 DH2 VDD1 VDD2 VDD3 RD0 Connect to capacitor and VDD to generate LCD voltage Vcc RD1 RD2 RD3 INT RE0 RES RE1 RE2 XOUT RE3 or MFP XIN VSS - 36 - Vcc W741C250 INSTRUCTION SET TABLE Symbol Description ACC: Accumulator ACC.n: Accumulator bit n WR: Working Register PAGE: Page Register MR1: Mode Register 1 PM0: Port Mode 0 PM1: Port Mode 1 PM2: Port Mode 2 PSR0: Port Status Register 0 R: Memory (RAM) of address R LCDR: LCD data RAM of address LDR R.n: Memory bit n of address R I: Constant parameter L: Branch or jump address CF: Carry Flag ZF: Zero Flag PC: Program Counter TM0: Timer 0 TM1: Timer 1 IEF.n: Interrupt Enable Flag n HCF.n: HOLD mode release Condition Flag n HEF.n: HOLD mode release Enable Flag n SEF.n: STOP mode wake-up Enable Flag n PEF.n: Port Enable Flag n EVFn: Event Flag n BF: Backup Flag ! =: Not equal &: AND ^: OR - 37 - Publication Release Date: March 1998 Revision A4 W741C250 Symbol Description, continued EX: Exclusive OR ←: Transfer direction, result [PAGE*10H+()]: Contents of address PAGE(bit2, bit1, bit0)*10H+() [P()]: Contents of port P() INSTRUCTION SET TABLE 1 MNEMONIC FUNCTION FLAG AFFECTED CYCLE Arithmetic ADD R, ACC ACC←(R) + (ACC) ZF, CF 1 ADD WR, #I ACC←(WR) + I ZF, CF 1 ADDR R, ACC ACC, R←(R) + (ACC) ZF, CF 1 ADDR WR, #I ACC, WR←(WR) + I ZF, CF 1 ADC R, ACC ACC←(R) + (ACC) + (CF) ZF, CF 1 ADC WR, #I ACC←(WR) + I + (CF) ZF, CF 1 ADCR R, ACC ACC, R←(R) + (ACC) + (CF) ZF, CF 1 ADCR WR, #I ACC, WR←(WR) + I + (CF) ZF, CF 1 ADU R, ACC ACC←(R) + (ACC) ZF 1 ADU WR, #I ACC←(WR) + I ZF 1 ADUR R, ACC ACC, R←(R) + (ACC) ZF 1 ADUR WR, #I ACC, W R←(WR) + I ZF 1 SUB R, ACC ACC←(R) - (ACC) ZF, CF 1 SUB WR, #I ACC←(WR) - I ZF, CF 1 SUBR R, ACC ACC, R←(R) - (ACC) ZF, CF 1 SUBR WR, #I ACC, WR←(WR) - I ZF, CF 1 SBC R, ACC ACC←(R) - (ACC) - (CF) ZF, CF 1 SBC WR, #I ACC←(WR) - I - (CF) ZF, CF 1 SBCR R, ACC ACC, R←(R) - (ACC) - (CF) ZF, CF 1 SBCR WR, #I ACC, WR←(WR) - I - (CF) ZF, CF 1 INC R ACC, R←(R) + 1 ZF, CF 1 DEC R ACC, R←(R) - 1 ZF, CF 1 - 38 - W741C250 Instruction Set Table 1, continued MNEMONIC FUNCTION FLAG AFFECTED CYCLE Logic Operations ANL R, ACC ACC←(R) & (ACC) ZF 1 ANL WR, #I ACC←(WR) & I ZF 1 ANLR R, ACC ACC, R←(R) & (ACC) ZF 1 ANLR WR, R #I ACC, WR←(WR) & I ZF 1 ORL R, ACC ACC←(R) ∧ (ACC) ZF 1 ORL WR, #I ACC←(WR) ∧ I ZF 1 ORLR R, ACC ACC, R←(R) ∧ (ACC) ZF 1 ORLR WR, #I ACC, WR←(WR) ∧ I ZF 1 XRL R, ACC ACC←(R) EX (ACC) ZF 1 XRL WR, #I ACC←(WR) EX I ZF 1 XRLR R, ACC ACC, R←(R) EX (ACC) ZF 1 XRLR WR, #I ACC, WR←(WR) EX I ZF 1 JMP L PC10−PC0←L10−L0 1 JB0 L PC10−PC0←L10−L0; if ACC.0 = "1" 1 JB1 L PC10−PC0←L10−L0; if ACC.1 = "1" 1 JB2 L PC10−PC0←L10−L0; if ACC.2 = "1" 1 JB3 L PC10−PC0←L10−L0; if ACC.3 = "1" 1 JZ L PC10−PC0←L10−L0; if ACC = 0 1 JNZ L PC10−PC0←L10−L0; if ACC ! = 0 1 JC L PC10−PC0←L10−L0; if CF = "1" 1 JNC L PC10−PC0←L10−L0; if CF ! = "1" 1 DSKZ R ACC, R←(R) - 1; skip if ACC = 0 ZF, CF 1 DSKNZ R ACC, R←(R) - 1; skip if ACC ! = 0 ZF, CF 1 SKB0 R Skip if R.0 = "1" 1 SKB1 R Skip if R.1 = "1" 1 SKB2 R Skip if R.2 = "1" 1 SKB3 R Skip if R.3 = "1" 1 Branch - 39 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 1, continued MNEMONIC FUNCTION FLAG AFFECTED CYCLE Data Move MOV WR, R WR←(R) 1 MOV R, WR R←(WR) 1 MOVA WR, R ACC, WR←(R) ZF 1 MOVA R, WR ACC, R←(WR) ZF 1 MOV R, ACC R←(ACC) MOV ACC, R ACC←(R) MOV R, #I R←I 1 MOV WR, @R WR←[PR (bit2, bit1, bit0) × 10H + (R)] 2 MOV @R, WR [PR (bit2, bit1, bit0) × 10H +(R)]←WR 2 MOV TABH, R TAB High addresss ← R 1 MOV TABL, R TAB Low addresss ← R 1 MOVC R R←[ TAB × 10H + (ACC)] 2 MOVC WR, #I WR ← [(I6 ~ I0) × 10H + (ACC)] 2 1 ZF 1 Input & Output MOVA R, RA ACC, R←[RA] ZF 1 MOVA R, RB ACC, R←[RB] ZF 1 MOVA R, RC ACC, R←[RC] ZF 1 MOVA R, RD ACC, R←[RD] ZF 1 MOV RA, R [RA]←(R) 1 MOV RB, R [RB]←(R) 1 MOV RE, R [RT]←(R) 1 MOV MFP, #I [MFP]← I 1 Flag & Register MOVA R, PAGE ACC, R←PAGE (Page Register) MOV PAGE, R PAGE←(R) 1 MOV PAGE, #I PAGE←I 1 MOV MR0, #I MR0←I 1 MOV MR1, #I MR1←I 1 - 40 - ZF 1 W741C250 Instruction Set Table 1, continued MNEMONIC FUNCTION FLAG AFFECTED CYCLE MOVA R, CF ACC.0, R.0←CF ZF 1 MOV CF, R CF←(R.0) CF 1 MOVA R, HCFL ACC, R←HCF0−HCF3 ZF 1 MOVA R, HCFH ACC, R←HCF4−HCF7 ZF 1 CLR PMF, #I Clear Parameter Flag if In = 1 1 SET PMF, #I Set Parameter Flag if In = 1 1 MOV PM0, #I Port Mode 0← I 1 MOV PM1, #I Port Mode 1← I 1 MOV PM2, #I Port Mode 2← I 1 CLR EVF, #I Clear Event Flag if In = 1 1 MOV PEF, #I Set/Reset Port Enable Flag 1 MOV IEF, #I Set/Reset Interrupt Enable Flag 1 MOV HEF, #I Set/Reset HOLD mode release Enable Flag 1 MOV SEF, #I Set/Reset STOP mode wake-up Enable Flag for RC port 1 MOVA R, PSR0 ACC, R←Port Status Register 0 CLR PSR0 Clear Port Status Register 0 SET CF Set Carry Flag CF 1 CLR CF Clear Carry Flag CF 1 CLR DIVR0 Clear last 4 bits of Divider 0 1 CLR WDT Clear Watchdog Timer 1 ZF 1 1 Shift & Rotate SHRC R ACC.n, R.n←(R.n+1); ZF, CF 1 ZF, CF 1 ZF, CF 1 ZF, CF 1 ACC.3, R.3←0; CF←R.0 RRC R ACC.n, R.n←(R.n+1); ACC.3, R.3←CF; CF←R.0 SHLC R ACC.n, R.n←(R.n-1); ACC.0, R.0←0; CF←R.3 RLC R ACC.n, R.n←(R.n-1); ACC.0, R.0←CF; CF←R.3 - 41 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 1, continued MNEMONIC FUNCTION FLAG AFFECTED CYCLE LCD MOV LCDR, #I LCDR← I 1 MOV WR, LCDR WR←(LCDR) 1 MOV LCDR, WR LCDR←(WR) 1 MOV LCDR, ACC LCDR←(ACC) 1 MOV LCDM, #I Select LCD output mode type 1 LCDON LCD ON 1 LCDOFF LCD OFF 1 Timer MOV TM0H, R Timer 0 High register ← R 1 MOV TM0L, R Timer 0 Low register ← R 1 MOV TM0, #I Timer 0 set 1 MOV TM1H, R Timer 1 High register ← R 1 MOV TM1L, R Timer 1 Low register ← R 1 MOV TM1, #I Timer 1 set 1 L STACK ← (PC)+1; PC10−PC0 ← L10−L0 1 (PC)←STACK 1 HOLD Enter Hold mode 1 STOP Enter Stop mode 1 NOP No Operation 1 Subroutine CALL RTN Other EN INT Enable Interrupt Function 1 DIS INT Disable Interrupt Function 1 - 42 - W741C250 INSTRUCTION SET TABLE 2 ADC R, ACC Add R to ACC with CF Machine Code: 0 0 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC ← (R) + (ACC) + (CF) Description: The contents of the data memory location addressed by R6 to R0, ACC, and CF are binary added and the result is loaded into the ACC. Flag Affected: CF & ZF ADC Add immediate data to WR with CF WR, #I Machine Code: 0 0 0 0 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC ← (WR) + I + (CF) Description: The contents of the Working Register (WR), I, and CF are binary added and the result is loaded into the ACC. Flag Affected: CF & ZF ADCR R, ACC Add R to ACC with CF Machine Code: 0 0 0 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) + (ACC) + (CF) Description: The contents of the data memory location addressed by R6 to R0, ACC, and CF are binary added and the result is placed in the ACC and the data memory. Flag Affected: CF & ZF - 43 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued ADCR WR, #I Add immediate data to WR with CF Machine Code: 0 0 0 0 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC, WR ← (WR) + I + (CF) Description: The contents of the Working Register (WR), I, CF are binary added and the result is placed in the ACC and the WR. Flag Affected: CF & ZF ADD Add R to ACC R, ACC Machine Code: 0 0 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC ← (R) + (ACC) Description: The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is loaded into the ACC. Flag Affected: CF & ZF ADD Add immediate data to WR WR, #I Machine Code: 0 0 0 1 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC ← (WR) + I Description: The contents of the Working Register (WR) and the immediate data I are binary added and the result is loaded into the ACC. Flag Affected: CF & ZF - 44 - W741C250 Instruction Set Table 2, continued ADDR R, ACC Add R to ACC Machine Code: 0 0 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) + (ACC) Description: The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is placed in the ACC and the data memory. Flag Affected: CF & ZF ADDR Add immediate data to WR WR, #I Machine Code: 0 0 0 1 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC, WR ← (WR) + I Description: The contents of the Working Register (WR) and the immediate data I are binary added and the result is placed in the ACC and the WR. Flag Affected: CF & ZF ADU Add R to ACC and Carry Flag unchanged R, ACC Machine Code: 0 0 1 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC ← (R) + (ACC) Description: The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is loaded into the ACC. Flag Affected: ZF - 45 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued ADU WR, #I Add immediate data to WR and Carry Flag unchanged 0 Machine Code: 0 1 0 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC ← (WR) + I Description: The contents of the Working Register (WR) and the immediate data I are binary added and the result is loaded into the ACC. Flag Affected: ADUR R, ACC ZF Add R to ACC and Carry Flag unchanged Machine Code: 0 0 1 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) + (ACC) Description: The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is placed in the ACC and the data memory. Flag Affected: ZF ADUR Add immediate data to WR and Carry Flag unchanged WR, #I Machine Code: 0 0 1 0 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC, WR ← (WR) + I Description: The contents of the Working Register (WR) and the immediate data I are binary added and the result is placed in the WR and the ACC. Flag Affected: ZF - 46 - W741C250 Instruction Set Table 2, continued ANL R, ACC And R to ACC Machine Code: 0 0 1 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC ← (R) & (ACC) Description: The contents of the data memory location addressed by R6 to R0 and the ACC are ANDed and the result is loaded into the ACC. Flag Affected: ZF ANL And immediate data to WR WR, #I Machine Code: 0 0 1 0 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC ← (WR) & I Description: The contents of the Working Register (WR) and the immediate data I are ANDed and the result is loaded into the ACC. Flag Affected: ZF ANLR R, ACC And R to ACC Machine Code: 0 0 1 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) & (ACC) Description: The contents of the data memory location addressed by R6 to R0 and the ACC are ANDed and the result is placed in the data memory and the ACC. Flag Affected: ZF - 47 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued ANLR WR, #I And immediate data to WR Machine Code: 0 0 1 0 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC, WR ← (WR) & I Description: The contents of the Working Register (WR) and the immediate data I are ANDed and the result is placed in the WR and the ACC. Flag Affected: ZF CALL Call subroutine L Machine Code: 0 1 1 0 0 Machine Cycle: 1 Operation: STACK ← (PC)+1; L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 PC10−PC0 ← L10−L0 Description: The next program counter (PC10 to PC0) is saved in the STACK and then the direct address (L10 to L0) is loaded into the program counter. A subroutine is called. CLR CF Clear CF Machine Code: 0 1 0 1 0 0 Machine Cycle: 1 Operation: Clear CF Description: Clear Carry Flag to 0. Flag Affected: CF 0 0 - 48 - 0 0 0 0 0 0 0 0 W741C250 Instruction Set Table 2, continued CLR DIVR0 Reset the last 4 bits of the DIVideR0 Machine Code: 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 Machine Cycle: 1 Operation: Reset the last 4 bits of Divider 0 Description: When this instruction is executed, the last 4 bits of Divider 0 (14 bits) are reset. CLR Clear EVent Flag EVF, #I Machine Code: 0 1 0 0 0 0 0 0 I7 I6 I5 I4 I3 I2 I1 I0 Machine Cycle: 1 Operation: Clear event flag Description: The condition corresponding to the data specified by I7 to I0 is controlled. I0 to I8 Mode after execution of instruction I0 = 1 EVF0 caused by overflow from Divider 0 is reset. I1 = 1 EVF1 caused by underflow from Timer 0 is reset. I2 = 1 EVF2 caused by signal change on port RC is reset. I3 = 1 Reserved I4 = 1 EVF4 caused by falling edge signal on the INT pin is reset. I5, I6 Reserved I7 = 1 EVF7 caused by underflow from Timer 1 is reset. - 49 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued CLR PMF, #I Clear ParaMeter Flag Machine Code: Machine Cycle: Operation: Description: 0 0 0 1 0 1 1 0 1 0 0 0 I3 I2 I1 I0 1 Clear Parameter Flag Description of each flag: I0, I1, I2 : Reserved I3 = 1 : The input clock of the watchdog timer is Fosc/1024. CLR PSR0 Clear Port Status Register 0 (RC port signal change flag) Machine Code: 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Machine Cycle: 1 Operation: Clear Port Status Register 0 (RC port signal change flag) Description: When this instruction is executed, the RC port signal change flag (PSR0) is cleared. CLR Reset the last 4 bits of the WatchDog Timer WDT Machine Code: 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 Machine Cycle: 1 Operation: Reset the last 4 bits of the watchdog timer Description: When this instruction is executed, the last 4 bits of the watchdog timer are reset. - 50 - W741C250 Instruction Set Table 2, continued DEC R Decrement R content Machine Code: 0 1 0 0 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) - 1 Description: Decrement the data memory content and load result into the ACC and the data memory. Flag Affected: CF & ZF DIS Disable interrupt function INT Machine Code: 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 Machine Cycle: 1 Operation: Disable interrupt function Description: Interrupt function is inhibited by executing this instruction. DSKNZ Decrement R content then skip if ACC ! = 0 R Machine Code: 0 1 0 0 1 0 0 Machine Cycle: 1 Operation: ACC, R ← (R) - 1; PC ← (PC) + 2 if ACC ! = 0 Description: Flag Affected: 0 1 0 R6 R5 R4 R3 R2 R1 R0 Decrement the data memory content and load result into the ACC and the data memory. If ACC ! = 0, the program counter is incremented by 2 and produces a skip. CF & ZF - 51 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued DSKZ R Decrement R content then skip if ACC is zero Machine Code: 0 1 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) - 1; PC ← (PC) + 2 if ACC = 0 Description: Decrement the data memory content and load result into the ACC and the data memory. If ACC = 0, the program counter is incremented by 2 and produces a skip. Flag Affected: CF & ZF EN Enable interrupt function INT Machine Code: 0 1 0 1 0 0 0 0 1 1 0 0 Machine Cycle: 1 Operation: Enable interrupt function Description: This instruction enables the interrupt function. HOLD Enter the HOLD mode Machine Code: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Machine Cycle: 1 Operation: Enter the HOLD mode Description: The following two conditions cause the HOLD mode to be released. (1) An interrupt is accepted. (2) The HOLD release condition specified by the HEF is met. In HOLD mode, when an interrupt is accepted the HOLD mode will be released and the interrupt service routine will be executed. After completing the interrupt service routine by executing the RTN instruction, the µC will enter HOLD mode again. - 52 - W741C250 Instruction Set Table 2, continued INC R Increment R content Machine Code: 0 1 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) + 1 Description: Increment the data memory content and load the result into the ACC and the data memory. Flag Affected: CF & ZF JB0 Jump when bit 0 of ACC is "1" L Machine Code: 1 0 0 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Cycle: 1 Operation: PC10−PC0 ← L10−L0; if ACC.0 = "1" Description: If bit 0 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 0 of the ACC is "0," the program counter (PC) is incremented. JB1 Jump when bit 1 of ACC is "1" L Machine Code: 1 0 0 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Cycle: 1 Operation: PC10−PC0 ← L10−L0; if ACC.1 = "1" Description: If bit 1 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 1 of the ACC is "0," the program counter (PC) is incremented. - 53 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued JB2 L Jump when bit 2 of ACC is "1" Machine Code: 1 0 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Cycle: 1 Operation: PC10−PC0 ← L10−L0; if ACC.2 = "1" Description: If bit 2 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 2 of the ACC is "0," the program counter (PC) is incremented. JB3 Jump when bit 3 of ACC is "1" L Machine Code: 1 0 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Cycle: 1 Operation: PC10−PC0 ← L10−L0; if ACC.3 = "1" Description: If bit 3 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 3 of the ACC is "0," the program counter (PC) is incremented. JC Jump when CF is "1" L Machine Code: 1 1 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Cycle: 1 Operation: PC10−PC0 ← L10−L0; if CF = "1" Description: If CF is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If the CF is "0," the program counter (PC) is incremented. - 54 - W741C250 Instruction Set Table 2, continued JMP L Jump absolutely Machine Code: 0 1 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Cycle: 1 Operation: PC10−PC0 ← L10−L0 Description: PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and an unconditional jump occurs. JNC Jump when CF is not "1" L Machine Code: 1 1 0 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Cycle: 1 Operation: PC10−PC0 ← L10−L0; if CF = "0" Description: If CF is "0," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If CF is "1," the program counter (PC) is incremented. JNZ Jump when ACC is not zero L Machine Code: 1 1 0 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Cycle: 1 Operation: PC10−PC0 ← L10−L0; if ACC ! = 0 Description: If the ACC is not zero, PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If the ACC is zero, the program counter (PC) is incremented. - 55 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued JZ L Jump when ACC is zero Machine Code: 1 1 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Machine Cycle: 1 Operation: PC10−PC0 ← L10−L0; if ACC = 0 Description: If the ACC is zero, PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If the ACC is not zero, the program counter (PC) is incremented. LCDON LCD ON Machine Code: 0 0 0 0 0 0 Machine Cycle: 1 Operation: LCD ON Description: Turn on LCD display. LCDOFF LCD OFF Machine Code: 0 0 0 0 0 0 Machine Cycle: 1 Operation: LCD OFF Description: Turn off LCD display. 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 - 56 - W741C250 Instruction Set Table 2, continued MOV ACC, R Move R content to ACC Machine Code: 0 1 0 0 1 1 1 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC ← (R) Description: The contents of the data memory location addressed by R6 to R0 are loaded into the ACC. Flag Affected: ZF MOV Move R.0 content to CF CF, R Machine Code: 0 1 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: CF ← (R.0) Description: The bit 0 content of the data memory location addressed by R6 to R0 is loaded into CF. Flag Affected: CF - 57 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued MOV HEF, #I Set/Reset Hold mode release Enable Flag Machine Code: 0 1 0 0 0 0 0 1 I7 I6 Machine Cycle: 1 Operation: Hold mode release enable flag control Description: I0 to I7 I5 I4 I3 I2 I1 I0 Operation I0 = 1 HEF0 is set so that overflow from Divider 0 will cause the HOLD mode to be released. I1 = 1 HEF1 is set so that underflow from Timer 0 will cause the HOLD mode to be released. I2 = 1 HEF2 is set so that signal change on port RC will cause the HOLD mode to be released. I3 = 1 Reserved I4 = 1 HEF4 is set so that the falling edge signal on the INT pin will cause the HOLD mode to be released. I5 & I6 I7 = 1 Reserved HEF7 is set so that underflow from Timer 1 will cause the HOLD mode to be released. - 58 - W741C250 Instruction Set Table 2, continued MOV IEF, #I Set/Reset Interrupt Enable Flag Machine Code: 0 1 0 1 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0 Machine Cycle: 1 Operation: Interrupt Enable flag Control Description: The interrupt enable flag corresponding to the data specified by I7−I0 is controlled: I0 to I5 Operation I0 = 1 The IEF0 is set so that interrupt 0 (overflow from Divider 0) is accepted. I1 = 1 The IEF1 is set so that interrupt 1 (underflow from Timer 0) is accepted. I2 = 1 The IEF2 is set so that interrupt 2 (signal change on port RC) is accepted. I3 = 1 Reserved The IEF4 is set so that interrupt 4 (falling edge signal on I4 = 1 MOV LCDM, #I the INT pin) is accepted. I5 & I6 Reserved I7 = 1 The IEF7 is set so that interrupt 7 (underflow from Timer 1) is accepted. Select LCD output Mode type Machine Code: 0 0 0 0 0 0 1 1 0 0 I5 I4 I3 I2 I1 I0 Machine Cycle: 1 Operation: Select LCD output mode type Description: When LCD output pins are set to DC output mode, user can select CMOS or NMOS as output type. I0−I5 = 0 => CMOS type; I0−I5 = 1 => NMOS type - 59 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued MOV LCDR, ACC Move ACC content to LCDR Machine Code: 0 0 0 0 0 1 1 D4 D3 D2 D1 D0 0 0 0 0 Machine Cycle: 1 Operation: LCDR ← (ACC) Description: The contents of the ACC are loaded to the LCD data RAM (LCDR) location addressed by D4 to D0. MOV LCDR, WR Load WR content to LCDR Machine Code: 0 1 0 0 0 1 0 D4 D3 D2 D1 D0 W3 W2 W1 W0 Machine Cycle: 1 Operation: LCDR ← (WR) Description: The contents of the WR are loaded to the LCD data RAM (LCDR) location addressed by D4 to D0. MOV Load immediate data to LCDR LCDR, #I Machine Code: 0 0 0 0 0 1 0 D4 D3 D2 D1 D0 I3 I2 I1 I0 Machine Cycle: 1 Operation: LCDR ← I Description: The immediate data I are loaded to the LCD data RAM (LCDR) location addressed by D4 to D0. - 60 - W741C250 Instruction Set Table 2, continued MOV MFP, #I Modulation Frequency Pulse generator Machine Code: 0 0 0 1 0 0 1 0 I7 I6 I5 I4 I3 I2 I1 I0 Machine Cycle: 1 Operation: [MFP] ← I Description: If the bit 2 of MR1 is "0," the waveform specified by I7 to I0 is delivered at the MFP output pin (MFP). The relationship between the waveform and immediate data I is as follows: MOV MR0, #I I5~I0 I0 = 1 I1 = 1 I2 = 1 I3 = 1 Signal Fosc 256 Fosc 512 Fosc 4096 Fosc 8192 I7 I6 Signal 0 0 Low 0 1 High 1 0 Fosc/16 1 1 Fosc/8 I4 = 1 Fosc 16384 I5 = 1 Fosc 32768 Load immediate data to Mode Register 0 (MR0) Machine Code: 0 0 0 1 0 0 1 1 1 0 0 Machine Cycle: 1 Operation: MR0 ← I Description: The immediate data I are loaded to the MR0. 0 I3 I2 I1 I0 MR0 bits description: bit 0 = 0 The fundamental frequency of Timer 0 is Fosc/4 = 1 The fundamental frequency of Timer 0 is Fosc/1024 bit 1 Reserved bit 2 Reserved bit 3 = 0 Timer 0 stop down-counting = 1 Timer 0 start down-counting - 61 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued MOV MR1, #I Load immediate data to Mode Register 1 (MR1) Machine Code: 0 0 0 1 0 0 1 1 0 0 0 Machine Cycle: 1 Operation: MR1 ← I Description: The immediate data I are loaded to the MR1. 0 I3 I2 I1 I0 MR1 bit description: MOV PAGE, #I bit0 = 0 The internal fundamental frequency of Timer 1 is Fosc = 1 The internal fundamental frequency of Timer 1 is Fosc/64 bit1 = 0 The fundamental frequency source of Timer 1 is internal clock = 1 The fundamental frequency source of Timer 1 is external clock via RC.0 input pin bit2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin = 1 The specified frequency of the Timer 1 is delivered at the MFP output pin bit3 = 0 Timer 1 stop down-counting = 1 Timer 1 start down-counting Load immediate data to Page Register Machine Code: 0 1 0 1 0 1 1 0 1 0 0 Machine Cycle: 1 Operation: Page Register ← I Description: The immediate data I are loaded to the PR. 0 I3 I2 I1 I0 Bit 3 is reserved. Bit 0, bit 1, and bit 2 indirect addressing mode preselect bits: - 62 - W741C250 Instruction Set Table 2, continued MOV PEF, #I bit2 bit1 bit0 0 0 0 = Page 0 (00H to 0FH) 0 0 1 = Page 1 (10H to 1FH) 0 1 0 = Page 2 (20H to 2FH) 0 1 1 = Page 3 (30H to 3FH) 1 0 0 = Page 4 (40H to 4FH) 1 0 1 = Page 5 (50H to 5FH) 1 1 0 = Page 6 (60H to 6FH) 1 1 1 = Page 7 (70H to 7FH) Set/Reset Port Enable Flag Machine Code: 0 1 0 0 0 0 1 1 0 0 0 0 I3 I2 I1 I0 Machine Cycle: 1 Operation: Port enable flag control Description: The data specified by I can cause HOLD mode to be released or an interrupt to occur. The signal change on port RC is specified. I0 to I3 Signal change at port RC I0 = 1 RC0 I1 = 1 RC1 I2 = 1 RC2 I3 = 1 RC3 - 63 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued MOV PM0, #I Set/Reset Port Mode 0 register Machine Code: Machine Cycle: Operation: Description: 0 1 0 1 0 0 1 1 0 0 0 0 I3 I2 I1 I0 1 Set/Reset Port mode 0 register I0 = 0: RA port is CMOS type; I0 = 1: RA port is NMOS type. I1 = 0: RB port is CMOS type; I1 = 1: RB port is NMOS type. I2 = 0: RC port pull-high resistor is disabled; I2 = 1: RC port pull-high resistor is enabled. I3 = 0: RD port pull-high resistor is disabled; I3 = 1: RD port pull-high resistor is enabled. MOV PM1, #I RA port independent Input/Output control Machine Code: 0 1 0 1 0 1 1 1 0 0 0 0 I3 I2 Machine Cycle: 1 Operation: Input/output control of 4 RA port pins is independent. Description: I0 = 0: RA.0 is output pin; I0 = 1: RA.0 is input pin. I1 = 0: RA.1 is output pin; I1 = 1: RA.1 is input pin. I2 = 0: RA.2 is output pin; I2 = 1: RA.2 is input pin. I3 = 0: RA.3 is output pin; I3 = 1: RA.3 is input pin. Default condition RA port is input mode (PM1 = 1111B). - 64 - I1 I0 W741C250 Instruction Set Table 2, continued MOV PM2, #I RB port independent Input/Output control Machine Code: 0 1 0 1 0 1 1 1 1 0 0 0 I3 I2 Machine Cycle: 1 Operation: Input/output control of 4 RB port pins is independent. Description: I0 = 0: RB.0 is output pin; I0 = 1: RB.0 is input pin. I1 = 0: RB.1 is output pin; I1 = 1: RB.1 is input pin. I2 = 0: RB.2 is output pin; I2 = 1: RB.2 is input pin. I3 = 0: RB.3 is output pin; I3 = 1: RB.3 is input pin. I1 I0 Default condition RB port is input mode (PM2 = 1111B). MOV R, ACC Move ACC content to R Machine Code: 0 1 0 1 1 0 0 1 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: R ← (ACC) Description: The contents of the ACC are loaded to the data memory location addressed by R6 to R0. MOVA R, RA Input RA port data to ACC & R Machine Code: 0 1 0 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC , R ← [RA] Description: The data on port RA are loaded into the data memory location addressed by R6 to R0 and the ACC. Flag Affected: ZF - 65 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued MOVA R, RB Input RB port data to ACC & R Machine Code: 0 1 0 1 1 0 1 1 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC , R ← [RB] Description: The data on port RB are loaded into the data memory location addressed by R6 to R0 and the ACC. Flag Affected: ZF MOVA R, RC Input RC port data to ACC & R Machine Code: 0 1 0 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC , R ← [RC] Description: The input data on input port RC are loaded into the data memory location addressed by R6 to R0 and the ACC. Flag Affected: ZF MOVA R, RD Input RD port data to ACC & R Machine Code: Machine Cycle: Operation: 0 1 0 0 1 0 1 1 1 R6 R5 R4 R3 R2 R1 R0 1 ACC , R ← [RD] Description: The input data on input port RD are loaded into the data memory location addressed by R6 to R0 and the ACC. Flag Affected: ZF - 66 - W741C250 Instruction Set Table 2, continued MOV R, WR Move WR content to R Machine Code: Machine Cycle: Operation: 1 1 1 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 1 R ← (WR) Description: The contents of the WR are loaded to the data memory location addressed by R6 to R0. MOV R, #I Load immediate data to R Machine Code: Machine Cycle: Operation: Description: MOV RA, R 1 0 1 1 1 I3 I2 I1 I0 R6 R5 R4 R3 R2 R1 R0 1 R←I The immediate data I are loaded to the data memory location addressed by R6 to R0. Output R content to RA port Machine Code: 0 1 0 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: [RA] ← (R) Description: The data in the data memory location addressed by R6 to R0 are output to port RA. - 67 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued MOV RB, R Output R content to RB port Machine Code: 0 1 0 1 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: [RB] ← (R) Description: The contents of the data memory location addressed by R6 to R0 are output to port RB. MOV Output R content to port RE RE, R Machine Code: 0 1 0 1 1 1 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: [RE] ← (R) Description: The contents of the data memory location addressed by R6 to R0 are output to port RE. MOV SEF, #I Set/Reset STOP mode wake-up Enable Flag for port RC Machine Code: 0 1 0 1 0 0 1 0 0 0 0 0 I3 I2 I1 I0 Machine Cycle: 1 Operation: Set/reset STOP mode wake-up enable flag for port RC Description: The data specified by I cause a wake-up from the STOP mode. The fallingedge signal on port RC can be specified independently. I0 to I3 Falling edge signal on port RC I0 = 1 RC0 I1 = 1 RC1 I2 = 1 RC2 I3 = 1 RC3 - 68 - W741C250 Instruction Set Table 2, continued MOV TM0, #I Timer 0 set 0 Machine Code: 0 0 1 0 0 0 0 I7 I6 I5 I4 I3 I2 I1 I0 Machine Cycle: 1 Operation: Timer 0 set Description: The data specified by I7 to I0 is loaded to the Timer 0 to start the timer. MOV TM0L, R Move R contents to TM0L 0 Machine Code: 0 0 1 0 1 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: TM0L ← (R) Description: The contents of the data memory location addressed by R6 to R0 are loaded into the TM0L. MOV TM0H, R Move R contents to TM0H 0 Machine code: 0 0 1 0 1 0 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: TM0H ← (R) Description: The contents of the data memory location addressed by R6 to R0 are loaded into the TM0H. MOV TM1, #I Timer 1 set 0 Machine Code: 0 0 1 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0 Machine Cycle: 1 Operation: Timer 1 set Description: The data specified by I7 to I0 is loaded to the Timer 1 to start the timer. - 69 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued MOV TM1L, R Move R contents to TM1L Machine Code: Machine Cycle: Operation: Description: MOV TM1H, R 0 Operation: Description: MOV WR, LCDR 0 1 0 1 0 1 0 R6 R5 R4 R3 R2 R1 R0 1 TM1L ← (R) The contents of the data memory location addressed by R6 to R0 are loaded into the TM1L. Move R contents to TM1H Machine code: Machine Cycle: 0 0 0 0 1 0 1 0 1 1 R6 R5 R4 R3 R2 R1 R0 1 TM1H ← (R) The contents of the data memory location addressed by R6 to R0 are loaded into the TM1H. Load LCDR content to WR Machine Code: 0 1 0 0 0 1 1 D4 D3 D2 D1 D0 W3 W2 W1 W0 Machine Cycle: 1 Operation: WR ← (LCDR) Description: The contents of the LCD data RAM location addressed by D4 to D0 are loaded to the WR. MOV Move R content to WR WR, R Machine Code: 1 1 1 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: WR ← (R) Description: The contents of the data memory location addressed by R6 to R0 are loaded to the WR. - 70 - W741C250 Instruction Set Table 2, continued MOV WR, @R Indirect load from R to WR Machine Code: 1 1 0 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 2 Operation: WR ← [PR (bit2, bit1, bit0) × 10H + (R)] Description: The data memory contents of address [PR (bit2, bit1, bit0) × 10H + (R)] are loaded to the WR. MOV Indirect load from WR to R @R, WR Machine Code: 1 1 0 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 2 Operation: [PR (bit2, bit1, bit0) × 10H + (R)] ← WR Description: The contents of the WR are loaded to the data memory location addressed by [PR (bit2, bit1, bit0) × 10H + (R)]. MOV PAGE, R Move R content to Page Register Machine Code: 0 1 0 1 1 1 1 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: PR ← (R) Description: The contents of the data memory location addressed by R6 to R0 are loaded to the PR. - 71 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued MOVA R, CF Move CF content to ACC.0 & R.0 Machine Code: 0 1 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC.0, R.0 ← (CF) Description: The content of CF is loaded to bit 0 of the data memory location addressed by R6 to R0 and the ACC. The other bits of the data memory and ACC are reset to "0." Flag Affected: ZF MOVA R, HCFH Move HCF4−7 to ACC & R Machine Code: 0 1 0 0 1 0 0 1 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← HCF4−7 Description: The contents of HCF bit 4 to bit 7 (HCF4 to HCF7) are loaded to the data memory location addressed by R6 to R0 and the ACC. The ACC contents and the meaning of the bits after execution of this instruction are as follows: Flag Affected: Bit 0 HCF4: "1" when the HOLD mode is released by a falling signal on the INT pin. Bit 1 HCF5: "1" when the HOLD mode is released by underflow from Timer 1. Bit 2 Reserved. Bit 3 Reserved. ZF - 72 - W741C250 Instruction Set Table 2, continued MOVA R, HCFL Move HCF0−3 to ACC & R Machine Code: 0 1 0 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← HCF0−3 Description: The contents of HCF bit 0 to bit 3 (HCF0 to HCF3) are loaded to the data memory location addressed by R6 to R0 and the ACC. The ACC contents and the meaning of the bits after execution of this instruction are as follows: Bit 0 HCF0: "1" when the HOLD mode is released by overflow from Divider 0. Bit 1 HCF1: "1" when the HOLD mode is released by underflow from Timer 0. Bit 2 HCF2: "1" when the HOLD mode is released by a signal change on port RC. Bit 3 Reserved Flag Affected: ZF MOVA R, PAGE Move Page Register content to ACC & R Machine Code: 0 1 0 1 1 1 1 1 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC , R ← (Page Register) Description: The contents of the Page Register (PR) are loaded to the data memory location addressed by R6 to R0 and the ACC. Flag Affected: ZF - 73 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued MOVA R, PSR0 Move Port Status Register 0 content to ACC & R Machine Code: 0 1 0 0 1 1 1 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← RC port signal change flag (PSR0) Description: The contents of the RC port signal change flag (PSR0) are loaded to the data memory location addressed by R6 to R0 and the ACC. When the signal changes on any pin of the RC port, the corresponding signal change flag should be set to 1. Otherwise, it should be 0. Flag Affected: ZF MOVA Move WR content to ACC & R R, WR Machine Code: 0 1 1 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (WR) Description: The contents of the WR are loaded to the ACC and the data memory location addressed by R6 to R0. Flag Affected: ZF MOVA Move R content to ACC & WR WR, R Machine Code: 0 1 1 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, WR ← (R) Description: The contents of the data memory location addressed by R6 to R0 are loaded to the WR and the ACC. Flag Affected: ZF - 74 - W741C250 Instruction Set Table 2, continued MOVC R Move look-up table ROM addressed by TABL and TABH to R Machine code: Machine Cycle: Operation: Description: MOVC WR, #I 1 0 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 2 WR ← [((TABH) × 100H + (TABL)) × 10H + ACC ] The contents of the look-up table ROM location addressed by TABH, TABL and ACC are loaded to R. Move look-up table ROM addressed by #I and ACC to WR Machine code: 1 0 1 0 1 W3 W2 W1 W0 I6 I5 I4 I3 I2 I1 I0 Machine Cycle: 2 Operation: WR ← [(I6 ~ I0) × 10H + (ACC)] Description: The contents of the look-up table ROM location addressed by I6 to I0 and the ACC are loaded to R. NOP No Operation Machine Code: 0 0 0 Machine Cycle: 1 Operation: No Operation 0 0 0 0 0 - 75 - 0 0 0 0 0 0 0 0 Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued ORL R, ACC OR R to ACC Machine Code: 0 0 1 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC ← (R) ∧ (ACC) Description: The contents of the data memory location addressed by R6 to R0 and the ACC are ORed and the result is loaded into the ACC. Flag Affected: ZF ORL OR immediate data to WR WR , #I Machine Code: 0 0 1 1 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC ← (WR) ∧ I Description: The contents of the Working Register (WR) and the immediate data I are ORed and the result is loaded into the ACC. Flag Affected: ZF ORLR R, ACC OR R to ACC Machine Code: 0 0 1 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) ∧ (ACC) Description: The contents of the data memory location addressed by R6 to R0 and the ACC are ORed and the result is placed in the data memory and the ACC. Flag Affected: ZF - 76 - W741C250 Instruction Set Table 2, continued ORLR WR , #I OR immediate data to WR Machine Code: 0 0 1 1 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC, WR ← (WR) ∧ I Description: The contents of the Working Register (WR) and the immediate data I are ORed and the result is placed in the WR and the ACC. Flag Affected: ZF RLC Rotate Left R with CF R Machine Code: 0 1 0 0 1 1 0 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC.n, R.n ← R.n-1; ACC.0, R.0 ← CF; CF ← R.3 Description: The contents of the ACC and the data memory location addressed by R6 to R0 are rotated left one bit, bit 3 is rotated into CF, and CF rotated into bit 0 (LSB). The same contents are loaded into the ACC. Flag Affected: CF & ZF RRC Rotate Right R with CF R Machine Code: 0 1 0 0 1 1 0 1 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC.n, R.n ← R.n+1; ACC.3, R.3 ← CF; CF ← R.0 Description: The contents of the ACC and the data memory location addressed by R6 to R0 are rotated right one bit, bit 0 is rotated into CF, and CF is rotated into bit 3 (MSB). The same contents are loaded into the ACC. Flag Affected: CF & ZF - 77 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued RTN Return from subroutine Machine Code: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Machine Cycle: 1 Operation: (PC) ← STACK Description: The program counter (PC10 to PC0) is restored from the stack. A return from a subroutine occurs. SBC Subtract ACC from R with Borrow R, ACC Machine Code: 0 0 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC ← (R) - (ACC) - (CF) Description: The contents of the ACC and CF are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is loaded into the ACC. Flag Affected: SBC WR, #I CF & ZF Subtract immediate data from WR with Borrow Machine Code: 0 0 0 0 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC ← (WR) - I - (CF) Description: The immediate data I and CF are binary subtracted from the contents of the WR and the result is loaded into the ACC. Flag Affected: CF & ZF - 78 - W741C250 Instruction Set Table 2, continued SBCR R, ACC Subtract ACC from R with Borrow Machine Code: 0 0 0 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) - (ACC) - (CF) Description: The contents of the ACC and CF are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is placed in the ACC and the data memory. Flag Affected: CF & ZF SBCR Subtract immediate data from WR with Borrow WR, #I Machine Code: 0 0 0 0 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC, R ← (WR) - I - (CF) Description: The immediate data I and CF are binary subtracted from the contents of the WR and the result is placed in the ACC and the WR. Flag Affected: SET CF CF & ZF Set CF Machine Code: 0 1 0 1 0 Machine Cycle: 1 Operation: Set CF Description: Set Carry Flag to 1. Flag Affected: CF 0 0 0 - 79 - 0 1 0 0 0 0 0 0 Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued SET PMF, #I Set ParaMeter Flag Machine Code: Machine Cycle: Operation: Description: 0 0 0 1 0 1 1 0 0 0 0 0 I3 I2 I1 I0 1 Set Parameter Flag Description of each flag: I0, I1, I2 : Reserved I3 = 1 : The input clock of the watchdog timer is Fosc/16384. SHLC R SHift Left R with CF and LSB = 0 Machine Code: 0 1 0 0 1 1 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC.n, R.n ← R.n-1; ACC.0, R.0 ← 0; CF ← R.3 Description: The contents of the ACC and the data memory location addressed by R6 to R0 are shifted left one bit, but bit 3 is shifted into CF, and bit 0 (LSB) is replaced with "0." The same contents are loaded into the ACC. Flag Affected: CF & ZF SHRC SHift Right R with CF and MSB = 0 R Machine Code: 0 1 0 0 1 1 0 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC.n, R.n ← R.n+1; ACC.3, R.3 ← 0; CF ← R.0 Description: The contents of the ACC and the data memory location addressed by R6 to R0 are shifted right one bit, but bit 0 is shifted into CF, and bit 3 (MSB) is replaced with "0." The same contents are loaded into the ACC. Flag Affected: CF & ZF - 80 - W741C250 Instruction Set Table 2, continued SKB0 R If bit 0 of R is equal to 1 then skip Machine Code: 1 0 0 0 1 0 0 Machine Cycle: 1 Operation: PC ← (PC) + 2; if R.0 = "1" Description: SKB1 R 0 0 R6 R5 R4 R3 R2 R1 R0 If bit 0 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 0 of R is not equal to 1, the program counter (PC) is incremented. If bit 1 of R is equal to 1 then skip Machine Code: 1 0 0 0 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: PC ← (PC) + 2; if R.1 = "1" Description: If bit 1 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 1 of R is not equal to 1, the program counter (PC) is incremented. SKB2 If bit 2 of R is equal to 1 then skip R Machine Code: 1 0 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: PC ← (PC) + 2; if R.2 = "1" Description: If bit 2 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 2 of R is not equal to 1. The program counter (PC) is incremented. - 81 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued SKB3 R If bit 3 of R is equal to 1 then skip Machine Code: 1 0 0 0 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: PC ← (PC) + 2; if R.3 = "1" Description: If bit 3 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 3 of R is not equal to 1, the program counter (PC) is incremented. STOP Enter the STOP mode Machine Code: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Machine Cycle: 1 Operation: STOP oscillator Description: Device enters STOP mode. When signal on the INT pin goes low or the falling edge signal of RC port is accepted, the µC will wake up and execute the next instruction. SUB Subtract ACC from R R, ACC Machine Code: 0 0 0 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC ← (R) - (ACC) Description: The contents of the ACC are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is loaded into the ACC. Flag Affected: CF & ZF - 82 - W741C250 Instruction Set Table 2, continued SUB WR , #I Subtract immediate data from WR Machine Code: 0 0 0 1 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC ← (WR) - I Description: The immediate data I are binary subtracted from the contents of the WR and the result is loaded into the ACC. Flag Affected: CF & ZF SUBR R, ACC Subtract ACC from R Machine Code: 0 0 0 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) - (ACC) Description: The contents of the ACC are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is placed in the ACC and the data memory. Flag Affected: CF & ZF SUBR Subtract immediate data from WR WR , #I Machine Code: 0 0 0 1 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC, WR ← (WR) - I Description: The immediate data I are binary subtracted from the contents of the WR and the result is placed in the ACC and the WR. Flag Affected: CF & ZF - 83 - Publication Release Date: March 1998 Revision A4 W741C250 Instruction Set Table 2, continued XRL R, ACC Exclusive OR R to ACC Machine Code: 0 0 1 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC ← (R) EX (ACC) Description: The contents of the data memory location addressed by R6 to R0 and the ACC are exclusive-ORed and the result is loaded into the ACC. Flag Affected: ZF XRL Exclusive OR immediate data to WR WR, #I Machine Code: 0 0 1 1 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC ← (WR) EX I Description: The contents of the Working Register (WR) and the immediate data I are exclusive-ORed and the result is loaded into the ACC. Flag Affected: ZF XRLR R, ACC Exclusive OR R to ACC Machine Code: 0 0 1 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0 Machine Cycle: 1 Operation: ACC, R ← (R) EX (ACC) Description: The contents of the data memory location addressed by R6 to R0 and the ACC are exclusive-ORed and the result is placed in the data memory and the ACC. Flag Affected: ZF - 84 - W741C250 Instruction Set Table 2, continued XRLR WR, #I Exclusive OR immediate data to WR Machine Code: 0 0 1 1 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0 Machine Cycle: 1 Operation: ACC, WR ← (WR) EX I Description: The contents of the Working Register (WR) and the immediate data I are exclusive-ORed and the result is placed in the WR and the ACC. Flag Affected: ZF - 85 - Publication Release Date: March 1998 Revision A4 W741C250 PACKAGE DIMENSIONS 64-Lead QFP (14 × 20 × 2.75mm footprint 4.8mm) HD D 64 52 51 1 E E H 33 19 20 e b 32 c 2 A A 1 See Detail F y Seating Plane L A L1 Symbol A A1 A2 b c D E e HD HE L L1 y 0 Dimension in inches Dimension in mm Min Nom Max Min. Max. Min. Min Nom Max Max. 0.130 0.004 3.30 0.10 0.107 0.112 0.117 2.73 2.85 2.97 0.014 0.016 0.020 0.35 0.40 0.50 0.004 0.006 0.010 0.10 0.15 0.25 0.546 0.551 0.556 13.87 14.00 14.13 0.782 0.787 0.792 19.87 20.00 20.13 0.033 0.039 0.045 0.85 1.00 1.15 0.728 0.740 0.752 18.49 18.80 19.10 0.964 0.976 0.988 24.49 24.80 25.10 0.039 0.047 0.055 1.00 1.20 1.40 0.087 0.094 0.103 2.21 2.40 2.62 0.004 0 12 - 86 - 0.10 0 12 Detail F W741C250 NOTES: - 87 - Publication Release Date: March 1998 Revision A4 W741C250 Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 88 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798