Ordering number : ENN*6830 CMOS IC LC680100A 32-Bit RISC Microcontroller Preliminary Overview The LC680100A is a 32 bit microcontroller developed exclusively by Sanyo, based on a 32 bit RISC CPU and incorporating on a single chip a high speed multiplier, 2kB of cache RAM, 2kB data RAM, DRAM control unit, external memory control unit and peripheral It is an ideal control device for digital cameras, color printers and hand held data terminals. Features (1) CPU core :32 bit RISC (Speed: 15MHz, Instruction cycle time: 67ns) (2) High Speed Multiplier :16bit x 16bit (in 1 instruction cycle) (3) Instruction cache RAM :2kB (512x32bit) (4) Data RAM :2kB (512x32bit) (5) DRAM Control Unit (6) External memory bus control unit (7) I/O port :One 16 bit I/O port, one 8 bit I/O port (8) UART :Two full duplex asynchronous channels (one channel has 16bit FIFO) (9) Serial I/O :One three-wire synchronous clock, 8 bit (10) Timer :4 channels (TM0 = 16bit + 16bit) (TM1, TM2, TM3 = 8bit + 8bit) (11) PWM Output :Three 8 bit resolution outputs (Common with TM1, TM2, TM3) (12) Interrupt controller :13 source events (5 internal, 8 external), 5 vectored (13) OSC circuit :Two types: main and RC. VCO/PLL is built-in, frequency multiplication possible. (14) Standby :Standby (HOLD) and sleep (HALT) modes available (15) VDD :3.3V typ. Package and Pins SQFP100, 100 pins Development tools A C compiler, assembler and emulator are available to be run on a PC. Ver.1.2 D0798 N3000 RM (IM) IT No.6830-1/16 LC680100A System Block Diagram Instruction Cache (2k bytes) Main OSC Multiplier Circuit Instruction Cache Control RC OSC System Clock, Standby 32bit Control RISC Bus CORE Data RAM Control (2k bytes) Mode Control Reset Control Coprocessor DRAM (Multiplier) Control Interrupt Control Interrupt enable control TM0H TM0L TM1H TM2H TM3H Special Function Register SFR Bus Control SIO0 UART0 UART1 SIO0 Timer 0 UART0 Timer 1 UART1 Timer 2 Port 0 Timer 3 Port 1 Figure 1 LC680100A System Block Diagram No.6830-2/16 LC680100A Terminal Assignment Diagram A7 A9 A8 VDD A10 A13 A12 A11 A15 A14 A16 A17 A19 A18 A21 A20 A22 A23 A26/CS4 A25/CS5 A24 VSS A27/CS3 89 37 P12/CASU 90 91 92 93 36 35 34 33 P11/RAS P10/BGNT VDD NMI 94 95 96 97 32 31 30 29 P0F P0E P0D/RXD1 P0C/TXD1 VSS P0B/PWM2 P0A/INT3 P09/INT2 P08/INT1 P06/PWM1 P07/T0IN/INT0 P04/SCK P05/PWM0 P03/SDI 3 4 5 28 27 26 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P01/RXD0 P02/SDO 98 99 100 1 2 VDD CK1 BREQ P14/DMXS P13/CASL VDD WRL/WR WAIT 39 38 LC680100A P00/TXD0 WRU/UBS 87 88 MODE CS2 CS6 RD VSS P17/MCLK/HOLDO P16/IRQOT P15/RFREQ TEST CS1 43 42 41 40 RESET CS0 83 84 85 86 HOLDI VSS A3 A2 A1 A0/LBS VSS PHIOT D13 D14 D15 47 46 45 44 CKIN D9 D10 D11 D12 79 80 81 82 CKOT D7 VDD D8 VDD D6 A6 A5 A4 CMP D4 D5 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 77 49 78 48 VSS D3 CK2 D2 D0 D1 (SQFP100, 0.5mm pitch) Package Dimension (unit : mm) 3181B SANYO : SQFP-100 No.6830-3/16 LC680100A Terminal Functions Pin Number Pin Name Note: PU = pull-up I/O Function Description Pin Format 1,6,15,34,55 VDD ,82 - Power supply +ve - 4,9,24,43,73 VSS ,91 - Power supply -ve Schmitt Input 2 CK1 I Input to main oscillator 3 CK2 O Output from main oscillator CMOS output 5 CMP I/O Phase comparator filter pin (multiplier circuit). Schmitt Input•Tristate output 7 CKOT 8 10 O CK1 or half frequency clock output from multiplier CMOS output CKIN I External clock input Schmitt Input PHIOT O System clock output CMOS output 11 HOLDI I HOLD request input Schmitt Input 12 RESET I Reset terminal Schmitt Input 13 MODE I Bus mode setting at reset Schmitt Input 14 TEST I Test input (Normally connected to VSS) Schmitt Input 16 P00/TXD0 I/O PORT0 bit0 I/O. Also UART0 send 17 P01/RXD0 I/O PORT0 bit1 I/O. Also UART0 receive •Used as input: Schmitt Input; presence of PU resistor software selectable. 18 P02/SDO I/O PORT0 bit2 I/O. Also SIO0 data out 19 P03/SDI I/O PORT0 bit3 I/O. Also SIO0 data in 20 P04/SCK I/O PORT0 bit4 I/O. Also SIO0 clock 21 P05/PWM0 I/O PORT0 bit5 I/O. Also PWM0 output 22 P06/PWM1 I/O PORT0 bit6 I/O. Also PWM1 output 23 P07/T0IN/INT0 I/O PORT0 bit7 I/O. Timer0 event input INT0 input 25 P08/INT1 I/O PORT0 bit8 I/O. INT1 input 26 P09/INT2 I/O PORT0 bit9 I/O. INT2 input 27 P0A/INT3 I/O PORT0 bit10 I/O. INT3 input 28 P0B/PWM2 I/O PORT0 bit11 I/O. PWM2 output 29 P0C/TXD1 I/O PORT0 bit12 I/O. UART1 send 30 P0D/RXD1 I/O PORT0 bit13 I/O. UART1 receive 31 P0E I/O PORT0 bit14 I/O. 32 P0F I/O PORT0 bit15 I/O. •Used as Output: CMOS/N-ch OD mode software selectable. No.6830-4/16 LC680100A Pin Number Pin Name 33 NMI 35 P10/BGNT 36 I/O Pin Format NMI interrupt Schmitt Input I/O PORT1 bit0 input. Also bus grant output. Schmitt Input•Tristate output P11/RAS I/O PORT1 bit1 input. Also DRAM control RAS signal out. 37 P12/CASU I/O PORT1 bit2 input. Also DRAM control CASU signal out. 38 P13/CASL I/O PORT1 bit3 input. Also DRAM control CASL signal out. 39 P14/DMXS I/O PORT1 bit4 input. Also DRAM control DMXS signal out. 40 P15/RFREQ I/O PORT1 bit5 input. Also DRAM control RFREQ I/O. Schmitt Input•PU Output 41 P16/IRQOT I/O PORT1 bit6 input. Also IRQOT output. Schmitt Input•Tristate output 42 P17/MCLK/HOLD0 I/O PORT1 bit7 input. MCLK output, HOLD state output 44 A0/LBS I/O Bus Address bit0 or Lower byte strobe signal. 45 to 54, 56 to 69 A1to A24 I/O Bus Address bit1 to 24. 70 A25/CS5 I/O Bus Address bit25 or CS5. 71 I Function Description Schmitt Input•Tristate output A26/CS4 I/O Bus Address bit26 or CS4 72 A27/CS3 I/O Bus Address bit27 or CS3. 74 to 81, 83 to 90 D0 to D15 I/O Bus data bit0 to 15 Schmitt Input•Tristate output 92 CS0 I/O CS0 93 CS1 I/O Schmitt Input•Tristate output CS1 94 CS2 I/O CS2 95 CS6 I/O CS6 96 RD I/O Bus read signal. 97 WRU/UBS I/O Upper byte write signal or Upper byte strobe. 98 WRL/WR I/O Upper byte write signal or Write. 99 WAIT I/O Bus cycle wait Schmitt Input•PU output 100 BREQ I Bus request. Schmitt Input Schmitt Input•Tristate output No.6830-5/16 LC680100A 1. Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Symbol Supply voltage VDDmax Input voltage VI(1) Output voltage Pins Conditions VDD Ratings Unit -0.3 to +4.6 V Pins for each input only -0.3 to VDD+0.3 V VO(1) Pins for each output only -0.3 to VDD+0.3 V Input/Output voltage VIO(1) Pins for both input and output -0.3 to VDD+0.3 V High level peak output current IOPH(1) Each output pin Current at each pin -5 mA ∑IOAH(1) P00 to P08 Total of 9 pins -80 mA ∑IOAH(2) P09 to P0F Total of 7 pins -80 mA IOPL(1) Each output pin Current at each pin 20 mA ∑IOAL(1) P00 to P07 Total of 8 pins 80 mA ∑IOAL(2) P08 to P0F Total of 8 pins 80 mA Ta = -20 to 70°C 440 mW High level total output current Low level peak output current Low level total output current Note1 Maximum power consumption Pdmax Operating temperature range Topg -20 to +70 °C Storage temperature range Tstg -55 to +125 °C SQFP100 Note2 Note1:All VDD terminals (pin1, 6, 15, 34, 55, 82) should be connected externally. All VSS terminals (pin4, 9, 24, 43, 73, 91) should be connected externally. Note2:Reflow method is recommended when soldering the SQFP package. No.6830-6/16 LC680100A 2. Recommended Operating Range at Ta = -20 to 70°C, VSS = 0V Parameter Symbol Pins Ratings Conditions Unit Min. Typ. Max. 3.0 3.3 3.6 V 2.5 3.6 V Operating supply voltage range VDD (1) VDD Supply voltage (Memory hold) VHD VDD High level input voltage VIH(1) Input pins except CK1 0.7VDD VDD VIH(2) CK1 0.7VDD VDD Low level input voltage VIL(1) Input pins except CK1 VSS 0.3VDD VIL(2) CK1 VSS 0.3VDD tCYC(1) CKIN 300K to 15MHz 66 3333 tCYC(2) CK1 400K to 15MHz (VCO is not used.) 132 5000 fEXCKIN CKIN Figure 1 300k 15M fEXCK1 CK1 Figure 1 400k 15M tCKINL tCKINH CKIN Figure 1 28 tCK1L tCK1H CK1 Figure 1 tEXR tEXF CKIN, CK1 Figure 1 fCK1 CK1, CK2 Figure 2, Table 1 Operation cycle time External system clock frequency External clock pulse width External clock rising and falling time Operation frequency range Keep RAM and Register data in Standby mode. V V ns Hz ns 28 400k 5 ns 8M Hz No.6830-7/16 LC680100A 3. Electrical Characteristics at Ta = -20 to 70°C, VSS = 0V, VDD = 3.0 to 3.6V Parameter Symbol Pins Ratings Conditions Min. Typ. Unit Max. IIH(1) Pins for each input only VIN = VDD 5 IIH(2) Pins for both input and output VIN = VDD Output disabled 5 IIL(1) Pins for each input only VIN = VSS -5 IIL(2) P15/RFREQ,WAIT VIN = VSS Output disabled -5 IIL(3) Input/output commonly terminals except written above VIN = VSS Output disabled -5 VOH(1) Port0 with PU option, P15/RFREQ IOH = -0.05mA VDD-0.5 VOH(2) Input/output commonly terminals except written above, CKOT, PHIOT IOH = -1mA VDD-0.5 VOL(1) Pins for each output only IOL = 4mA 0.4 VOL(2) Pins for both input and output IOL = 4mA 0.4 PU resistor rPU Port0 with PU option, P15/RFREQ Hysterisis voltage vHIS Each input only, I/O terminal External interrupt pulse width tINTL tINTH INT0 to INT3 Reset input pulse width tRESL RESET Figure 4 2 VCO frequency fVCO CKOT Figure 5 4M Figure 5, cCMP = 0.1µF High level input current Low level input current High level output voltage Low level output voltage NMI µA µA V V 1K 20K VDD 0.1 Figure 4 VCO lock-up time tLOCK CMP,CKOT RC oscillation frequency fRC Built-in RC oscillation circuit Ceramic oscillation stabilizing time tCF CK1,CK2 Figure 3 Current consumption in run mode IDDRUN VDD CKIN=15MHz Current consumption in sleep mode IDDSLP Current consumption in standby mode Pin capacitance Ω 2 Tcyc 4 ms 16M ms 10 300k Hz 1M Hz 10 ms 60 120 mA VDD 50 100 mA IDDSTY VDD 10 200 µA cP All pins 10 PF No.6830-8/16 LC680100A 4. Serial Input/Output Characteristics at Ta = -20 to 70°C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure 14 Parameter Symbol Pins Ratings Conditions Min. Typ. Unit Max. Input clock cycle time tSCK SCK input Figure 6 16 Tcyc Input clock L pulse width tSCKL SCK input Figure 6 533 ns Input clock H pulse width tSCKH SCK input Figure 6 533 ns Output clock cycle time tSCKO SCK output Figure 6 16 Tcyc Output clock L pulse width tSCKOL SCK output Figure 6 8 Tcyc Output clock H pulse width tSCKOH SCK output Figure 6 8 Tcyc Input data set up time tsDI SCK, SDI Figure 6 200 ns Input data hold time thDI SCK, SDI Figure 6 50 Output delay time tdDO SCK, SDO Figure 6 ns 100 130 ns No.6830-9/16 LC680100A 5. Bus Timing at Ta = -20 to 70°C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure14 Parameter Symbol Pins Ratings Conditions Min. Typ. Unit Max. Address output delay time tAAD A27 to A0 Figure 7, Figure 8 75 Address output hold time tADA A27 to A0 Figure 7, Figure 8 75 CS delay time (1) tACS CSn Figure 7, Figure 8 45 CS hold time (1) tCSA CSn Figure 7, Figure 8 55 RD delay time (1) tARD RD Figure 7 45 RD hold time (1) tRDA RD Figure 7 55 Read data set up time (1) tsRD1 D15 to D0 Figure 7 30 Read data hold time (1) thRD1 D15 to D0, Figure 7 0 WR delay time (1) tAWR WRU, WRL Figure 8 45 WR hold time (1) tWRA WRU, WRL Figure 8 55 Write data delay time (1) tdWD1 D15 to D0, WRU , WRL Figure 8 70 Write data hold time (1) thWD1 D15 to D0, WRU, WRL Figure 8 0 Bus request input setup time tsBRQ CKIN, BREQ Figure 12 30 Bus request input hold time thBRQ CKIN, BREQ Figure 12 30 BGNT output delay time tdBGT CKIN, BGNT Figure 12 50 Bus release delay time tdBOF Figure 12 50 WAIT set up time tsWAIT WAIT input hold time thWAIT CKIN, A27 to A0, RD ,WRU ,WRL CKIN, WAIT CKIN, WAIT ns ns ns 30 ns 30 30 No.6830-10/16 LC680100A 6. DRAM Timing at Ta = -20 to 70°C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure 14 Parameter Symbol Pins Ratings Conditions Min. Typ. Unit Max. Address (ROW) delay time tAROW A27 to A0 Figure 9, Figure 10 75 Address (COL) delay time tACOL A27 to A0 Figure 9, Figure 10 55 Address (COL) hold time tCOLA A27 to A0 Figure 9, Figure 10 70 RAS delay time tARAS RAS Figure 9, Figure 10 65 RAS hold time tRASA RAS Figure 9, Figure 10 50 DMXS delay time tDMXSR DMXS Figure 9, Figure 10 70 DMXS hold time tDMXSC DMXS Figure 9, Figure 10 50 CASL•CASU delay time tACAS(L/U) CASU, CASL Figure 9, Figure 10 65 CASL•CASU hold time tCAS(L/U)A CASU, CASL Figure 9, Figure 10 50 Read data set up time (2) tsRD2 D15 to D0 Figure 9 30 Read data hold time (2) thRD2 D15 to D0, RD Figure 9 0 WRL•WRU delay time tAWR(L/U) WRU, WRL Figure 10 45 WRL•WRU hold time ns ns tWR(L/U)A WRU, WRL Figure 10 50 Write data delay time (2) tdWD2 D15 to D0, WRU, WRL Figure 10 70 Write data hold time (2) thWD2 D15 to D0, WRU, WRL Figure 10 ns 0 Table 1. Guaranteed Value for the Ceramic Oscillators Oscillator 4MHZ (External Capacitor) 4MHZ (Capacitor built-in) 8MHZ (External Capacitor) 8MHZ (Capacitor built-in) Manufacturer Murata Oscillator C1 C2 CSA4. OOMG CST4. OOMGW 33pF (30pF) 33pF (30pF) CSA8. OOMTZ CST8. OOMTW 33pF (30pF) 33pF (30pF) No.6830-11/16 LC680100A Figure1 External Clock Input 1/fEXCKIN or 1/fEXCK1 External Input CK1 0.8VDD 0.2VDD CK2 External Input CKIN tCKINL or tCK1L Figure2 Ceramic Oscillation C1 tCKINH or tCK1H Figure3 Oscillation Stabilizing Time VDD CK1 VDD lowest limit Oscillator CK2 CK2 C2 Stabilized oscillation tCF Figure5 VCO Figure4 External Pulse Input Phase Compare 0.5VDD cCMP CMP VCO tINTL tRESL tINTH VCOSW 1/2 CKOT Figure6 Serial Input/Output Timing tSCK or tSCKO tSCKL OR tSCKOL tSCKH OR tSCKOH SCK 0.5VDD tsDI thDI 0.5VDD SDI SDO 0.5VDD tdDO No.6830-12/16 LC680100A Figure7 External Bus Read Timing Figure8 External Bus Write Timing No.6830-13/16 LC680100A Figure9 DRAM Read Timing Figure10 DRAM Write Timing No.6830-14/16 LC680100A Figure11 REREQ Input/Output Timing Figure12 Bus Request/Release Timing Figure13 Wait Input/Output Timing Figure14 The Load Used in Measuring the Timing No.6830-15/16 LC680100A PS No.6830-16/16