White Electronic Designs WE128K32-XXX 128Kx32 EEPROM MODULE, SMD 5962-94585 FEATURES Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs 5 Volt Power Supply Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation ■ Weight WE128K32-XG2TX - 8 grams typical WE128K32-XH1X - 13 grams typical ■ ■ ■ ■ ■ ■ Access Times of 120*, 140, 150, 200, 250, 300ns ■ Packaging: • 66-pin, PGA Type, 27.3mm (1.075") square, Hermetic Ceramic HIP (Package 400) • 68 lead, 22.4mm sq. CQFP (G2T), 4.57mm (0.180") high, (Package 509) ■ Organized as 128Kx32; User Configurable as 256Kx16 or 512Kx8 ■ Write Endurance 10,000 Cycles ■ Data Retention Ten Years Minimum (at +25°C) ■ Commercial, Industrial and Military Temperature Ranges ■ Low Power CMOS ■ Automatic Page Write Operation ■ Page Write Cycle Time: 10ms Max FIG. 1 * 120ns not available for SMD product PIN CONFIGURATION FOR WE128K32N-XH1X PIN DESCRIPTION TOP VIEW I/O0-31 Data Inputs/Outputs A0-16 Address Inputs WE1-4 Write Enables CS1-4 Chip Selects OE Output Enable VCC Power Supply GND Ground NC Not Connected BLOCK DIAGRAM January 2004 Rev. 9 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs FIG. 3 WE128K32-XXX PIN CONFIGURATION FOR WE128K32-XG2TX TOP VIEW PIN DESCRIPTION I/O0-31 Data Inputs/Outputs The WEDC 68 lead CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But it has the TCE and lead inspection advantage of the CQFP form. A0-16 Address Inputs WE1-4 Write Enables CS1-4 Chip Selects OE Output Enable VCC Power Supply GND Ground NC Not Connected BLOCK DIAGRAM White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 WE128K32-XXX White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter TRUTH TABLE Symbol Operating Temperature TA Storage Temperature Signal Voltage Relative to GND Unit -55 to +125 °C T STG -65 to +150 °C VG -0.6 to +6.25 V -0.6 to +13.5 V Voltage on OE and A9 CS H L L X X X NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. OE X L H H X L WE X H L X H X Mode Standby Read Write Out Disable Write Inhibit Data I/O High Z Data Out Data In High Z/Data Out CAPACITANCE (TA = +25°C) Parameter RECOMMENDED OPERATING CONDITIONS Symbol Conditions OE capacitance COE VIN = 0 V, f = 1.0 MHz Max Unit CWE VIN = 0 V, f = 1.0 MHz 50 pF Max Unit WE1-4 capacitance HIP (PGA) CQFP G2T 4.5 5.5 V CS1-4 capacitance CCS VIN = 0 V, f = 1.0 MHz 20 pF 2.0 V CC + 0.3 V Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 20 pF V IL -0.5 +0.8 V Address input capacitance CAD VIN = 0 V, f = 1.0 MHz 50 pF Operating Temp. (Mil.) TA -55 +125 °C Operating Temp. (Ind.) TA -40 +85 °C Parameter Symbol Min Supply Voltage V CC Input High Voltage V IH Input Low Voltage pF 20 20 This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Max Unit VCC = 5.5, VIN = GND to VCC 10 µA CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA Operating Supply Current x 32 Mode ICCx32 CS = VIL, OE = VIH, f = 5MHz 250 mA Standby Current ISB CS = VIH, OE = VIH, f = 5MHz 2.5 mA Output Low Voltage VOL IOL = 2.1mA, VCC = 4.5V 0.45 V Input Leakage Current Output Leakage Current Symbol ILI ILOx32 Conditions Min Output High Voltage VOH IOH = -400µA, VCC = 4.5V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V 2.4 FIG. 4 AC TEST CIRCUIT V AC TEST CONDITIONS Parameter Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75Ω . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs AC WRITE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) WRITE A write cycle is initiated when OE is high and a low pulse is on WE or CS with CS or WE low. The address is latched on the falling edge of CS or WE whichever occurs last. The data is latched by the rising edge of CS or WE, whichever occurs first. A byte write operation will automatically continue to completion. Write Cycle Parameter WRITE CYCLE TIMING Figures 5 and 6 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS or WE goes low. The WE line transition from high to low also initiates an internal 150 µsec delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the 150 µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 WE128K32-XXX 4 Symbol Min Max Unit Write Cycle Time, TYP = 6ms tWC Address Set-up Time tAS 0 10 ms ns Write Pulse Width (WE or CS) tWP 100 ns Chip Select Set-up Time tCS 0 ns Address Hold Time tAH 100 ns Data Hold Time tDH 10 ns Chip Select Hold Time tCSH 0 ns Data Set-up Time tDS 50 ns Output Enable Set-up Time tOES 0 ns Output Enable Hold Time tOEH 0 ns Write Pulse Width High tWPH 50 ns White Electronic Designs WE128K32-XXX FIG. 5 WRITE WAVEFORMS WE CONTROLLED FIG. 6 WRITE WAVEFORMS CS CONTROLLED 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WE128K32-XXX White Electronic Designs READ The WE128K32-XXX stores data at the memory location determined by the address pins. When CS and OE are low and WE is high, this data is present on the outputs. When CS and OE are high, the outputs are in a high impedance state. This two line control prevents bus contention. AC READ CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Read Cycle Parameter Symbol Read Cycle Time t RC -120 Min Max 120 -140 Min Max 140 -150 Min Max 150 -200 Min Max 200 -250 Min Max 250 -300 Min Max 300 Address Access Time t ACC 120 140 150 200 250 300 ns Chip Select Access Time t ACS 120 140 150 200 250 300 ns Output Hold from Add. Change, OE or CS t OH 0 Output Enable to Output Valid t OE 0 Chip Select or OE to High Z Output t DF 0 50 0 0 55 60 70 FIG. 7 READ WAVEFORMS Address CS OE Output NOTES: OE may be delayed up to t ACS - tOE after the falling edge of CS without impact on t OE or by t ACC - t OE after an address change without impact on t ACC . White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 6 0 0 55 70 0 0 55 70 0 0 85 70 0 Unit ns ns 85 ns 70 ns WE128K32-XXX White Electronic Designs DATA POLLING DATA POLLING CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) The WE128K32-XXX offers a data polling feature which allows a faster method of writing to the device. Figure 8 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D7 (for each chip.) Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. Parameter Symbol Min Data Hold Time tDH 10 OE Hold Time tOEH 10 OE To Output Valid tOE Write Recovery Time t WR Max ns ns 55 0 Unit ns ns DATA POLLING WAVEFORMS FIG. 8 Toggle But Characteristics(1) TOGGLE BIT: In addition to DATA Polling another method for determining the end of a write cycle is provided. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. Symbol Parameter Min Max Units t DH Data Hold Time 10 ns t OEH OE Hold Time 10 ns t OE OE to Output Delay t OEHP OE High Pulse 150 ns t WR Write Recovery Time 0 ns ns WE CS tOEH OE tDH I/O6 (2) tOE HIGH Z tWR NOTE: 1. Toggling either OE or CS or both OE and CS will operate toggle bit. 2. Beginning and ending state of I/O6 will vary 3. Any address location may be used but the address should not vary. 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs PAGE WRITE OPERATION PAGE WRITE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) The WE128K32-XXX has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150µs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. The usual procedure is to increment the least significant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. Page Mode Write Characteristics Symbol Parameter Unit Min Max Write Cycle Time, TYP = 6ms t WC Address Set-up Time tAS 0 ns Address Hold Time (1) tAH 100 ns Data Set-up Time tDS 50 ns Data Hold Time tDH 10 ns Write Pulse Width tWP 100 ns Byte Load Cycle Time tBLC Write Pulse Width High tWPH 10 150 50 1. Page address must remain valid for duration of write cycle. After the 150µs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. FIG. 9 PAGE MODE WRITE WAVEFORMS x x White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 WE128K32-XXX 8 ms µs ns White Electronic Designs WE128K32-XXX FIG. 10 SOFTWARE DATA PROTECTION ENABLE ALGORITHM(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE NOTES: 1. Data Format: D7 - D0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs WE128K32-XXX SOFTWARE DATA PROTECTION FIG. 11 A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WE-128K32-XXX has the feature disabled. Write access to the device is unrestricted. SOFTWARE DATA PROTECTION DISABLE ALGORITHM(1) To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. LOAD DATA 55 TO ADDRESS 2AAA (3) EXIT DATA PROTECT STATE LOAD DATA 20 TO ADDRESS 5555 HARDWARE DATA PROTECTION LOAD DATA XX TO ANY ADDRESS(4) These features protect against inadvertent writes to the WE128K32-XXX. These are included to improve reliability during normal operation: LOAD LAST BYTE TO LAST ADDRESS a) VCC power on delay As VCC climbs past 3.8V typical the device will wait 5msec typical before allowing write cycles. b) VCC sense While below 3.8V typical write cycles are inhibited. c) Write inhibiting Holding OE low and either CS or WE high inhibits write cycles. d) Noise filter Pulses of <8ns (typ) on WE or CS will not initiate a write cycle. NOTES: 1. Data Format: D7 - D0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 10 White Electronic Designs WE128K32-XXX PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T) White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 12 WE128K32-XXX WE128K32-XXX White Electronic Designs FIG. 12 ALTERNATE PIN CONFIGURATION FOR WE128K32NP-XH1X TOP VIEW PIN DESCRIPTION I/O0-31 Data Inputs/Outputs BLOCK DIAGRAM A0-16 Address Inputs WE 1-4 Write Enables CS1-4 Chip Selects OE Output Enable VCC Power Supply GND Ground NC Not Connected ORDERING INFORMATION W E 128K32 X - XXX X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: Q = Compliant M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C PACKAGE TYPE: H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400*) G2T = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 509) ACCESS TIME (ns) IMPROVEMENT MARK N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade P = Alternate Pin Configuration for HIP package ORGANIZATION 128K x 32 User Configurable as 256K x 16 or 512K x 8 EEPROM WHITE ELECTRONIC DESIGNS CORP. 13 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs DEVICE TYPE SPEED PACKAGE WE128K32-XXX SMD NO. 128K x 32 EEPROM Module 300ns 66 pin HIP (H1) 5962-94585 01H5X 128K x 32 EEPROM Module 250ns 66 pin HIP (H1) 5962-94585 02H5X 128K x 32 EEPROM Module 200ns 66 pin HIP (H1) 5962-94585 03H5X 128K x 32 EEPROM Module 150ns 66 pin HIP (H1) 5962-94585 04H5X 128K x 32 EEPROM Module 140ns 66 pin HIP (H1) 5962-94585 05H5X 128K x 32 EEPROM Module 300ns 66 pin HIP (H1, P type pinout) 5962-94585 01H6X 128K x 32 EEPROM Module 250ns 66 pin HIP (H1, P type pinout) 5962-94585 02H6X 128K x 32 EEPROM Module 200ns 66 pin HIP (H1, P type pinout) 5962-94585 03H6X 128K x 32 EEPROM Module 150ns 66 pin HIP (H1, P type pinout) 5962-94585 04H6X 128K x 32 EEPROM Module 140ns 66 pin HIP (H1, P type pinout) 5962-94585 05H6X 128K x 32 EEPROM Module 300ns 68 lead CQFP/J (G2T) 5962-94585 01HMX 128K x 32 EEPROM Module 250ns 68 lead CQFP/J (G2T) 5962-94585 02HMX 128K x 32 EEPROM Module 200ns 68 lead CQFP/J (G2T) 5962-94585 03HMX 128K x 32 EEPROM Module 150ns 68 lead CQFP/J (G2T) 5962-94585 04HMX 128K x 32 EEPROM Module 140ns 68 lead CQFP/J (G2T) 5962-94585 05HMX White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 14