WEDC WE32K32N

White Electronic Designs
WE32K32-XXX
32Kx32 EEPROM MODULE, SMD 5962-94614
FEATURES
Access Times of 80**, 90, 120, 150ns
MIL-STD-883 Compliant Devices Available
Write Endurance, 10,000 Cycles
Packaging:
• 68 lead, Hermetic CQFP (G2U), 122.4mm
(0.880") square, 3.56mm (0.140") height
(Package 510).
Organized as 32Kx32; User Configurable 64Kx16
or 128Kx8
Commercial, Industrial and Military Temperature
Ranges
• 66-pin, PGA Type, 1.075" square, Hermetic
Ceramic HIP (Package 400)
Automatic Page Write Operation
Page Write Cycle Time: 10ms Max
* This product is subject to change without notice.
** 80ns speed is not fully characterized and is subject to change or cancellation without
notice.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
Data Retention at 25°C, 10 Years
5 Volt Power Supply
Low Power CMOS, 10mA Standby Typical
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
FIGURE 1 – PIN CONFIGURATION FOR
WE32K32N-XH1X
Top View
1
12
34
45
56
I/O8
WE2#
I/O15
I/O24
VCC
I/O31
I/O9
CS2#
I/O14
I/O25
CS4#
I/O30
I/O10
GND
I/O13
I/O26
WE4#
I/O29
A13
I/O11
I/O12
A6
I/O27
I/O28
A14
A10
OE#
A7
A3
A0
NC
A11
NC
NC
A4
A1
NC
A12
WE1#
A8
A5
A2
NC
VCC
I/O7
A9
WE3#
I/O23
I/O0
CS1#
I/O6
I/O16
CS3#
I/O22
I/O1
NC
I/O5
I/O17
GND
I/O21
I/O4
I/O18
I/O3
I/O2
11
23
22
33
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
W E 1 # CS 1 #
W E 2 # CS 2 #
W E 3 # CS 3 #
W E 4 # CS 4
32K x 8
32K x 8
32K x 8
32K x 8
OE#
A0-14
I/O20
I/O19
44
Pin Description
I/O0-31
A0-14
WE1-4#
CS1-4#
OE#
VCC
GND
NC
55
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
66
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
1
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WE32K32-XXX
FIGURE 2 – PIN CONFIGURATION FOR WE32K32-XG2UX
Pin Description
NC
A0
A1
A2
A3
A4
A5
CS3#
GND
CS4#
WE1#
A6
A7
A8
A9
A10
VCC
Top View
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
NC
NC
NC
NC
WE2#
WE3#
WE4#
OE#
CS2#
NC
CS1#
NC
A14
A13
A12
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A11
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VCC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O0-31
A0-14
WE1-4#
CS1-4#
OE#
VCC
GND
NC
Block Diagram
W E 1 # CS 1 #
W E 2 # CS 2 #
W E 3 # CS 3 #
W E 4 # CS 4 #
32K x 8
32K x 8
32K x 8
32K x 8
OE#
A0-14
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
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WE32K32-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE# and A9
Symbol
TA
TSTG
VG
TRUTH TABLE
Unit
°C
°C
V
V
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
CS#
H
L
L
X
X
X
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Symbol
VCC
VIH
VIL
TA
TA
Min
4.5
2.0
-0.3
-55
-40
Max
5.5
VCC + 0.3
+0.8
+125
+85
WE#
X
H
L
X
H
X
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
CAPACITANCE
TA = +25°C
Symbol
Conditions
Address input capacitance
OE# capacitance
CAD
COE
VIN = 0 V, f = 1.0 MHz
50
pF
WE# capacitance
CWE
VIN = 0 V, f = 1.0 MHz
50
pF
CS1-4# capacitance
CCS
VIN = 0 V, f = 1.0 MHz
25
pF
Data I/O capacitance
CI/O
VI/O = 0 V, f = 1.0 MHz
40
pF
Parameter
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
OE#
X
L
H
H
X
L
Unit
V
V
V
°C
°C
Max Unit
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
Input Leakage Current
Output Leakage Current
ILI
ILOx32
Operating Supply Current (x32)
Standby Current
Output Low Voltage
Output High Voltage
ICCx32
ISB
VOL
VOH
-80
Conditions
Min
VCC = 5.5, VIN = GND to VCC
CS# = VIH, OE# = VIH, VOUT = GND to
VCC
CS# = VIL, OE# = VIH, f = 5MHz
CS# = VIH, OE# = VIH, f = 5MHz
IOL = 2.1mA, VCC = 4.5V
IOH = -400µA, VCC = 4.5V
FIGURE 3
AC Test Circuit
-90
Max
10
10
Min
320
2.5
0.45
2.4
-120
Max
10
10
Min
250
2.5
0.45
2.4
Max
10
10
-150
Min
200
2.5
0.45
2.4
Max
10
10
150
2.5
0.45
2.4
Unit
µA
µA
mA
mA
V
V
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
≈
Typ
VIL = 0, VIH = 3.0
5
1.5
1.5
Unit
V
ns
V
V
Notes: VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
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March 2006
Rev. 4
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WE32K32-XXX
WRITE
The WE# line transition from high to low also initiates
an internal 150 µsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150 µsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
A write cycle is initiated when OE# is high and a low pulse
is on WE# or CS# with CS# or WE# low. The address
is latched on the falling edge of CS# or WE# whichever
occurs last. The data is latched by the rising edge of CS#
or WE#, whichever occurs first. A byte write operation will
automatically continue to completion.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
AC Write Characteristics
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
WRITE CYCLE
Write Cycle Parameter
-80
-90
-120
-150
Symbol
Unit
Min
Max
Min
10
Max
Min
10
Max
Min
10
Max
10
ms
Write Cycle Time, TYP = 6ms
tWC
Address Set-up Time
tAS
0
0
30
30
ns
Write Pulse Width (WE# or CS#)
tWP
100
100
150
150
ns
Chip Select Set-up Time
tCS
0
0
0
0
ns
Address Hold Time
tAH
50
50
100
100
ns
Data Hold Time
tDH
0
0
10
10
ns
Chip Select Hold Time
tCSH
0
0
0
0
ns
Data Set-up Time
tDS
50
50
100
100
ns
Write Pulse Width High
tWPH
50
50
50
50
ns
Output Enable Set-up Time
tOES
10
10
10
10
ns
Output Enable Hold Time
tOEH
10
10
10
10
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
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WE32K32-XXX
FIGURE 4 – WRITE WAVEFORMS WE# CONTROLLED
t WC
OE#
t OEH
t OES
ADDRESS
t AS
CS1-4#
tCSH
t AH
t CS
WE1-4#
t WP
t WPH
t DS
t DH
DATA IN
FIGURE 5 – WRITE WAVEFORMS CS# CONTROLLED
t WC
OE#
t OEH
t OES
ADDRESS
t AS
tCSH
t AH
WE1 - 4#
t CS
CS1 - 4#
t WP
t WPH
t DS
t DH
DATA IN
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
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WE32K32-XXX
READ
The WE32K32-XXX stores data at the memory location
determined by the address pins. When CS# and OE#
are low and WE# is high, this data is present on the
outputs. When CS# and OE# are high, the outputs are in
a high impedance state. This 2 line control prevents bus
contention.
AC Read Characteristics (See Figure 6)
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
READ CYCLE
Symbol
Parameter
-80
Min
Read Cycle Time
tRC
-90
Max
80
Min
-120
Max
90
Min
-150
Max
120
Min
Unit
Max
150
ns
Address Access Time
tACC
80
90
120
150
ns
CS Access Time
tACS
80
90
120
150
ns
Output Hold from Add. Change, OE# or CS#
tOH
Output Enable to Output Valid
tOE
40
50
85
85
ns
Chip Select or OE# to Output in High Z
tDF
40
50
70
70
ns
0
0
0
0
ns
FIGURE 6 – READ WAVEFORMS
t RC
ADDRESS
ADDRESS VALID
CS#
t ACS
t OE
OE#
t DF
t ACC
OUTPUT
t OH
HIGH Z
OUTPUT
VALID
NOTES:
1. OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - tOE after
an address change without impact on tACC.
2. tCHZ, tOHZ are specified from OE# or CS# whichever occurs first (CL = 5pF).
3. All I/O transitions are measured ±200 mV from steady state with loading as specified in "Load Test Circuits."
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
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WE32K32-XXX
DATA POLLING CHARACTERISTICS
DATA POLLING
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
The WE32K32-XXX offers a data polling feature which
allows a faster method of writing to the device. Figure 7
shows the timing diagram for this function. During a byte
or page write cycle, an attempted read of the last byte
written will result in the complement of the written data
on D7 (for each chip.) Once the write cycle has been
completed, true data is valid on all outputs and the next
cycle may begin. Data polling may begin at any time during
the write cycle.
Parameter
Symbol
Min
Data Hold Time
tDH
10
ns
OE# Hold Time
tOEH
10
ns
OE# To Output Valid
tOE
Write Recovery Time
tWR
Max
100
0
Unit
ns
ns
FIGURE 7 – DATA POLLING WAVEFORMS
WE1-4#
CS1-4#
t OEH
OE#
I/O7
t DH
t OE
HIGH Z
t WR
ADDRESS
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March 2006
Rev. 4
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WE32K32-XXX
PAGE WRITE OPERATION
The usual procedure is to increment the least significant
address lines from A0 through A5 at each write cycle. In this
manner a page of up to 64 bytes can be loaded in to the
EEPROM in a burst mode before beginning the relatively
long interval programming cycle.
The WE32K32-XXX has a page write operation that allows
one to 64 bytes of data to be written into the device and
consecutively loads during the internal programming
period. Successive bytes may be loaded in the same
manner after the first data byte has been loaded. An
internal timer begins a time out operation at each write
cycle. If another write cycle is completed within 150µs
or less, a new time out period begins. Each write cycle
restarts the delay period. The write cycles can be continued
as long as the interval is less than the time out period.
After the 150µs time out is completed, the EEPROM
begins an internal write cycle. During this cycle the entire
page of bytes will be written at the same time. The internal
programming cycle is the same regardless of the number
of bytes accessed.
PAGE WRITE CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
PAGE MODE WRITE CHARACTERISTICS
Parameter
Write Cycle Time, TYP = 6ms
Data Set-up Time
Data Hold Time
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
Symbol
tWC
tDS
tDH
tWP
tBLC
tWPH
-80
Min
-90
Max
10
50
0
100
Min
-120
Max
10
50
0
100
Max
10
100
10
150
150
50
Min
-150
150
50
Min
Max
10
100
10
150
150
50
150
50
Unit
ms
ns
ns
ns
µs
ns
FIGURE 8 – PAGE WRITE WAVEFORMS
OE#
CS#
t WP
t BLC
t WPH
WE#
t DS
t DH
ADDRESS (1)
VALID
ADDRESS
t WC
VALID DATA
DATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE n
BYTE n + 1
NOTE:
1. Decoded Address Lines must be valid for the duration of the write.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
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WE32K32-XXX
FIGURE 9 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
NOTES:
1. Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data is loaded.
4. 1 to 64 bytes of data to be loaded.
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March 2006
Rev. 4
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FIGURE 10 –
SOFTWARE BLOCK DATA PROTECTION
DISABLE ALGORITHM(1)
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled
or disabled by the user. When shipped by White
Microelectronics, the WE32K32-XXX has the feature
disabled. Write access to the device is unrestricted.
To enable software write protection, the user writes three
access code bytes to three special internal locations.
Once write protection has been enabled, each write to the
EEPROM must use the same three byte write sequence
to permit writing. After setting software data protection,
any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device, however, for the duration
of tWC. The write protection feature can be disabled by
a six byte write sequence of specific data to specific
locations. Power transitions will not reset the software
write protection.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
Each 32KByte block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions,
or unauthorized modification using a PROM programmer.
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
WE32K32-XXX
EXIT DATA
PROTECT STATE(3)
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WE32K32-XXX. These are included to improve reliability
during normal operation:
LOAD LAST BYTE
TO
LAST ADDRESS
a)
VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5msec typical before allowing write cycles.
b)
VCC sense
While below 3.8V typical write cycles are inhibited.
c)
Write inhibiting
Holding OE# low and either CS# or WE# high
inhibits write cycles.
d)
Noise filter
Pulses of <8ns (typ) on WE# or CS# will not initiate
a write cycle.
NOTES:
1. Data Format: I/O15-0 (Hex);
Address Format: A16 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 64 bytes of data may loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
10
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WE32K32-XXX
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) ± 0.25 (0.010) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.60 (0.181)
MAX
3.81 (0.150)
± 0.13 (0.005)
1.42 (0.056) ± 0.13 (0.005)
0.76 (0.030) ± 0.13 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
0.46 (0.018) ± 0.05 (0.002) DIA
25.4 (1.0) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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March 2006
Rev. 4
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WE32K32-XXX
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
25.15 (0.990) ± 0.25 (0.010) SQ
3.51 (0.140) MAX
22.36 (0.880) ± 0.25 (0.010) SQ
0.25 (0.010) ± 0.10 (0.002)
0.25 (0.010) REF
Pin 1
R 0.25
(0.010)
24.0 (0.946)
± 0.25 (0.010)
0.53 (0.021)
± 0.18 (0.007)
1 /7
1.01 (0.040)
± 0.13 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2U
CQFP fills the same fit and
function as the JEDEC 68
lead CQFJ or 68 PLCC.
But the G2U has the TCE
and lead inspection advantage of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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March 2006
Rev. 4
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WE32K32-XXX
ORDERING INFORMATION
W E 32K32 X - XXX X X X
WHITE ELECTRONIC DESIGNS CORP.
EEPROM
ORGANIZATION, 32K x 32
User Configurable as 64Kx16 or 128Kx8
IMPROVEMENT MARK
N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade
ACCESS TIME (ns)
PACKAGE TYPE:
H1 = Ceramic Hex In-line Package, HIP (Package 400)
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP Low Profile (Package 510)
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
32K x 32 EEPROM Module
150ns
66 pin HIP (H1)
5962-94614 01HXX
32K x 32 EEPROM Module
120ns
66 pin HIP (H1)
5962-94614 02HXX
32K x 32 EEPROM Module
90ns
66 pin HIP (H1)
5962-94614 03HXX
32K x 32 EEPROM Module
150ns
68 lead CQFP/J (G2U)
5962-94614 01HZX
32K x 32 EEPROM Module
120ns
68 lead CQFP/J (G2U)
5962-94614 02HZX
32K x 32 EEPROM Module
90ns
68 lead CQFP/J (G2U)
5962-94614 03HZX
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com