ETC WME128K8

White Electronic Designs
WME128K8-XXX
128Kx8 CMOS MONOLITHIC EEPROM, SMD 5962-96796
FEATURES
FIG. 1
■ Read Access Times of 120, 140, 150, 200, 250, 300ns
PIN CONFIGURATION
32 DIP
32 CSOJ
TOP VIEW
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
■ JEDEC Approved Packages
• 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300)
• 32 lead, Hermetic Ceramic, 0.400" SOJ (Package
101)
■ Commercial, Industrial and Military Temperature
Ranges
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
■ MIL-STD-883 Compliant Devices Available
■ Write Endurance 10,000 Cycles
■ Data Retention at 25°C, 10 Years
■ Low Power CMOS Operation
■ Automatic Page Write Operation
• Internal Address and Data Latches for 128 Bytes
• Internal Control Timer
■ Page Write Cycle Time 10ms Max.
■ Data Polling for End of Write Detection
■ Hardware and Software Data Protection
■ TTL Compatible Inputs and Outputs
PIN DESCRIPTION
A0-16
Address Inputs
I/O0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
Vcc
+5.0V Power
VSS
Ground
February 2002 Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WME128K8-XXX
White Electronic Designs
A BSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Any Pin
Voltage on OE and A9
Symbol
TA
TSTG
VG
TRUTH TABLE
Unit
°C
°C
V
V
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
CS
H
L
L
X
X
X
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Symbol
Min
Max
Supply Voltage
VCC
4.5
5.5
V
Input High Voltage
VIH
2.0
VCC + 0.3
V
Input Low Voltage
VIL
-0.3
+0.8
V
Operating Temp. (Mil.)
TA
-55
+125
°C
Operating Temp. (Ind.)
TA
-40
+85
°C
WE
X
H
L
X
H
X
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
CAPACITANCE
(TA = +25°C)
Parameter
RECOMMENDED OPERATING CONDITIONS
Parameter
OE
X
L
H
H
X
L
Input Capacitance
Output Capacitance
Unit
Sym
CIN
COUT
Condition
VIN = 0V, f = 1MHz
VI /O = 0V, f = 1MHz
Unit
Max
20
20
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
Conditions
Unit
Min
Input Leakage Current
Output Leakage Current
Dynamic Supply Current
Standby Current
Output Low Voltage
Output High Voltage
ILI
ILO
I CC
I SB
VOL
VOH
VCC = 5.5, VIN = GND to VCC
CS = VIH, OE = VIH, VOUT = GND to V CC
CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5
CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5
I OL = 2.1mA, Vcc = 4.5V
I OH = -400µA, Vcc = 4.5V
Max
10
10
80
0.625
.45
2.4
µA
µA
mA
mA
V
V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
FIG. 2
AC TEST CONDITIONS
AC TEST CIRCUIT
I OL
Current Source
VZ
D.U.T.
≈ 1.5V
(Bipolar Supply)
C eff = 50 pf
I OH
Current Source
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
2
Parameter
Typ
Input Pulse Levels
VIL = 0, VIH = 3.0
Input Rise and Fall
5
Input and Output Reference Level
1.5
Output Timing Reference Level
1.5
Unit
V
ns
V
V
Notes:
VZ is programmable from -2V to +7V.
I OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 W.
VZ is typically the midpoint of V OH and VOL .
I OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
WME128K8-XXX
White Electronic Designs
READ
Figure 3 shows Read cycle waveforms. A read cycle begins with selection address, chip select and output enable. Chip select is accomplished by placing the CS line
low. Output enable is done by placing the OE line low.
The memory places the selected data byte on I/O0 through
I/O7 after the access time. The output of the memory is
placed in a high impedance state shortly after either the
OE line or CS line is returned to a high level.
FIG. 3 READ WAVEFORMS
t RC
ADDRESS VALID
ADDRESS
CS
t ACS
t OE
OE
t DF
t ACC
t OH
HIGH Z
OUTPUT
OUTPUT
VALID
NOTE:
OE may be delayed up to tACS- tOE after the falling edge of CS
without impact on tOE or by tACC- tOE after an address change without
impact on tACC.
AC READ CHARACTERISTICS (SEE FIGURE 3)
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
-120
Min
-140
Max
Min
120
-150
Max
140
Min
Max
Max
Max
Unit
Max
tRC
tACC
120
140
150
200
250
300
Chip Select Access Time
tACS
120
140
150
200
250
300
Output Hold from Address Change, OE or CS
tOH
Output Enable to Output Valid
tOE
50
55
55
55
85
85
ns
Chip Select or Output Enable to High Z Output
tDF
70
70
70
70
70
70
ns
3
0
250
-300
Min
Address Access Time
0
200
-250
Min
Read Cycle Time
0
150
-200
Min
0
300
0
ns
0
ns
ns
ns
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WME128K8-XXX
White Electronic Designs
WRITE
WRITE CYCLE TIMING
Write operations are initiated when both CS and WE
are low and OE is high. The EEPROM devices support
both a CS and WE controlled write cycle. The address
is latched by the falling edge of either CS or WE, whichever occurs last.
Figures 4 and 5 show the write cycle timing relationships. A write cycle begins with address application,
write enable and chip select. Chip select is accomplished by placing the CS line low. Write enable consists of setting the WE line low. The write cycle begins
when the last of either CS or WE goes low.
The data is latched internally by the rising edge of either CS or WE, whichever occurs first. A byte write
operation will automatically continue to completion.
The WE line transition from high to low also initiates an
internal 150µsec delay timer to permit page mode operation. Each subsequent WE transition from high to
low that occurs before the completion of the 150µsec
time out will restart the timer from zero. The operation
of the timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
128Kx8
Min
Write Cycle Time, TYP = 6ms
Address Set-up Time
Write Pulse Width (WE or CS)
Chip Select Set-up Time
Address Hold Time
Data Hold Time
Chip Select Hold Time
Data Set-up Time
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
tWC
tAS
tWP
tCS
tAH
tDH
tCH
tDS
tOES
t OEH
tWPH
4
10
150
0
100
10
0
100
10
10
50
Unit
Max
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WME128K8-XXX
White Electronic Designs
FIG. 4 WRITE WAVEFORMS WE CONTROLLED
t WC
OE
t OEH
t OES
ADDRESS (1)
t AS
tCSH
t AH
CS
t CS
WE
t WP
t WPH
t DS
t DH
DATA IN
NOTE:
1. Decoded Address Lines must be valid for the duration of the write.
FIG. 5 WRITE WAVEFORMS CS CONTROLLED
t WC
OE
t OEH
t OES
ADDRESS
t AS
WE
tCSH
t AH
t CS
CS
t WP
t WPH
t DS
t DH
DATA IN
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WME128K8-XXX
White Electronic Designs
DATA POLLING
The WME128K8-XXX offers a data polling feature which
allows a faster method of writing to the device. Figure
6 shows the timing diagram for this function. During a
byte or page write cycle, an attempted read of the last
byte written will result in the complement of the written
data on I/O7. Once the write cycle has been completed,
true data is valid on all outputs and the next cycle may
begin. Data polling may begin at any time during the
write cycle.
DATA POLLING CHARACTERISTICS
(VCC = 5.0V, VCC= 0V, TA = -55°C TO +125°C)
Parameter
Data Hold Time
OE Hold Time
OE To Output Valid
Write Recovery Time
Symbol Min
tDH
10
tOEH
10
tOE
tWR
0
Max
55
Unit
ns
ns
ns
ns
FIG. 6 DATA POLLING WAVEFORMS
WE
CS
t OEH
OE
I/O7
t DH
t OE
HIGH Z
t WR
ADDRESS
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
6
WME128K8-XXX
White Electronic Designs
PAGE WRITE OPERATION
PAGE WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
The WME128K8-XXX has a page write operation that
allows one to 128 bytes of data to be written into the
device and consecutively loads during the internal programming period. Successive bytes may be loaded in
the same manner after the first data byte has been
loaded. An internal timer begins a time out operation at
each write cycle. If another write cycle is completed
within 150µs or less, a new time out period begins. Each
write cycle restarts the delay period. The write cycles
can be continued as long as the interval is less than the
time out period.
Page Mode Write Characteristics
Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Address Hold Time (1)
Data Set-up Time
Data Hold Time
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
Symbol
Unit
Min
tWC
tAS
tAH
tDS
tDH
tWP
tBLC
tWPH
Max
10
10
100
100
10
150
150
50
ms
ns
ns
ns
ns
ns
µs
ns
1. Page address must remain valid for duration of write cycle.
The usual procedure is to increment the least significant address lines from A0 through A6 at each write
cycle. In this manner a page of up to 128 bytes can be
loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle.
After the 150µs time out is completed, the EEPROM
begins an internal write cycle. During this cycle the
entire page of bytes will be written at the same time.
The internal programming cycle is the same regardless
of the number of bytes accessed.
FIG. 7 PAGE MODE WRITE WAVEFORMS
OE
CS
t WP
t WPH
t BLC
WE
t AS
ADDRESS
t AH
VALID
ADDRESS
t DS
DATA
VALID DATA
t WC
t DH
BYTE 0
BYTE 1
7
BYTE 2
BYTE 3
BYTE 127
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FIG. 8 SOFTWARE DATA
PROTECTION ENABLE ALGORITHM (1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
NOTES:
1. Data Format: I/O7-I/O0 (Hex);
Address Format: A16 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no
other data is loaded.
3. Write Protect state will be deactivated at end of write period
even if no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
8
WME128K8-XXX
White Electronic Designs
SOFTWARE DATA PROTECTION
FIG. 9 SOFTWARE BLOCK
DATA PROTECTION DISABLE
ALGORITHM
A software write protection feature may be enabled or
disabled by the user. When shipped by White Microelectronics, the WME128K8-XXX has the feature disabled. Write access to the device is unrestricted.
To enable software write protection, the user writes three
access code bytes to three special internal locations.
Once write protection has been enabled, each write to
the EEPROM must use the same three byte write sequence to permit writing. After setting software Data
protection, any attempt to write to the device without
the three-byte command sequence will start the internal write timers. No Data will be written to the device;
however, for the duration of tWC. The write protection
feature can be disabled by a six byte write sequence of
specific data to specific locations. Power transitions
will not reset the software write protection.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
The software write protection guards against inadvertent writes during power transitions or unauthorized
modification using a PROM programmer.
LOAD DATA 55
TO
ADDRESS 2AAA
(3)
EXIT DATA
PROTECT STATE
WME128K8-XXX
LOAD DATA 20
TO
ADDRESS 5555
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WME128K8-XXX. These are included to improve reliability during normal operation:
LOAD DATA XX
TO
ANY ADDRESS(4)
a) VCC power on delay
LOAD LAST BYTE
TO
LAST ADDRESS
As VCC climbs past 3.8V typical the device will wait
5msec typical before allowing write cycles.
b) VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE low and either CS or WE high inhibits
write cycles.
d) Noise filter
Pulses of <15ns (typ) on WE or CS will not initiate a
write cycle.
NOTES:
1. Data Format: I/O7-I/O0 (Hex);
Address Format: A16 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no
other data is loaded.
3. Write Protect state will be deactivated at end of write period
even if no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WME128K8-XXX
White Electronic Designs
PACKAGE 101: 32 LEAD, CERAMIC SOJ
3.96 (0.156) MAX
21.1 (0.830) ± 0.25 (0.010)
0.89 (0.035)
Radius TYP
0.2 (0.008)
± 0.05 (0.002)
11.3 (0.446)
± 0.2 (0.009)
9.55 (0.376) ± 0.25 (0.010)
1.27 (0.050) ± 0.25 (0.010)
PIN 1 IDENTIFIER
1.27 (0.050) TYP
19.1 (0.750) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
42.4 (1.670) ± 0.4 (0.016)
15.04 (0.592)
± 0.3 (0.012)
4.34 (0.171) ± 0.79 (0.031)
PIN 1 IDENTIFIER
0.84 (0.033)
± 0.4 (0.014)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
10
White Electronic Designs
WME128K8-XXX
ORDERING INFORMATION
W M E 128K8 - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M = Military Screened
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
PACKAGE TYPE:
C = 32 Pin Ceramic DIP (Package 300)
DE = 32 Lead CSOJ (Package 101)
ACCESS TIME (ns)
ORGANIZATION 128K x 8
EEPROM
MONOLITHIC
WHITE ELECTRONIC DESIGNS CORP.
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
128K x 8 EEPROM Monolithic
300ns
32 pin DIP (C)
5962-96796 01HYX
128K x 8 EEPROM Monolithic
250ns
32 pin DIP (C)
5962-96796 02HYX
128K x 8 EEPROM Monolithic
200ns
32 pin DIP (C)
5962-96796 03HYX
128K x 8 EEPROM Monolithic
150ns
32 pin DIP (C)
5962-96796 04HYX
128K x 8 EEPROM Monolithic
140ns
32 pin DIP (C)
5962-96796 05HYX
128K x 8 EEPROM Monolithic
120ns
32 pin DIP (C)
5962-96796 06HYX
128K x 8 EEPROM Monolithic
300ns
32 lead SOJ (DE)
5962-96796 01HXX
128K x 8 EEPROM Monolithic
250ns
32 lead SOJ (DE)
5962-96796 02HXX
128K x 8 EEPROM Monolithic
200ns
32 lead SOJ (DE)
5962-96796 03HXX
128K x 8 EEPROM Monolithic
150ns
32 lead SOJ (DE)
5962-96796 04HXX
128K x 8 EEPROM Monolithic
140ns
32 lead SOJ (DE)
5962-96796 05HXX
128K x 8 EEPROM Monolithic
120ns
32 lead SOJ (DE)
5962-96796 06HXX
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com