WEDC WE512K16

White Electronic Designs
WE512K16-XG4X
512Kx16 CMOS EEPROM MODULE
FEATURES
Access Time of 140, 150, 200ns
Page Write Cycle Time: 10ms Max
Packaging:
Data Polling for End of Write Detection
• 68 lead, 40mm Hermetic CQFP (Package 501)
Hardware and Software Data Protection
Organized as 4 banks of 128Kx16
TTL Compatible Inputs and Outputs
Write Endurance 10,000 Cycles
5 Volt Power Supply
Data Retention Ten Years Minimum
Military Temperature Range
8 Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
Low Power CMOS
Weight - 20 grams typical
Automatic Page Write Operation
FIGURE 1 – PIN CONFIGURATION
Top View
Pin Description
NC
A0
A1
A2
A3
A4
A5
CS1#
GND
CS3#
WE#
A6
A7
A8
A9
A10
VCC
I/O0-15
A0-16
WE#
CS1-4#
OE#
VCC
GND
NC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NC
NC
INC
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
+5.0V Power
Ground
Not Connected
Block Diagram
CS 1 #
CS 2 #
CS 3 #
CS 4 #
A0-16
OE#
WE#
VCC
A11
A12
A13
A14
A15
A16
CS2#
OE#
CS4#
NC
NC
NC
NC
NC
NC
NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
I/O0-7
I/O8-15
NOTE: CS1-4# are used as bank selects. During reads, only one CSx#
can be active at one time.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
1
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White Electronic Designs
WE512K16-XG4X
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE# and A9
Symbol
TA
TSTG
VG
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
TRUTH TABLE
Unit
°C
°C
V
V
CS#
H
L
L
X
X
X
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Symbol
VCC
VIH
VIL
TA
Min
4.5
2.0
-0.3
-55
Max
5.5
VCC + 0.3
+0.8
+125
WE#
X
H
L
X
H
X
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
CAPACITANCE
TA = +25°C
Parameter
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
OE#
X
L
H
H
X
L
Unit
V
V
V
°C
Symbol
Conditions
Max Unit
OE capacitance
COE
VIN = 0 V, f = 1.0 MHz
50
pF
WE capacitance
CWE
VIN = 0 V, f = 1.0 MHz
50
pF
CS1-4 capacitance
CCS
VIN = 0 V, f = 1.0 MHz
25
pF
Data I/O capacitance
CI/O
VI/O = 0 V, f = 1.0 MHz
40
pF
Address input capacitance
CAD
VIN = 0 V, f = 1.0 MHz
70
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current (x16)
Chip Erase Current
Standby Current
Output Low Voltage
Output High Voltage
Symbol
ILI
ILO
ICCx16
ICC1
ISB
VOL
VOH
Conditions
VCC = 5.5, VIN = GND to VCC
CS# = VIH, OE# = VIH, Vout = GND to VCC
CS1# = VIL, OE# = CS2-4# = VIH, f = 5MHz, VCC = 5.5
CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5
CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
IOL = 2.1mA, VCC = 4.5V
IOH = -400µA, VCC = 4.5V
Min
Max
10
10
160
250
5
0.45
2.4
Unit
µA
µA
mA
mA
mA
V
V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
FIGURE 4
AC Test Circuit
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
VIL = 0, VIH = 3.0
5
1.5
1.5
Unit
V
ns
V
V
Notes: VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
2
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White Electronic Designs
WE512K16-XG4X
AC WRITE CHARACTERISTICS
WRITE
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
A write cycle is initiated when OE# is high and a low pulse
is on WE# or CS# with CS# or WE# low. The address
is latched on the falling edge of CS# or WE# whichever
occurs last. The data is latched by the rising edge of CS#
or WE#, whichever occurs first. A word write operation will
automatically continue to completion.
Write Cycle Parameter
Symbol
Min
Max
Unit
10
ms
Write Cycle Time, TYP = 6ms
tWC
Address Set-up Time
tAS
10
ns
ns
Write Pulse Width (WE# or CS#)
tWP
120
Chip Select Set-up Time
tCS
0
ns
WRITE CYCLE TIMING
Address Hold Time
tAH
100
ns
Figures 3 and 4 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
Data Hold Time
tDH
10
ns
Chip Select Hold Time
tCSH
0
ns
Data Set-up Time
tDS
100
ns
Output Enable Set-up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
The WE# line transition from high to low also initiates
an internal 150 µsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150 µsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
Write Pulse Width High
tWPH
50
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WE512K16-XG4X
FIGURE 3 – WRITE WAVEFORM WE# CONTROLLED
OE#
ADDRESS
CS1-4#
WE#
DATA IN
FIGURE 4 – WRITE WAVEFORM CS# CONTROLLED
OE#
ADDRESS
WE#
CS1-4#
DATA IN
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
4
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White Electronic Designs
WE512K16-XG4X
READ
The module stores data at the memory location determined
by the address pins. When CS# and OE# are low and WE#
is high, this data is present on the outputs. When CS# and
OE# are high, the outputs are in a high impedance state.
This two line control prevents bus contention.
AC READ CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or OE# to High Z Output
trc
tacc
tacs
toh
toe
tdf
-140
Min
140
-150
Max
Min
150
140
140
0
0
Min
200
150
150
0
0
50
50
-200
Max
55
70
Max
200
200
0
0
55
70
Unit
ns
ns
ns
ns
ns
ns
FIGURE 5 – READ WAVEFORMS
ADDRESS
CS#
OE#
OUTPUT
Notes:
OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact
on tOE or by tACC - toe after an address change without impact on tACC.
CS1-4# are used as bank selects.
During reads, only one CSx# can be active at one time.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WE512K16-XG4X
DATA POLLING
The module offers a data polling feature which allows a
faster method of writing to the device. Figure 6 shows the
timing diagram for this function. During a word or page
write cycle, an attempted read of the last word written will
result in the complement of the written data on I/O7 and
I/O15. Once the write cycle has been completed, true data
is valid on all outputs and the next cycle may begin. Data
polling may begin at any time during the write cycle.
DATA POLLING CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
Min
Data Hold Time
tDH
10
OE# Hold Time
tOEH
10
OE# To Output Valid
tOE
Write Recovery Time
tWR
Max
ns
ns
55
0
Unit
ns
ns
FIGURE 6 – DATA POLLING WAVEFORM
WE1-4#
CS1-4#
OE#
I/O7
ADDRESS
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WE512K16-XG4X
PAGE WRITE CHARACTERISTICS
PAGE WRITE OPERATION
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
The module has a page write operation that allows one
to 128 words of data to be written into the device and
consecutively loads during the internal programming
period. Successive words may be loaded in the same
manner after the first data word has been loaded. An
internal timer begins a time out operation at each write
cycle. If another write cycle is completed within 150µs
or less, a new time out period begins. Each write cycle
restarts the delay period. The write cycles can be continued
as long as the interval is less than the time out period.
Page Mode Write Characteristics
Symbol
Parameter
Min
Write Cycle Time, TYP = 6ms
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In this
manner a page of up to 128 words can be loaded in to the
EEPROM in a burst mode before beginning the relatively
long interval programming cycle.
Unit
Max
10
tWC
ms
Address Set-up Time
tAS
0
ns
Address Hold Time (1)
tAH
50
ns
Data Set-up Time
tDS
50
ns
Data Hold Time
tDH
0
ns
100
Write Pulse Width
tWP
Word Load Cycle Time
tBLC
Write Pulse Width High
tWPH
ns
150
50
µs
ns
1. Page address must remain valid for duration of write cycle.
After the 150µs time out is completed, the EEPROM begins
an internal write cycle. During this cycle the entire page
of words will be written at the same time. The internal
programming cycle is the same regardless of the number
of words accessed.
FIGURE 7 – PAGE MODE WRITE WAVEFORM
OE#
CS#
WE#
tAS
ADDRESS (1)
tAH
VALID
ADDRESS
DATA
WORD 0
WORD 1
WORD 2
WORD 3
WORD 126
WORD 127
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
7
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White Electronic Designs
WE512K16-XG4X
FIGURE 8 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM(1)
LOAD DATA AAAA
TO
ADDRESS 5555
LOAD DATA 5555
TO
ADDRESS 2AAA
LOAD DATA A0A0
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XXXX
TO
ANY ADDRESS(4)
LOAD LAST WORD
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
NOTES:
1. Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data is loaded.
4. 1 to 128 words of data to be loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 9 –
SOFTWARE BLOCK DATA PROTECTION
DISABLE ALGORITHM(1)
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled
or disabled by the user. When shipped by White
Microelectronics, the module has the feature disabled.
Write access to the device is unrestricted.
To enable software write protection, the user writes three
access code words to three special internal locations.
Once write protection has been enabled, each write to the
EEPROM must use the same three-word write sequence
to permit writing. After setting software data protection,
any attempt to write to the device without the three-word
command sequence will start the internal write timers. No
data will be written to the device, however, for the duration
of tWC. The write protection feature can be disabled by
a six-word write sequence of specific data to specific
locations. Power transitions will not reset the software
write protection.
LOAD DATA AAAA
TO
ADDRESS 5555
LOAD DATA 5555
TO
ADDRESS 2AAA
LOAD DATA 8080
TO
ADDRESS 5555
LOAD DATA AAAA
TO
ADDRESS 5555
Each 128K-word block of the EEPROM has independent
write protection. One or more blocks may be enabled and
the rest disabled in any combination. The software write
protection guards against inadvertent writes during power
transitions, or unauthorized modification using a PROM
programmer.
LOAD DATA 5555
TO
ADDRESS 2AAA
LOAD DATA 2020
TO
ADDRESS 5555
LOAD DATA XXXX
TO
ANY ADDRESS(4)
WE512K16-XG4X
EXIT DATA
HARDWARE DATA PROTECTION
PROTECT STATE(3)
These features protect against inadvertent writes to the
module. These are included to improve reliability during
normal operation:
LOAD LAST WORD
TO
LAST ADDRESS
a)
VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5 msec typical before allowing write cycles.
b)
VCC sense
c)
Write inhibiting
While below 3.8V typical write cycles are inhibited.
Holding OE# low and either CS# or WE# high
inhibits write cycles.
d)
Noise filter
Pulses of <8ns (typ) on WE# or CS# will not initiate
a write cycle.
NOTES:
1. Data Format: I/O15-0 (Hex);
Address Format: A16 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 words of data may loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WE512K16-XG4X
PACKAGE 501: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G4)
5.1 (0.200) MAX
39.6 (1.56) ± 0.38 (0.015) SQ
1.27 (0.050)
± 0.1 (0.005)
PIN 1 IDENTIFIER
Pin 1
12.7 (0.500)
± 0.5 (0.020)
4 PLACES
5.1 (0.200)
± 0.25 (0.010)
4 PLACES
1.27 (0.050)
TYP
0.25 (0.010)
± 0.05 (0.002)
0.38 (0.015)
± 0.08 (0.003)
68 PLACES
38 (1.50) TYP
4 PLACES
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
W E 512K16 - XXX G4 X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
PROCESSING:
Q = MIL-STD-883 Compliant
M = Military Screened
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
PACKAGE:
G4 = 40mm Ceramic Quad Flat Pack, CQFP (Package 501)
ACCESS TIME (ns)
ORGANIZATION, 4 banks of 128Kx16
EEPROM
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com