WE512K8, WE256K8, WE128K8-XCX 512Kx8 CMOS EEPROM, WE512K8-XCX, SMD 5962-93091 512KX8 BIT CMOS EEPROM MODULE FIG. 1 PIN CONFIGURATION TOP VIEW FEATURES ■ Read Access Times of 150, 200, 250, 300ns ■ JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package 300) ■ Commercial, Industrial and Military Temperature Ranges ■ MIL-STD-883 Compliant Devices Available ■ Write Endurance 10,000 Cycles ■ Data Retention at 25°C, 10 Years ■ Low Power CMOS Operation: 3mA Standby Typical/100mA Operating Maximum ■ Automatic Page Write Operation Internal Address and Data Latches for 512 Bytes, 1 to 128 Bytes/Row, Four Pages PIN DESCRIPTION ■ Page Write Cycle Time 10mS Max. A0-18 Address Inputs I/O0- 7 Data Input/Output ■ Data Polling for End of Write Detection CS Chip Select ■ Hardware and Software Data Protection OE Output Enable WE Write Enable VCC +5.0V Power VSS Ground ■ TTL Compatible Inputs and Outputs BLOCK DIAGRAM May 2000 Rev.1 1 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WE512K8, WE256K8, WE128K8-XCX 256Kx8 CMOS EEPROM, WE256K8-XCX, SMD 5962-93155 256KX8 BIT CMOS EEPROM MODULE FIG.2 PIN CONFIGURATION TOP VIEW FEATURES ■ Read Access Times of 150, 200ns ■ JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package 302) ■ Commercial, Industrial and Military Temperature Ranges ■ MIL-STD-883 Compliant Devices Available ■ Write Endurance 10,000 Cycles ■ Data Retention at 25°C, 10 Years ■ Low Power CMOS Operation: 2mA Standby Typical/90mA Operating Maximum ■ Automatic Page Write Operation Internal Address and Data Latches for 512 Bytes, 1 to 64 Bytes/Row, Eight Pages PIN DESCRIPTION ■ Page Write Cycle Time 10mS Max. A0-17 Address Inputs I/O0-7 Data Input/Output ■ Data Polling for End of Write Detection CS Chip Select ■ Hardware and Software Data Protection OE Output Enable WE Write Enable VCC +5.0V Power VSS Ground ■ TTL Compatible Inputs and Outputs BLOCK DIAGRAM White Electronic Designs Corporation Phoenix AZ (602) 437-1520 2 WE512K8, WE256K8, WE128K8-XCX 128Kx8 CMOS EEPROM, WE128K8-XCX, SMD 5962-93154 128KX8 BIT CMOS EEPROM MODULE FIG. 3 PIN CONFIGURATION TOP VIEW FEATURES ■ Read Access Times of 150, 200ns ■ JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package 300) ■ Commercial, Industrial and Military Temperature Ranges ■ MIL-STD-883 Compliant Devices Available ■ Write Endurance 10,000 Cycles ■ Data Retention at 25°C, 10 Years ■ Low Power CMOS Operation: 1mA Standby Typical/70mA Operating ■ Automatic Page Write Operation Internal Address and Data Latches for 256 Bytes, 1 to 64 Bytes/Row, Four Pages PIN DESCRIPTION ■ Page Write Cycle Time 10mS Max. A0-16 Address Inputs I/O0-7 Data Input/Output ■ Data Polling for End of Write Detection CS Chip Select ■ Hardware and Software Data Protection OE Output Enable WE Write Enable VCC +5.0V Power VSS Ground ■ TTL Compatible Inputs and Outputs BLOCK DIAGRAM 3 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WE512K8, WE256K8, WE128K8-XCX A BSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Any Pin Voltage on OE and A9 Thermal Resistance junction to case Lead Temperature (soldering -10 secs) Symbol TA TSTG VG qJC TRUTH TABLE -55 to +125 -65 to +150 -0.6 to + 6.25 -0.6 to +13.5 28 Unit °C °C V V °C/W +300 °C OE WE Mode Data I/O H L L X X X X L H H X L X H L X H X Standby Read Write Out Disable Write Inhibit High Z Data Out Data In High Z/Data Out CAPACITANCE (TA = +25°C) NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Sym Condition 512Kx8 256Kx8 128Kx8 Unit Max Max Max Input Capacitance CIN VIN = 0V, f = 1MHz 45 80 45 pF Output Capacitance COUT VI/O = 0V, f = 1MHz 60 80 60 pF This parameter is guaranteed by design but not tested. RECOMMENDED OPERATING CONDITIONS Parameter CS Symbol Min Max Supply Voltage VCC 4.5 5.5 Unit V Input High Voltage VIH 2.0 VCC + 0.3 V Input Low Voltage VIL -0.3 +0.8 V Operating Temp. (Mil.) TA -55 +125 °C Operating Temp. (Ind.) TA -40 +85 °C DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Symbol Conditions 512K x 8 Min Typ Max 256K x 8 Min Typ Max 128K x 8 Unit Min Typ Max Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 10 10 Output Leakage Current I LO CS = VIH, OE = VIH, VOUT = GND to V CC 10 10 10 µA Dynamic Supply Current I CC CS = VIL, OE = VIH, f = 5MHz, VCC = 5.5 80 70 mA Standby Current ISB CS = VIL, OE = VIH, f = 5MHz, VCC = 5.5 3 4 mA Output Low Voltage VOL I OL = 2.1mA, VCC = 4.5V Output High Voltage VOH I OH = -400µA, VCC = 4.5V 100 60 8 2 0.45 2.4 90 50 6 1 0.45 2.4 µA 0.45 2.4 V V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V AC TEST CONDITIONS FIG. 4 AC TEST CIRCUIT Parameter Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns 1.5 1.5 V V Input and Output Reference Level Output Timing Reference Level Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 ý. VZ is typically the midpoint of VOH and VOL . IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corporation Phoenix AZ (602) 437-1520 4 WE512K8, WE256K8, WE128K8-XCX READ Figure 5 shows Read cycle waveforms. A read cycle begins with selection address, chip select and output enable. Chip select is accomplished by placing the CS line low. Output enable is done by placing the OE line low. The memory places the selected data byte on I/O0 through I/O7 after the access time. The output of the memory is placed in a high impedance state shortly after either the OE line or CS line is returned to a high level. FIG. 5 READ WAVEFORMS NOTE: OE may be delayed up to tACS-tOE after the falling edge of CS without impact on tOE or by tACC -tOE after an address change without impact on tACC. AC READ CHARACTERISTICS (SEE FIGURE 5) FOR WE512K8-XCX (VCC= 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Symbol -150 Min -200 Max 150 Min -250 Max 200 Min -300 Max Unit Max Read Cycle Time tRC Address Access Time tACC 150 200 250 300 Chip Select Access Time tACS 150 200 250 300 Output Hold from Address Change, OE or CS tOH Output Enable to Output Valid tOE 85 85 100 125 ns Chip Select or Output Enable to High Z Output tDF 70 70 70 70 ns 0 250 Min 0 300 0 ns 0 ns ns ns FOR WE256K8-XCX AND WE128K8-XCX Parameter Symbol -150 Min -200 Max 150 Min Unit Max Read Cycle Time tRC Address Access Time tACC 200 Chip Select Access Time tACS Output Hold from Address Change, OE or CS tOH Output Enable to Output Valid tOE 85 100 ns Chip Select or Output Enable to High Z Output tDF 70 70 ns 150 150 10 5 ns 200 200 10 ns ns ns White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WE512K8, WE256K8, WE128K8-XCX WRITE CYCLE TIMING WRITE Figures 6 and 7 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS or WE goes low. Write operations are initiated when both CS and WE are low and OE is high. The EEPROM devices support both a CS and WE controlled write cycle. The address is latched by the falling edge of either CS or WE, whichever occurs last. The data is latched internally by the rising edge of either CS or WE, whichever occurs first. A byte write operation will automatically continue to completion. The WE line transition from high to low also initiates an internal 150µsec delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the 150µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. AC WRITE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Write Cycle Time, TYP = 6mS Address Set-up Time Write Pulse Width (WE or CS) Chip Select Set-up Time Address Hold Time (1) Data Hold Time Chip Select Hold Time Data Set-up Time Output Enable Set-up Time Output Enable Hold Time Write Pulse Width High Symbol tWC tAS tWP tCS tAH tDH tCH tDS tOES tOEH tWPH 512K x 8 Min Max 10 10 150 0 125 10 0 100 10 10 50 256K x 8 Min Max 10 30 150 0 50 0 0 100 30 0 50 NOTES: 1. A17 and A18 must remain valid through WE and CS low pulse, for 512K x 8. A15 , A16, and A17 must remain valid through WE and CS low pulse, for 256K x 8. A15 and A16 must remain valid through WE and CS low pulse, for 128K x 8. White Electronic Designs Corporation Phoenix AZ (602) 437-1520 6 128K x 8 Min Max 10 30 150 0 50 0 0 100 30 0 50 Unit ms ns ns ns ns ns ns ns ns ns ns WE512K8, WE256K8, WE128K8-XCX FIG. 6 WRITE WAVEFORMS WE CONTROLLED NOTE: 1. Decoded Address Lines must be valid for the duration of the write. FIG. 7 WRITE WAVEFORMS CS CONTROLLED NOTE: 1. Decoded Address Lines must be valid for the duration of the write. 7 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WE512K8, WE256K8, WE128K8-XCX DATA POLLING Data polling allows a simple bit test operation to determine the status of the EEPROM. During the internal programming cycle, a read of the last byte written will produce the complement of the data on I/O7. For example, if the data written consisted of I/O7 = HIGH, then the data read back would consist of I/O7 = LOW. Operation with data polling permits a faster method of writing to the EEPROM. The actual time to complete the memory programming cycle is faster than the guaranteed maximum. The EEPROM features a method to determine when the internal programming cycle is completed. After a write cycle is initiated, the EEPROM will respond to read cycles to provide the microprocessor with the status of the programming cycle. The status consists of the last data byte written being returned with data bit I/O 7 complemented during the programming cycle, and I/O7 true after completion. A polled byte write sequence would consist of the following steps: 1. write byte to EEPROM 2. store last byte and last address written 3. release a time slice to other tasks 4. read byte from EEPROM - last address 5. compare I/O7 to stored value a) If different, write cycle is not completed, go to step 3. b) If same, write cycle is completed, go to step 1 or step 3. DATA POLLING AC CHARACTERISTICS (VCC = 5.0V, VCC = 0V, TA = -55°C TO +125°C) Parameter Symbol 512Kx8 256Kx8 128Kx8 Unit Min Max Min Max Min Data Hold Time tDH 10 0 0 Output Enable Hold Time tOEH 10 0 0 Output Enable To Output Delay tOE Write Recovery Time tWR 100 100 0 0 FIG. 8 DATA POLLING WAVEFORMS White Electronic Designs Corporation Phoenix AZ (602) 437-1520 8 Max ns ns 100 0 ns ns WE512K8, WE256K8, WE128K8-XCX PAGE WRITE OPERATION The page address must be the same for each byte load and must be valid during each high to low transition of WE (or CS). The block address also must be the same for each byte load and must remain valid throughout the WE (or CS) low pulse. The page and block address lines are summarized below: These devices have a page write operation that allows one to 64 bytes of data (one to 128 bytes for the WE512K8) to be written into the device and then simultaneously written during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150µs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. PAGE MODE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter The usual procedure is to increment the least significant address lines from A0 through A5 (A0 through A6 for the WE512K8) at each write cycle. In this manner a page of up to 64 bytes (128 bytes for the WE512K8) can be loaded into the EEPROM in a burst mode before beginning the relatively long interval programming cycle. Min Max Unit tWC Data Set-up Time tDS 100 ns Data Hold Time tDH 10 ns Write Pulse Width tWP 150 Byte Load Cycle Time tBLC Write Pulse Width High tWPH Device After the 150µs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. Symbol Write Cycle Time, TYP = 6mS 10 ms ns 150 50 µs ns Block Address Page Address WE512K8-XCX A17-A18 A7 -A16 WE256K8-XCX A15-A17 A6 -A14 WE128K8-XCX A15-A16 A6 -A14 FIG. 9 PAGE WRITE WAVEFORMS NOTE: 1. Decoded Address Lines must be valid for the duration of the write. 9 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WE512K8, WE256K8, WE128K8-XCX FIG. 10 SOFTWARE BLOCK DATA PROTECTION ENABLE A LGORITHM LOAD DATA AA TO ADDRESS 5555 (1) LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE ENTER DATA TO LAST ADDRESS PROTECT STATE NOTES: 1. Data Format: I/O7-0 (Hex); Address Format: A14 -A0 (Hex). A17 and A18 control selection of one of four blocks in the 512Kx8. A15 , A16, and A17 control selection of one of 8 pages in the 256Kx8. A15 and A16 control one of the four blocks in the 128Kx8. 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512Kx8. 1 to 64 bytes of data at each of 8 blocks may be loaded in the 256Kx8 and 1 to 64 bytes on 4 blocks in the 128Kx8. White Electronic Designs Corporation Phoenix AZ (602) 437-1520 10 WE512K8, WE256K8, WE128K8-XCX SOFTWARE DATA PROTECTION FIG. 11 SOFTWARE BLOCK DATA PROTECTION DISABLE A LGORITHM LOAD DATA AA TO ADDRESS 5555 A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the devices have the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. (1) LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 Each 32K byte block (128K bytes for the WE512K8) of EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions or unauthorized modification using a PROM programmer. The block selection is controlled by the upper most address lines (A17 through A18 for the WE512K8, A15 through A17 for the WE256K8, or A15 and A16 for the WE128K8). LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) EXIT DATA PROTECT STATE(3) HARDWARE DATA PROTECTION LOAD LAST BYTE TO LAST ADDRESS Several methods of hardware data protection have been implemented in the White Microelectronics EEPROM. These are included to improve reliability during normal operations. a) VCC power on delay As VCC climbs past 3.8V typical the device will wait 5mSec typical before allowing write cycles. NOTES: 1. Data Format: I/O7-0 (Hex); Address Format: A14 -A0 (Hex). A17 and A18 control selection of one of four blocks in the 512Kx8. A15, A16 , and A17 control selection of one of 8 pages in the 256Kx8. A15 and A16 control one of the four blocks in the 128Kx8. 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512Kx8. 1 to 64 bytes of data at each of 8 blocks may be loaded in the 256Kx8 and 1 to 64 bytes on 4 blocks in the 128Kx8. b) VCC sense While below 3.8V typical write cycles are inhibited. c) Write inhibiting Holding OE low and either CS or WE high inhibits write cycles. d) Noise filter Pulses of <8ns (typ) on WE or CS will not initiate a write cycle. 11 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WE512K8, WE256K8, WE128K8-XCX PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 302: 32 PIN, CERAMIC DIP, DUAL CAVITY BOTTOM BRAZED ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corporation Phoenix AZ (602) 437-1520 12 WE512K8, WE256K8, WE128K8-XCX ORDERING INFORMATION W E XXXK8 - XXX C X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads PROCESSING: Q = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE: C = Ceramic DIP (Package 300 for 128Kx8) (Package 302 for 256Kx8) (Package 300 for 512Kx8) ACCESS TIME (ns) ORGANIZATION, 512Kx8, 256Kx8 or 128Kx8 EEPROM WHITE ELECTRONIC DESIGNS DEVICE TYPE SPEED PACKAGE WM PART NO. SMD NO. 512K x 8 EEPROM 150ns 32 pin DIP (C) WE512K8-150CQ 5962-93091 01HYX 512K x 8 EEPROM 300ns 32 pin DIP (C) WE512K8-300CQ 5962-93091 02HYX 512K x 8 EEPROM 250ns 32 pin DIP (C) WE512K8-250CQ 5962-93091 03HYX 512K x 8 EEPROM 200ns 32 pin DIP (C) WE512K8-200CQ 5962-93091 04HYX 256K x 8 EEPROM 200ns 32 pin DIP (C) WE256K8-200CQ 5962-93155 01HYX 256K x 8 EEPROM 150ns 32 pin DIP (C) WE256K8-150CQ 5962-93155 02HYX 128K x 8 EEPROM 200ns 32 pin DIP (C) WE128K8-200CQ 5962-93154 01HXX 128K x 8 EEPROM 150ns 32 pin DIP (C) WE128K8-150CQ 5962-93154 02HXX DEVICE TYPE WM PART NO. SPEED PACKAGE SMD NO. 13 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com