WED3DG72256V-D2 2GB- 256Mx72 SDRAM W/ PLL, REGISTER AND SPD FEATURES DESCRIPTION n Burst Mode Operation The WED3DG72256V is a 256Mx72 synchronous DRAM module which consists of eighteen 256M x 4 stack SDRAM components in TSOP- 11 package, two 18- bit Drive ICs for input control signal and one 2K EEPROM in an 8- pin TSSOP package for Serial Presence Detect which are mounted on a 168 Pin DIMM multilayer FR4 Substrate. n Auto and Self Refresh capability n LVTTL compatible inputs and outputs n Serial Presence Detect with EEPROM n Fully synchronous: All signals are registered on the positive edge of the system clock n Programmable Burst Lengths: 1, 2, 4, 8 or Full Page n 3.3 volt 6 0.3v Power Supply n 168- Pin DIMM JEDEC * This datasheet describes a product that may or may not be under development and is subject to change or cancellation without notice. PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Sept. 2002 Rev. 0 ECO #15460 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 CS0 DNU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD CLK0 VSS DNU CS2 DQM2 DQM3 DNU VDD NC NC CB2 CB3 VSS DQ16 DQ17 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VDD DQ20 NC *VREF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS *CLK2 NC NC **SDA **SCL VDD Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 PIN NAMES Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD *CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 1 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS *CLK3 NC **SA0 **SA1 **SA2 VDD A0 A12 BA0-1 DQ0-63 CB0-7 CLK0 CKE0 CS0-CS3 RAS CAS WE DQM0-7 VDD VSS *VREF REGE SDA SCL SA0-2 DNU NC Address input (Multiplexed) Select Bank Data Input/Output Check bit (Data-in/data-out) Clock input Clock Enable input Chip select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Do not use No Connect * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DG72256V-D2 FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQMB0 # DQMB4 DQ0 DQ1 DQ2 DQ3 DQM CS I/O 0 I/O 1 D0 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D18 I/O 2 I/O 3 DQ32 DQ33 DQ34 DQ35 DQM CS I/O 0 I/O 1 D9 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D27 I/O 2 I/O 3 DQ4 DQ5 DQ6 DQ7 DQM CS I/O 0 I/O 1 D1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D19 I/O 2 I/O 3 DQ36 DQ37 DQ38 DQ39 DQM CS I/O 0 I/O 1 D10 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D28 I/O 2 I/O 3 DQMB5 DQMB1 DQ8 DQ9 DQ10 DQ11 DQM CS I/O 0 I/O 1 D2 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D20 I/O 2 I/O 3 DQ40 DQ41 DQ42 DQ43 DQM CS I/O 0 I/O 1 D11 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D29 I/O 2 I/O 3 DQ12 DQ13 DQ14 DQ15 DQM CS I/O 0 I/O 1 D3 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D21 I/O 2 I/O 3 DQ44 DQ45 DQ46 DQ47 DQM CS I/O 0 I/O 1 D12 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D30 I/O 2 I/O 3 CB0 CB1 CB2 CB3 DQM CS I/O 0 I/O 1 D4 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D22 I/O 2 I/O 3 CB4 CB5 CB6 CB7 DQM CS I/O 0 I/O 1 D13 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D31 I/O 2 I/O 3 CS3 CS2 DQMB2 DQMB6 DQ16 DQ17 DQ18 DQ19 DQM CS I/O 0 I/O 1 D5 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D23 I/O 2 I/O 3 DQ48 DQ49 DQ50 DQ51 DQM CS I/O 0 I/O 1 D14 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D32 I/O 2 I/O 3 DQ20 DQ21 DQ22 DQ23 DQM CS I/O 0 I/O 1 D6 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D24 I/O 2 I/O 3 DQ52 DQ53 DQ54 DQ55 DQM CS I/O 0 I/O 1 D15 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D33 I/O 2 I/O 3 DQMB7 DQMB3 DQ24 DQ25 DQ26 DQ27 DQM CS I/O 0 I/O 1 D7 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D25 I/O 2 I/O 3 DQ56 DQ57 DQ58 DQ59 DQM CS I/O 0 I/O 1 D16 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D34 I/O 2 I/O 3 DQ28 DQ29 DQ30 DQ31 DQM CS I/O 0 I/O 1 D8 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D26 I/O 2 I/O 3 DQ60 DQ61 DQ62 DQ63 DQM CS I/O 0 I/O 1 D17 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 D35 I/O 2 I/O 3 SERIAL PD CS0-CS3 DQMB0 to DQMB7 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 WE REGE PCK R E G I S T E R RS0-RS3 RDQMB0 - RDQMB7 BA0-BAN: SDRAMS D0-D35 RBA0 - RBAN A0-AN: SDRAMS D0-D35 RA0-RAN RRAS RAS: SDRAMS D0 - D35 CAS: SDRAMS D0 - D35 RCAS CKE: SDRAMS D0 - D17 RCKE0 CKE: SDRAMS D18 - D35 RCKE1 WE: SDRAMS D0 - D35 RWE * Wire per Clock Loading Table/Wiring Diagrams SCL SDA A0 A1 A2 SA0 SA1 SA2 VCC D0 - D35 D0 - D35 VSS NOTE: DQ wiring may differ than described in this drawing, however DQ/DQMB/CKE/S relationships must be maintained as shown. # NOTE: ALL RESISTOR VALUES ARE 10 OHMS. - White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 2 3 Sept. 2002 Rev. 0 ECO #15460 WED3DG72256V-D2 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, Vout VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 36 50 Units V V °C W mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C) Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VDD VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ Max Unit 3.3 3.6 V 3.0 VDDQ+0.3 V 0.8 V V 0.4 V 10 µA Note 1 2 IOH= -2mA IOL= -2mA 3 Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is £ 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is £ 3ns. 3. Any input 0V £ VIN £ VDDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (TA = 23°C, f = 1MHz, VDD = 3.3V, VREF=1.4V 6200mV) Parameter Input Capacitance (A0-A12) Input Capacitance (RAS,CAS,WE) Input Capacitance (CKE0) Input Capacitance (CLK0) Input Capacitance (CS0,CS2) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63) Data input/output capacitance (CB0-CB7) Sept. 2002 Rev. 0 ECO #15460 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 Cout Cout1 3 Min - Max 15 15 15 20 15 15 15 22 22 Unit pF pF pF pF pF pF pF pF pF White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DG72256V-D2 OPERATING CURRENT CHARACTERISTICS (VCC = 3.3V, TA = 0°C to +70°C) Parameter Operating Current (One bank active) Symbol ICC1 Precharge Standby Current in Power Down Mode ICC2P ICC2PS Icc2N Precharge Standby Current in Non-Power Down Mode Active standby current in power-down mode Active standby current in non power-down mode Icc2NS ICC3P ICC3PS ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Conditions Burst Length = 1 tRC ³ tRC(min) IOL = 0mA CKE £ VIL(max), tCC = 10ns CKE & CLK £ VIL(max), tCC = ¥ CKE ³ VIH(min), CS ³ VIH(min), tcc = 10ns Input signals are charged one time during 20 CKE ³ VIH(min), CLK £ VIL(max), tcc = ¥ Input signals are stable CKE ³ VIL(max), tCC = 10ns CKE & CLK £ VIL(max), tcc = ¥ CKE ³ VIH(min), CS ³ VIH(min), tcc = 10ns Input signals are changed one time during 20ns CKE ³ VIH(min), CLK £ VIL(max), tcc = ¥ input signals are stable Io = mA Page burst 4 Banks activated tCCD = 2CLK tRC ³ tRC(min) CKE £ 0.2V Version 133 100 4,280 4,370 565 185 1430 Units Note mA 1 mA 3 365 710 290 mA 3 mA 3 2,150 mA 3 1,265 mA 3 4,280 mA 1 6,980 mA mA 2 3 4,820 7,340 605 Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1 PLL & 2 Drive ICs. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 4 Sept. 2002 Rev. 0 ECO #15460 WED3DG72256V-D2 ORDERING INFORMATION Part Number WED3DG72256V10D2 WED3DG72256V7D2 WED3DG72256V75D2 SPEED 100MHz 133MHz 133MHz CAS Latency CL=2 CL=2 CL=3 PACKAGE DIMENSIONS .255 .050 ALL DIMENSIONS ARE IN INCHES Sept. 2002 Rev. 0 ECO #15460 5 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DG72256V-D2 REV. DATE REQUESTED BY DETAILS A 11-6-01 PAUL MARIEN CREATED B 1-22-02 PAUL MARIEN C 3-25-02 PAUL MARIEN 0 9-19-02 PAUL MARIEN White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 6 -CORRECT BLOCK DIAGRAM -CHANGE MODULE HEIGHT TO 1.100" -PG. 5 CORRECT SPECIFICATIONS -PG. 6 CORRECT MODULE WIDTH DEMINSION -CHANGED FROM ADVANCED TO FINAL Sept. 2002 Rev. 0 ECO #15460