74AC16374 16-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS (NON INVERTED) ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 120MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRASMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74AC16374 is an advanced high-speed CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. This 16 bit D-Type Flip-Flop is controlled by two clock inputs (CK) and two output enable inputs (OE). The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the outputs will be in a normal logic state (high or low logic level); while OE is high, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. April 2001 TSSOP ORDER CODES PACKAGE TSSOP TUBE T &R 74AC16374TTR PIN CONNECTION 1/9 74AC16374 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 1OE 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 24 1Q0 to 1Q7 2Q0 to 2Q7 2OE IEC LOGIC SYMBOLS NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 3-State Outputs 3-State Outputs 3 State Output Enable Input (Active LOW) 25 2CK Clock Input (LOW-to-HIGH Edge Trigger) 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1CK Clock Input (LOW-to-HIGH Edge Trigger) 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 V CC Positive Supply Voltage TRUTH TABLE INPUTS OE CK D H X Q X Z L X NO CHANGE L L L L H H X : Don’t Care Z : High Impedance 2/9 OUTPUTS 74AC16374 LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) ± 50 mA ± 400 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol V CC Parameter Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature dt/dv Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1) Value Unit 2 to 6 V 0 to VCC V 0 to VCC V -55 to 125 °C 8 ns/V 1) VIN from 30% to 70% of VCC 3/9 74AC16374 DC SPECIFICATIONS Test Condition Symbol VIH V IL VOH VOL II I OZ ICC IOLD IOHD Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) TA = 25 °C VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 Value VO = 0.1 V or VCC-0.1V Min. Typ. 2.1 3.15 3.85 1.5 2.25 2.75 1.5 2.25 2.75 VO = 0.1 V or VCC-0.1V Max. -55 to 125°C Min. Min. Max. 2.1 3.15 3.85 0.9 1.35 1.65 0.9 1.35 1.65 V 0.9 1.35 1.65 3.0 IO=-50 µA 2.9 2.99 2.9 2.9 IO=-50 µA 4.4 4.49 4.4 4.4 5.49 Unit Max. 2.1 3.15 3.85 4.5 V 5.5 IO=-50 µA 5.4 5.4 5.4 3.0 IO =-12 mA 2.56 2.46 2.46 4.5 IO =-24 mA 3.86 3.76 3.76 5.5 IO =-24 mA 4.86 4.76 4.76 3.0 IO=50 µA 0.002 0.1 0.1 0.1 4.5 IO=50 µA 0.001 0.1 0.1 0.1 5.5 IO=50 µA 0.001 0.1 0.1 0.1 3.0 IO =12 mA 0.36 0.44 0.44 4.5 IO =24 mA 0.36 0.44 0.44 5.5 IO =24 mA 0.36 0.44 0.44 5.5 VI = VCC or GND ± 0.1 ±1 ±1 µA 5.5 VI = VIH or VIL VO = VCC or GND ± 0.5 ±5 ±5 µA 5.5 VI = VCC or GND 8 80 80 µA VOLD = 1.65 V max 75 75 mA VOHD = 3.85 V min -75 -75 mA 5.5 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω 4/9 -40 to 85°C V V 74AC16374 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter Value TA = 25 °C VCC (V) Typ. Max. tPLH tPHL Propagation Delay Time CK to Q tPZL tPZH Output Enable Time (*) 5.9 9.8 17.0 17.0 5.0(**) 4.2 6.5 10.8 10.8 3.3 (*) 6.7 11.1 21.2 21.2 (**) 5.0 4.9 7.3 12.1 12.1 tPLZ tPHZ Output Disable Time 3.3 (*) 6.3 10.0 12.0 12.0 5.0(**) 4.9 7.6 9.1 9.1 tW ts th fMAX CLOCK Pulse Width HIGH or LOW Setup Time D to CK, HIGH or LOW Hold Time D to CK, HIGH or LOW Maximum Clock Frequency 3.3 Min. -40 to 85 °C -55 to 125°C Min. Max. Min. 3.3 (*) 2.5 2.0 5.2 5.2 (**) 5.0 2.5 2.0 4.2 4.2 3.3 (*) 1.5 1.0 2.5 2.5 (**) 5.0 2.0 1.2 2.5 2.5 3.3 (*) 1.0 -0.5 1.5 1.5 5.0(**) 1.0 -0.5 1.5 1.5 3.3 (*) 60 100 60 60 (**) 100 120 100 100 5.0 Unit Max. ns ns ns ns ns ns MHz (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) Value TA = 25 °C Min. CIN C OUT C PD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) Typ. Max. -40 to 85 °C -55 to 125°C Min. Max. Min. Unit Max. 5.0 3.5 pF 5.0 11 pF 20 pF 5.0 fIN=10MHz 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit) 5/9 74AC16374 TEST CIRCUIT Test Switch tPLH, tPHL Open tPZL, tPLZ 2VCC tPZH, tPHZ GND C L = 50pF or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/9 74AC16374 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: CLOCK PULSE WIDTHS (f=1MHz; 50% duty cycle) 7/9 74AC16374 TSSOP48 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. 1.1 MAX. 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 12.4 12.5 12.6 0.408 0.492 0.496 E 7.95 8.1 8.25 0.313 0.319 0.325 E1 6.0 6.1 6.2 0.236 0.240 0.244 e 0.5 BSC 0.0197 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e E1 PIN 1 IDENTIFICATION 1 L E c D 8/9 TYP. 74AC16374 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. 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