Revised August 2001 74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold General Description Features The VCXH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit operation. ■ 1.65V–3.6V VCC supply operation The VCXH16374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74VCXH16374 is designed for low voltage (1.65V to 3.6V) VCC applications with output compatibility up to 3.6V. The 74VCXH16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 3.6V tolerant control inputs and outputs ■ Bushold on data inputs eliminates the need for external pull-up/pull-down resistors ■ tPD 3.0 ns max for 3.0V to 3.6V VCC 3.9 ns max for 2.3V to 2.7V VCC 7.8 ns max for 1.65V to 1.95V VCC ■ Static Drive (IOH/IOL) ±24 mA @ 3.0V VCC ±18 mA @ 2.3V VCC ±6 mA @ 1.65V VCC ■ Uses patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 300 mA ■ ESD performance: Human body model > 2000V Machine model > 200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number 74VCXH16374GX (Note 1) Package Number BGA54A (Preliminary) 74VCXH16374MTD (Note 2) MTD48 Package Descriptions 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: BGA package available in Tape and Reel only. Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS500228 www.fairchildsemi.com 74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold January 2000 74VCXH16374 Connection Diagrams Pin Descriptions Pin Assignment for TSSOP Pin Names Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0–I15 Bushold Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Truth Tables Inputs CP1 Pin Assignment for FBGA Outputs OE1 I0–I7 O0–O7 L H H L L L L L X O0 X H X Z Inputs CP2 (Top Thru View) Outputs OE2 I8–I15 O8–O15 L H H L L L L L X O0 X H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, control inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP www.fairchildsemi.com 2 flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. The 74VCXH16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each Logic Diagram Byte 1 (0:7) Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74VCXH16374 Functional Description 74VCXH16374 Absolute Maximum Ratings(Note 3) Recommended Operating Conditions (Note 5) −0.5V to +4.6V Supply Voltage (VCC) DC Input Voltage (VI) Power Supply −0.5V to 4.6V OEn, CPn Operating −0.5V to VCC + 0.5V I0 – I15 1.65V to 3.6V Data Retention Only Output Voltage (VO) 1.2V to 3.6V −0.3V to VCC Input Voltage −0.5V to +4.6V Outputs 3-STATED Outputs Active (Note 4) Output Voltage (VO) −0.5V to VCC +0.5V Output in Active States DC Input Diode Current (IIK) 0V to VCC Output in “OFF” State VI < 0V −50 mA 0.0V to 3.6V Output Current in IOH/IOL VCC = 3.0V to 3.6V ±24 mA VO < 0V −50 mA VCC = 2.3V to 2.7V ±18 mA VO > VCC +50 mA VCC = 1.65V to 2.3V DC Output Diode Current (IOK) DC Output Source/Sink Current ±50 mA (IOH/IOL) −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V DC VCC or GND Current per ±100 mA Supply Pin (ICC or GND) Storage Temperature Range (TSTG) ±6 mA Free Air Operating Temperature (TA) 10 ns/V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. −65°C to +150°C Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused control inputs must be held HIGH or LOW. DC Electrical Characteristics (2.7V < VCC ≤ 3.6V) Symbol Parameter Conditions VCC (V) VIH HIGH Level Input Voltage 2.7 − 3.6 VIL LOW Level Input Voltage 2.7 − 3.6 VOH HIGH Level Output Voltage VOL II II(HOLD) II(OD) IOZ LOW Level Output Voltage Input Leakage Current Min Max Units 0.8 V 2.0 V IOH = −100 µA 2.7 − 3.6 VCC − 0.2 V IOH = −12 mA 2.7 2.2 V IOH = −18 mA 3.0 2.4 V IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.7 − 3.6 0.2 V IOL = 12 mA 2.7 0.4 V IOL = 18 mA 3.0 0.4 V IOL = 24 mA 3.0 0.55 V V Control Pins 0 ≤ VI ≤ 3.6V 2.7 − 3.6 ±5.0 µA Data Pins VI = VCC or GND 2.7 − 3.6 ±5.0 µA Bushold Input Minimum VIN = 0.8V 3.0 75 Drive Hold Current VIN = 2.0V 3.0 −75 Bushold Input Over-Drive (Note 6) 3.6 450 Current to Change State (Note 7) 3.6 −450 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V VI = VIH or VIL 2.7 − 3.6 µA µA ±10 µA IOFF Power-OFF Leakage Current 0 ≤ (VO) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current VI = VCC or GND 2.7 − 3.6 20 µA VCC ≤ (VO) ≤ 3.6V (Note 8) 2.7 − 3.6 ±20 µA VIH = VCC −0.6V 2.7 − 3.6 750 µA ∆ICC Increase in ICC per Input Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: Outputs disabled or 3-STATE only. www.fairchildsemi.com 4 Symbol Parameter V CC Conditions (V) VIH HIGH Level Input Voltage 2.3 − 2.7 VIL LOW Level Input Voltage 2.3 − 2.7 VOH HIGH Level Output Voltage VOL IOH = −100 µA LOW Level Output Voltage Min V V 2.3 − 2.7 VCC − 0.2 V 2.3 2.0 V IOH = −12 mA 2.3 1.8 V IOH = −18 mA 2.3 1.7 IOL = 100 µA 2.3 − 2.7 0.2 V IOL = 12 mA 2.3 0.4 V IOL = 18 mA 2.3 0.6 V 0 ≤ VI ≤ 3.6V 2.3 − 2.7 ±5.0 µA VI = V CC or GND 2.3 − 2.7 ±5.0 µA II(HOLD) Bushold Input Minimum VIN = 0.7V 2.3 45 Drive Hold Current VIN = 1.6V 2.3 -45 Bushold Input Over-Drive (Note 9) 2.7 300 2.7 −300 II(OD) 0.7 IOH = −6 mA Input Leakage Current Data Pins Units 1.6 II Control Pins Max Current to Change State (Note 10) IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V IOFF Power-OFF Leakage Current 0 ≤ (VO) ≤ 3.6V ICC Quiescent Supply Current V µA µA 2.3 − 2.7 ±10 µA 0 10 µA VI = V CC or GND 2.3 − 2.7 20 µA VCC ≤ (VO) ≤ 3.6V (Note 11) 2.3 − 2.7 ±20 µA Max Units VI = V IH or VIL Note 9: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 10: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 11: Outputs disabled or 3-STATE only. DC Electrical Characteristics (1.65V ≤ VCC < 2.3V) Symbol Parameter Conditions VCC Min (V) VIH HIGH Level Input Voltage 1.65 - 2.3 VIL LOW Level Input Voltage 1.65 - 2.3 VOH HIGH Level Output Voltage IOH = −100 µA 0.65 × VCC 1.65 - 2.3 VCC − 0.2 IOH = −6 mA 1.65 1.25 IOL = 100 µA 1.65 - 2.3 VOL LOW Level Output Voltage II Input Leakage Current II(HOLD) Bushold Input Minimum VIN = 0.57V 1.65 25 Drive Hold Current VIN = 1.07V 1.65 -25 IOL = 6 mA Control Pins Data Pins II(OD) IOZ V 0.35 × V CC V V V 0.2 V 1.65 0.3 V 0 ≤ VI ≤ 3.6V 1.65 - 2.3 ±5.0 µA VI = V CC or GND 1.65 - 2.3 ±5.0 µA Bushold Input Over-Drive (Note 12) 1.95 200 Current to Change State (Note 13) 1.95 −200 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V VI = V IH or VIL 1.65 - 2.3 µA µA ±10 µA IOFF Power-OFF Leakage Current 0 ≤ (VO) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current VI = V CC or GND 1.65 - 2.3 20 µA VCC ≤ (VO) ≤ 3.6V (Note 14) 1.65 - 2.3 ±20 µA Note 12: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 13: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 14: Outputs disabled or 3-STATE only. 5 www.fairchildsemi.com 74VCXH16374 DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V) 74VCXH16374 AC Electrical Characteristics (Note 15) TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V Min VCC = 2.5V ± 0.2V Max Min Max 200 VCC = 1.8V ± 0.15V Min Units Max fMAX Maximum Clock Frequency 250 tPHL, tPLH Propagation Delay CP to On 0.8 3.0 1.0 3.9 1.5 7.8 ns tPZL, tPZH Output Enable Time 0.8 3.5 1.0 4.6 1.5 9.2 ns tPLZ, tPHZ Output Disable Time 0.8 3.5 1.0 3.8 1.5 6.8 ns tS Setup Time 1.5 1.5 2.5 ns tH Hold Time 1.0 1.0 1.0 ns tW Pulse Width 1.5 1.5 4.0 ns tOSHL Output to Output Skew tOSLH (Note 16) 0.5 100 0.5 MHz 0.75 ns Note 15: For CL = 50PF, add approximately 300 ps to the AC maximum specification. Note 16: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP VOLV VOHV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Quiet Output Dynamic Valley VOH Conditions CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V V CC TA = +25°C (V) Typical 1.8 0.25 2.5 0.6 3.3 0.8 1.8 −0.25 2.5 −0.6 3.3 −0.8 1.8 1.5 2.5 1.9 3.3 2.2 Units V V V Capacitance Symbol Parameter Conditions TA = +25°C Typical Units CIN Input Capacitance VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC 6 pF COUT Output Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 7 pF CPD Power Dissipation Capacitance 20 pF VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V www.fairchildsemi.com 6 74VCXH16374 AC Loading and Waveforms TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V; VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V tPZH, tPHZ GND FIGURE 1. AC Test Circuit FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and tREC Waveforms Symbol FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic VCC 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VX VOL +0.3V VOL +0.15V VOL +0.15V VY VOH −0.3V VOH −0.15V VOH −0.15V 7 www.fairchildsemi.com 74VCXH16374 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary) www.fairchildsemi.com 8 74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com