Features • EE Programmable 524,288 x 1- and 1,048,576 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) • In-System Programmable via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX®, APEX™ • • • • • • • • Devices, Lucent ORCA® FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®, Virtex™ FPGAs Cascadable Read Back to Support Additional Configurations or Higher-density Arrays Low-power CMOS EEPROM Process Programmable Reset Polarity Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Packages), 8-lead PDIP and 20-lead PLCC Packages (Pin Compatible Across Product Family) Emulation of Atmel’s AT24CXXX Serial EEPROMs Available in 3.3V ± 10% LV and 5V ± 5% C Versions System-friendly READY Pin Low-power Standby Mode Description The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for programming Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-lead LAP, 8-lead PDIP and the popular 20-lead PLCC. The AT17 Series uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These devices support a write protection mode and a system-friendly READY pin, which signifies a “good” power level to the FPGA and can be used to ensure reliable system power-up. The AT17 Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. FPGA Configuration EEPROM Memory 512-kilobit and 1-megabit AT17C512 AT17LV512 AT17C010 AT17LV010 Rev. 0944E–12/01 1 Pin Configurations 8-lead LAP DATA CLK RESET/OE CE 1 2 3 4 VCC SER_EN CEO (A2) GND 8 7 6 5 8-lead PDIP DATA CLK RESET/OE CE 1 2 3 4 8 7 6 5 VCC SER_EN CEO (A2) GND 18 17 16 15 14 9 10 11 12 13 4 5 6 7 8 NC SER_EN NC READY CEO (A2) NC GND NC NC NC CLK WP1 RESET/OE WP2 CE 3 2 1 20 19 NC DATA NC VCC NC 20-lead PLCC 2 AT17C512/010/LV512/010 0944E–12/01 AT17C512/010/LV512/010 Block Diagram SER_EN WP1 WP2 PROGRAMMING DATA SHIFT REGISTER PROGRAMMING MODE LOGIC OSC CONTROL ROW ADDRESS COUNTER ROW DECODER OSC BIT COUNTER POWER ON RESET EEPROM CELL MATRIX COLUMN DECODER TC CLK READY Device Description RESET/OE CE CEO(A2) DATA The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17 Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE. 3 0944E–12/01 Pin Description 8 PDIP/ LAP Pin 20 PLCC Pin Name I/O Description 1 2 DATA I/O Three-state DATA output for configuration. Open-collector bi-directional pin for programming. 2 4 CLK I Clock input. Used to increment the internal address and bit counter for reading and programming. 5 WP1(1) I WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. 6 RESET/OE I Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. For most applications, RESET should be programmed active Low. This document describes the pin as RESET/OE. 7 WP2(1) I WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. 4 8 CE I Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a lowpower standby mode. Note that this pin will not enable/disable the device in the 2wire Serial Programming mode ( SER_EN Low). 5 10 GND 3 CEO O Chip Enable Output (active Low). This output goes Low when the address counter has reached its maximum value. In a daisy chain of AT17 Series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again. A2 I Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pulldown resistor. 15 READY(1) O Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated) when power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if used). 7 17 SER_EN I Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. 8 20 VCC 6 Note: 4 Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. 14 +3.3V/+5V power supply pin. 1. This pin is not available on the 8-lead packages. AT17C512/010/LV512/010 0944E–12/01 AT17C512/010/LV512/010 FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The AT17 Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode. This document discusses the AT40K, AT40KAL and AT94KAL applications, as well as Xilinx applications. Control of Configuration Cascading Serial Configuration EEPROMs Most connections between the FPGA device and the AT17 Serial EEPROM are simple and self-explanatory: • The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices. • The master FPGA CCLK output drives the CLK input of the AT17 Series Configurator. • The CEO output of any AT17 Series Configurator drives the CE input of the next Configurator in a cascade chain of EEPROMs. • SER_EN must be connected to VCC (except during ISP). • The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded Configurators provide additional memory. As the last bit from the first Configurator is read, the clock signal to the Configurator asserts its CEO output Low and disables its DATA line driver. The second Configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded Configurators are reset if the RESET/OE on each Configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level. AT17 Series Reset Polarity The AT17 Series Configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17C parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.3V nominal. Standby Mode The AT17C/LV512/010 Series Configurator enters a low-power standby mode whenever CE is asserted High. In this mode, the Configurator consumes less than 0.5 mA of current at 5V. The output remains in a high-impedance state regardless of the state of the OE input. 5 0944E–12/01 Example Circuits Figure 1. AT17 Series Device for Programming PSLI Devices AT17 Series Device AT40K/AT40KAL/AT94K RESET RESET M2 M1 M0 VCC SER_EN DATA CLK CE (2) RESET/OE(1) READY DATA0 CCLK CON INIT GND Notes: 1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices. The FPGA CON/DONE output drives the CE input of the AT17 Series Configurator, while the RESET/OE input is driven by the FPGA INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration before CON/DONE has gone High. A Low level on the RESET/OE input, during FPGA reset, clears the configurator’s internal address pointer so that the reconfiguration starts at the beginning. Figure 2. Drop-In Replacement of XC17/ATT17 PROMs for Xilinx/Lucent FPGA Applications VCC 4.7 kW XILINX FPGA PROGRAM PROGRAM M2 M1 M0 DIN CCLK DONE(3) INIT AT17 Series Device VCC SER_EN DATA CLK CE (2) RESET/OE(1) READY GND Notes: 6 1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices. 3. An internal pull-up resistor is enabled here for DONE. AT17C512/010/LV512/010 0944E–12/01 AT17C512/010/LV512/010 For details of ISP, please refer to the “Programming Specification for Atmel's AT17 and AT17A Series FPGA Configuration EEPROMs”, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0437.pdf. Figure 3. In-System Programming of AT17 Series for PSLI Applications VCC VCC 4.7 kW 4.7 kW DATA 1 SCLK 3 2 5 6 7 8 9 10 4 VCC GND AT17 Series Device AT40K/AT40KAL/AT94K RESET RESET M2 M1 M0 DATA0 CCLK CON INIT SER_EN SER_EN DATA CLK CE (2) RESET/OE(1) READY GND Notes: 1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices. Figure 4. In-System Programming of AT17 Series for Xilinx/Lucent FPGA Applications VCC VCC 4.7 kW DATA 1 SCLK 3 2 5 6 7 8 9 10 VCC VCC 4.7 kW 4 VCC 4.7 kW XILINX FPGA PROGRAM PROGRAM 4.7 kW M2 M1 M0 DIN CCLK DONE(3) INIT AT17 Series Device GND SER_EN SER_EN DATA CLK CE (1) READY(2) RESET/OE GND Notes: 1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices. 3. An internal pull-up resistor is enabled here for DONE. 7 0944E–12/01 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V Operating Conditions AT17CXXX Symbol VCC 8 Description AT17LVXXX Min Max Min Max Units Commercial Supply voltage relative to GND -0°C to +70°C 4.75 5.25 3.0 3.6 V Industrial Supply voltage relative to GND -40°C to +85°C 4.5 5.5 3.0 3.6 V Military Supply voltage relative to GND -55°C to +125°C 4.5 5.5 3.0 3.6 V AT17C512/010/LV512/010 0944E–12/01 AT17C512/010/LV512/010 DC Characteristics VCC = 5V ± 5% Commercial/5V ± 10% Industrial/Military Symbol Description Min Max Units VIH High-level Input Voltage 2.0 VCC V VIL Low-level Input Voltage 0.0 0.8 V VOH High-level Output Voltage (IOH = -4 mA) VOL Low-level Output Voltage (IOL = +4 mA) VOH High-level Output Voltage (IOH = -4 mA) VOL Low-level Output Voltage (IOL = +4 mA) VOH High-level Output Voltage (IOH = -4 mA) VOL Low-level Output Voltage (IOL = +4 mA) 0.4 V ICCA Supply Current, Active Mode 10 mA IL Input or Output Leakage Current (VIN = VCC or GND) 10 µA Commercial 0.5 mA ICCS Supply Current, Standby Mode Industrial/Military 0.5 mA 3.86 V Commercial 0.32 3.76 V V Industrial 0.37 3.7 V V Military -10 DC Characteristics VCC = 3.3V ± 10% Symbol Description Min Max Units VIH High-level Input Voltage 2.0 VCC V VIL Low-level Input Voltage 0.0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +2.5 mA) ICCA Supply Current, Active Mode IL Input or Output Leakage Current (VIN = VCC or GND) ICCS Supply Current, Standby Mode 2.4 V Commercial 0.4 2.4 V V Industrial 0.4 2.4 V V Military 0.4 V 5 mA 10 µA Commercial 100 µA Industrial/Military 100 µA -10 9 0944E–12/01 AC Characteristics CE TSCE TSCE THCE RESET/OE THOE THC TLC CLK TOE TCAC TOH TDF TCE DATA TOH AC Characteristics when Cascading RESET/OE CE CLK TCDF DATA LAST BIT TOCK FIRST BIT TOOE TOCE CEO TOCE 10 AT17C512/010/LV512/010 0944E–12/01 AT17C512/010/LV512/010 . AC Characteristics for AT17C512/010 VCC = 5V ± 5% Commercial/VCC = 5V ± 10% Industrial/Military Commercial Symbol Description TOE(2) OE to Data Delay (2) TCE TCAC (2) Min Max Industrial/Military(1) Max Units 30 35 ns CE to Data Delay 45 45 ns CLK to Data Delay 50 50 ns TOH Data Hold From CE, OE, or CLK TDF(3) CE or OE to Data Float Delay TLC CLK Low Time 20 20 ns THC CLK High Time 20 20 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 20 25 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter Is reset) 20 20 ns FMAX MAX Input Clock Frequency 15 15 MHz Notes: 0 Min 0 50 ns 50 ns 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. AC Characteristics for AT17C512/010 when Cascading VCC = 5V± 5% Commercial/VCC = 5V ± 10% Industrial/Military Commercial Symbol Description TCDF (3) CLK to Data Float Delay TOCK(2) TOCE(2) TOOE(2) FMAX MAX Input Clock Frequency Notes: Min Max Units 50 50 ns CLK to CEO Delay 35 40 ns CE to CEO Delay 35 35 ns RESET/OE to CEO Delay 30 30 ns 12.5 Max Industrial/Military(1) Min 12.5 MHz 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. 11 0944E–12/01 AC Characteristics for AT17LV512/010 VCC = 3.3V ± 10% Commercial Symbol Description TOE(2) OE to Data Delay (2) TCE TCAC (2) Min Max Industrial/Military(1) Max Units 50 55 ns CE to Data Delay 55 60 ns CLK to Data Delay 55 60 ns TOH Data Hold From CE, OE, or CLK TDF(3) CE or OE to Data Float Delay TLC CLK Low Time 25 25 ns THC CLK High Time 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 30 35 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 ns FMAX MAX Input Clock Frequency 15 10 MHz Notes: 0 Min 0 50 ns 50 ns 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. AC Characteristics for AT17LV512/010 when Cascading VCC = 3.3V ± 10% Commercial Symbol Description TCDF(3) CLK to Data Float Delay TOCK(2) TOCE(2) TOOE(2) FMAX MAX Input Clock Frequency Notes: 12 Min Max Units 50 50 ns CLK to CEO Delay 50 55 ns CE to CEO Delay 35 40 ns RESET/OE to CEO Delay 35 35 ns 12.5 Max Industrial/Military(1) Min 10 MHz 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. AT17C512/010/LV512/010 0944E–12/01 AT17C512/010/LV512/010 Thermal Resistance Coefficients(1) θJC [°C/W] θJA [°C/W] Airflow = 0 ft/min 8CN4 45 135.71 Plastic Dual Inline Package (PDIP) 8P3 37 107 Plastic Leaded Chip Carrier (PLCC) 20J 35 90 Package Type Leadless Array Package (LAP) Note: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0636.pdf. 13 0944E–12/01 Ordering Information – 5V Devices Memory Size Ordering Code Package Operation Range 512-Kbit AT17C512-10CC AT17C512-10PC AT17C512-10JC 8CN4 8P3 20J Commercial (0°C to 70°C) AT17C512-10CI AT17C512-10PI AT17C512-10JI 8CN4 8P3 20J Industrial (-40°C to 85°C) AT17C010-10CC AT17C010-10PC AT17C010-10JC 8CN4 8P3 20J Commercial (0°C to 70°C) AT17C010-10CI AT17C010-10PI AT17C010-10JI 8CN4 8P3 20J Industrial (-40°C to 85°C) 1-Mbit Ordering Information – 3.3V Devices Memory Size Ordering Code Package Operation Range 512-Kbit AT17LV512-10CC AT17LV512-10PC AT17LV512-10JC 8CN4 8P3 20J Commercial (0°C to 70°C) AT17LV512-10CI AT17LV512-10PI AT17LV512-10JI 8CN4 8P3 20J Industrial (-40°C to 85°C) AT17LV010-10CC AT17LV010-10PC AT17LV010-10JC 8CN4 8P3 20J Commercial (0°C to 70°C) AT17LV010-10CI AT17LV010-10PI AT17LV010-10JI 8CN4 8P3 20J Industrial (-40°C to 85°C) 1-Mbit Package Type 8CN4 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 14 AT17C512/010/LV512/010 0944E–12/01 AT17C512/010/LV512/010 Packaging Information 8CN4 – LAP Marked Pin1 Indentifier E A A1 D Top View Side View Pin1 Corner L1 0.10 mm TYP 8 1 e COMMON DIMENSIONS (Unit of Measure = mm) 2 7 3 6 b 5 4 e1 L Bottom View SYMBOL MIN NOM MAX A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b 0.45 0.50 0.55 D 5.89 5.99 6.09 E 4.89 5.99 6.09 e 1.27 BSC e1 1.10 REF NOTE 1 L 0.95 1.00 1.05 1 L1 1.25 1.30 1.35 1 Note: 1. Metal Pad Dimensions. 11/14/01 R 1150 E.Cheyenne Mtn Blvd. Colorado Springs, CO 80906 TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) DRAWING NO. 8CN4 REV. A 15 0944E–12/01 8P3 – PDIP D PIN 1 E1 A B1 SEATING PLANE A1 L B B2 e (4 PLACES) E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001 BA. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). NOM MAX – – 4.318 A1 0.381 – – D 9.144 – 9.652 E 7.620 – 8.255 E1 6.096 – 6.604 B 0.406 – 0.508 B1 1.397 – 1.651 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e R 16 TITLE 2325 Orchard Parkway 8P3, 8-lead (0.300"/7.62 mm Wide) Plastic Dual San Jose, CA 95131 Inline Package (PDIP) MIN A SYMBOL NOTE Note 2 Note 2 2.540 TYP 09/28/01 DRAWING NO. REV. 8P3 B AT17C512/010/LV512/010 0944E–12/01 AT17C512/010/LV512/010 20J – PLCC PIN NO. 1 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER e E1 E D2/E2 B1 B A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 9.779 – 10.033 D1 8.890 – 9.042 E 9.779 – 10.033 E1 8.890 – 9.042 D2/E2 7.366 – 8.382 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel ® is the registered trademark of Atmel. FLEX ™ is the trademark of Altera Corporation; ORCA™ is the trademark of Lucent Technologies, Inc.; SPARTAN ™ and Virtex™ are the trademarks of Xilinx, Inc.; APEX ™ is the trademark of MIPS Technologies; Other terms and product names may be the trademarks of others. Printed on recycled paper. 0944E–12/01//xM