CY26049-36
FailSafe™ PacketClock
Global Communications Clock Generator
FailSafe™ PacketClock Global Communications Clock Generator
Features
Functional Description
■
Fully Integrated Phase-Locked Loop (PLL)
■
FailSafe Output
■
8 kHz Reference Clock
■
PLL Driven by a Crystal Oscillator that is Phase Aligned with
External Reference
■
Selectable Standard Communication Output Frequencies
■
Low Jitter, High Accuracy Outputs
■
3.3 V Operation
■
16-pin TSSOP Package
■
Commercial and Industrial Temperature Ranges
CY26049 is a FailSafe frequency synthesizer with a reference
clock input and three clock outputs. The device provides an
optimum solution for applications which require continuous
operation in case of primary clock failure. The continuous,
glitch-free operation is achieved by using a DCXO which serves
as a primary clock source. The FailSafe control circuit
synchronizes the DCXO with the reference as long as the
reference is within the pull range of the crystal.
In the event of a reference clock failure the DCXO maintains the
last frequency and phase information of the reference clock. The
unique feature of the CY26049-36 is that the DCXO is, in fact,
the primary clocking source. When the reference clock is
restored, the DCXO automatically resynchronizes to the
reference. The status of the reference clock input, as detected
by the CY26049-36, is reported by the SAFE pin.
In the buffer mode (FS3:FS0 = 1110 or 1111), the CY26049-36
can be used as a jitter attenuator. In this mode, extensive jitter
on the input clock is ‘filtered’, resulting in a low jitter output clock.
For a complete list of related documentation, click here.
Logic Block Diagram
external pullable crystal
(18.432 MHz)
XIN
XOUT
Input reference
(typical 8 kHz)
ICLK
FAILSAFETM
CONTROL
PHASE
LOCKED
LOOP
DIGITAL
CONTROLLED
CRYSTAL
OSCILLATOR
FS[3:0]
frequency select
CLK
OUTPUT
DIVIDERS
CLK/2
8K
SAFE
High=ICLK detected
Cypress Semiconductor Corporation
Document Number: 38-07415 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 23, 2016
CY26049-36
Contents
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Frequency Select Tables ................................................. 4
Absolute Maximum Conditions ....................................... 5
Recommended Pullable Crystal Specifications ............ 5
Recommended Operating Conditions ............................ 5
DC Electrical Specifications ............................................ 6
DC Electrical Specifications ............................................ 6
Thermal Resistance .......................................................... 6
AC Electrical Specifications ............................................ 7
Voltage and Timing Definitions ....................................... 7
Test Circuit ........................................................................ 8
Ordering Information ........................................................ 8
Ordering Code Definitions ........................................... 8
Document Number: 38-07415 Rev. *I
Package Diagram .............................................................. 9
Acronyms ........................................................................ 10
Document Conventions ................................................. 10
Units of Measure ....................................................... 10
Document History Page ................................................. 11
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support ....................... 12
Products .................................................................... 12
PSoC®Solutions ....................................................... 12
Cypress Developer Community ................................. 12
Technical Support ..................................................... 12
Page 2 of 12
CY26049-36
Pin Configuration
Figure 1. 16-pin TSSOP pinout (Top View)
CY26049-36
ICLK 1
16 NC
8K 2
15 CLK
FS1 3
14 FS0
FS2 4
13 FS3
VDD 5
12 VDD
VSS 6
11 VSS
CLK/2 7
10 SAFE
XIN 8
9 XOUT
Pin Definitions
Pin Name
Pin Number
Pin Description
ICLK
1
Reference Input Clock; 8 kHz or 10 to 60 MHz.
8K
2
Clock Output; 8 kHz or high impedance in buffer mode.
FS1
3
Frequency Select 1; Determines CLK outputs according to Table 1 on page 4.
FS2
4
Frequency Select 2; Determines CLK outputs according to Table 1 on page 4.
VDD
5
Voltage Supply; 3.3 V.
VSS
6
Ground
CLK/2
7
Clock Output; Frequency according to Table 1 on page 4.
XIN
8
Pullable Crystal Input; 18.432 MHz.
XOUT
9
Pullable Crystal Output; 18.432 MHz.
SAFE
10
High = reference ICLK within range, Low = reference ICLK out of range.
VSS
11
Ground
VDD
12
Voltage Supply; 3.3 V.
FS3
13
Frequency Select 3; Determines CLK outputs according to Table 1 on page 4.
FS0
14
Frequency Select 0; Determines CLK outputs according to Table 1 on page 4.
CLK
15
Clock Output; Frequency according to Table 1 on page 4.
NC
16
No Connect
Document Number: 38-07415 Rev. *I
Page 3 of 12
CY26049-36
Frequency Select Tables
Table 1. CY26049-36 Frequency Select–Output Decoding Table–External Mode (MHz except as noted)
ICLK
FS3
FS2
FS1
FS0
CLK/2
CLK
8K
Crystal
8 kHz
0
0
0
0
1.544
3.088
8 kHz
18.432
8 kHz
0
0
0
1
2.048
4.096
8 kHz
18.432
8 kHz
0
0
1
0
22.368
44.736
8 kHz
18.432
8 kHz
0
0
1
1
17.184
34.368
8 kHz
18.432
8 kHz
0
1
0
0
77.76
155.52
8 kHz
18.432
8 kHz
0
1
0
1
16.384
32.768
8 kHz
18.432
8 kHz
0
1
1
0
14.352
28.704
8 kHz
18.432
8 kHz
0
1
1
1
High Z [1]
High Z [1]
High Z [1]
18.432
8 kHz
1
0
0
0
18.528
37.056
8 kHz
18.432
8 kHz
1
0
0
1
12.352
24.704
8 kHz
18.432
8 kHz
1
0
1
0
7.68
15.36
8 kHz
18.432
8 kHz
1
0
1
1
High Z [1]
High Z [1]
High Z [1]
18.432
8 kHz
1
1
0
0
12.288
24.576
8 kHz
18.432
8 kHz
1
1
0
1
16.384
32.768
8 kHz
18.432
Crystal
Table 2. CY26049-36 Frequency Select–Output Decoding Table–Buffer Mode
ICLK
FS3
FS2
FS1
FS0
CLK/2
CLK
8K
20 to 60 MHz
1
1
1
0
ICLK/2
ICLK
High Z [1]
10 to 30 MHz
1
1
1
1
2 × ICLK
4 × ICLK
High Z
[1]
ICLK/2
ICLK
Note
1. High Z = high impedance.
Document Number: 38-07415 Rev. *I
Page 4 of 12
CY26049-36
Absolute Maximum Conditions
Storage Temperature
(Non-Condensing) ................................... –55 C to +125 C
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Junction Temperature ............................. –40 C to +125 C
Supply Voltage (VDD) ...................................... –0.5 to +7.0 V
Data Retention at TJ = 125 C ..............................> 10 years
Package Power Dissipation ..................................... 350 mW
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
ESD (Human Body Model) MIL-STD-883 .................. 2000 V
Recommended Pullable Crystal Specifications
Parameter [2]
Description
Comments
Min
Typ
Max
Units
Parallel resonance, fundamental
mode, AT cut
–
18.432
–
MHz
Nominal load capacitance
–
14
–
pF
R1
Equivalent
(ESR)
–
–
25
R3/R1
Ratio of third overtone mode ESR Ratio used because typical R1
values are much less than the
to fundamental mode ESR
maximum spec
3
–
–
DL
Crystal drive level
–
0.5
2
mW
F3SEPHI
Third overtone separation from High side
3 × FNOM
400
–
–
ppm
F3SEPLO
Third overtone separation from Low side
3 × FNOM
–
–
–200
ppm
pF
FNOM
Nominal crystal frequency
CLNOM
series
resistance Fundamental mode
No external series resistor assumed
C0
Crystal shunt capacitance
C0/C1
Ratio of shunt
capacitance
C1
Crystal motional capacitance
to
motional
–
–
7
180
–
250
14.4
18
21.6
fF
Recommended Operating Conditions
Parameter
Description
Min
Typ
Max
Unit
3.15
3.3
3.45
V
0
–
70
°C
–40
–
85
°C
VDD
Operating Voltage
TAC
Ambient Temperature (Commercial Temperature)
TAI
Ambient Temperature (Industrial Temperature)
CLOAD
Max Output Load Capacitance
–
–
15
pF
tPU
Power up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
500
ms
tER(I)
8 kHz Input Edge Rate, 20% to 80% of VDD = 3.3 V
0.07
–
–
V/ns
Note
2. Ecliptek crystals ECX-5761-18.432 M and ECX-5762-18.432 M meet these specifications.
Document Number: 38-07415 Rev. *I
Page 5 of 12
CY26049-36
DC Electrical Specifications
Commercial Temperature: 0 C to 70 C
Parameter
Description
Test Conditions
IOH
Output High Current
VOH = VDD – 0.5 V,
VDD = 3.3 V (source)
Min
Typ
Max
Unit
12
24
–
mA
IOL
Output Low Current
VOL = 0.5 V, VDD = 3.3 V (sink)
12
24
–
mA
VIH
Input High Voltage
CMOS Levels
0.7
–
–
VDD
VIL
Input High Voltage
CMOS Levels
–
–
0.3
VDD
IIH
Input High Current
VIH = VDD
–
5
10
A
IIL
Input Low Current
VIL = 0 V
CIN
Input Capacitance
[3] output
–
5
10
A
–
–
7
pF
IOZ
Output Leakage Current
High Z
–
±5
–
A
IDD
Supply Current
CLOAD = 15 pF, VDD = 3.45 V,
FS [3:0] = 0100
–
–
45
mA
CLOAD = 15 pF, VDD = 3.45 V,
FS [3:0] = 1101
–
–
30
mA
DC Electrical Specifications
Industrial Temperature: –40 C to 85 C
Min
Typ
Max
Unit
IOH
Parameter
Output High Current
Description
VOH = VDD – 0.5 V,
VDD = 3.3 V (source)
Test Conditions
10
20
–
mA
IOL
Output Low Current
VOL = 0.5 V, VDD = 3.3 V (sink)
10
20
–
mA
VIH
Input High Voltage
CMOS Levels
0.7
–
–
VDD
VIL
Input High Voltage
CMOS Levels
–
–
0.3
VDD
IIH
Input High Current
VIH = VDD
–
5
10
A
IIL
Input Low Current
VIL = 0 V
–
5
10
A
CIN
Input Capacitance
–
–
7
pF
IOZ
Output Leakage Current
High Z [3] output
–
±5
–
A
IDD
Supply Current
CLOAD = 15 pF, VDD = 3.45 V,
FS [3:0] = 0100
–
–
50
mA
CLOAD = 15 pF, VDD = 3.45 V,
FS [3:0] = 1101
–
–
35
mA
Thermal Resistance
Parameter [4]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
16-pin TSSOP Unit
89
°C/W
12
°C/W
Notes
3. High Z = high impedance.
4. These parameters are guaranteed by design and are not tested.
Document Number: 38-07415 Rev. *I
Page 6 of 12
CY26049-36
AC Electrical Specifications
Commercial Temperature: 0 C to 70 C and Industrial Temperature: –40 C to 85 C
Min
Typ
Max
Unit
fICLK-E
Parameter
Frequency, Input Clock
Description
Input Clock Frequency,
External Mode
Test Conditions
–
8.00
–
kHz
fICLK-B
Frequency, Input Clock
Input Clock Frequency, Buffer Mode
10
–
60
MHz
–250
–
+250
ppm
[5]
LR
FailSafe Lock Range
Range of reference
Safe = High
tDC = t2/t1
Output Duty Cycle
Duty Cycle defined in Figure 2,
measured at 50% of VDD
45
50
55
%
tPJIT1
Clock Jitter; output > 5 MHz
Period Jitter, Peak to Peak,
10,000 periods
–
–
250
ps
RMS Period Jitter, RMS
–
–
50
ps
tPJIT2
Clock Jitter; output < 5 MHz
Period Jitter, Peak to Peak,
10,000 periods
–
–
500
ps
RMS Period Jitter, RMS
–
–
100
ps
Time for PLL to lock within
±150 ppm of target frequency
–
–
3
ms
[6]
ICLK
for
tP_LOCK
PLL Lock Time
tFS_LOCK
Failsafe Lock Time [6]
Time for PLL to lock to ICKL
(outputs phase aligned with ICKL
and Safe = High)
–
–
7
s
fERROR
Frequency Synthesis Error
Actual mean frequency error versus
target
–
0
–
ppm
ER
Rising Edge Rate
Output Clock Edge Rate, Measured
from 20% to 80% of VDD,
CLOAD = 15 pF. See Figure 3.
0.8
1.4
2
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured
from 20% to 80% of VDD,
CLOAD = 15 pF. See Figure 3.
0.8
1.4
2
V/ns
Voltage and Timing Definitions
Figure 2. Duty Cycle Definition; DC = t2/t1
t1
t2
CLK
50%
50%
Figure 3. Rise and Fall Time Definitions: ER = 0.6 × VDD / t3, EF = 0.6 × VDD / t4
t4
t3
80%
CLK
20%
Notes
5. Dependent on crystals chosen and crystal specs.
6. Lock times are measured beginning when VDD has reached its minimum specified value and ICLK is stable.
Document Number: 38-07415 Rev. *I
Page 7 of 12
CY26049-36
Test Circuit
Figure 4. Test Circuit
ICLK
8K
1
16
2
15
CLK
CLOAD
CLOAD
VDD
3
14
4
13
5
12
VDD
0.1uF
0.1uF
CLK/2
6
11
7
10
8
9
CLOAD
18.432 MHz
Ordering Information
Ordering Code
Package Type
Operating Temperature Range
Pb-free
CY26049ZXC-36
16-pin TSSOP
Commercial, 0 °C to 70 °C
CY26049ZXC-36T
16-pin TSSOP–Tape and Reel
Commercial, 0 °C to 70 °C
CY26049ZXI-36
16-pin TSSOP
Industrial, –40 °C to 85 °C
CY26049ZXI-36T
16-pin TSSOP–Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 26049 Z
X
X
-36
T
T = Tape and Reel; blank = Tube
Fixed
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free package
Package Type:
Z = 16-pin TSSOP
Part Identifier
Company ID: CY = Cypress
Document Number: 38-07415 Rev. *I
Page 8 of 12
CY26049-36
Package Diagram
Figure 5. 16-pin TSSOP 4.40 mm Body Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Document Number: 38-07415 Rev. *I
Page 9 of 12
CY26049-36
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
DCXO
Digital Controlled Crystal Oscillator
°C
degree Celsius
ESD
Electrostatic Discharge
fF
femtofarad
ESR
Equivalent Series Resistance
kHz
kilohertz
JEDEC
Joint Electron Devices Engineering Council
MHz
megahertz
PLL
Phase Locked Loop
µA
microampere
TSSOP
Thin Shrunk Small Outline Package
mA
milliampere
mm
millimeter
ms
millisecond
mW
milliwatt
ns
nanosecond
Document Number: 38-07415 Rev. *I
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
V
volt
Page 10 of 12
CY26049-36
Document History Page
Document Title: CY26049-36, FailSafe™ PacketClock Global Communications Clock Generator
Document Number: 38-07415
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
114749
08/08/02
CKN
New data sheet
*A
120067
01/06/03
CKN
Changed “FailSafe is a trademark of Silicon Graphics, Inc.” to read “FailSafe
is a trademark of Cypress Semiconductor”
*B
128000
07/15/03
IJA
Changed Benefits to read “When reference is in range, SAFE pin is driven high”
Changed first sentence to “CY26049 is a FailSafe frequency synthesizer with
a reference clock input and three clock outputs”
Changed title from “Failsafe PacketClock Global Communications Clocks”
to “FailSafe PacketClock Global Communications Clock Generator”
Changed definitions in Pin Description Table
Replaced format for Absolute Maximum Conditions
Replaced Recommended Pullable Crystal Specifications table
Added tpu to Recommended Operating Conditions
Added IIH and IIL to DC Electrical Specifications
Replaced AC Electrical Specifications from Cy26049-16 data sheet
Changed Voltage and Timing Definitions to match CY2410 data sheet
Moved Package Diagram to end of data sheet
*C
244412
See ECN
RGL
*D
2865396
01/25/2010
*E
2925613
04/30/10
KVM
*F
3377436
09/20/2011
PURU
Added Ordering Code Definitions.
Updated Package Diagram.
Added Acronyms and Units of Measure.
Updated to new template.
*G
4545891
10/20/2014
TAVA
Updated Package Diagram:
spec 51-85091 – Changed revision from *C to *E.
Updated to new template.
Completing Sunset Review.
*H
4587350
12/05/2014
TAVA
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*I
5281528
05/23/2016
PSR
Added Thermal Resistance.
Updated to new template.
Document Number: 38-07415 Rev. *I
Description of Change
Spec. (tER(I)) Input Edge Rate in the Recommended Operating Conditions
Table
Added Lead Free Devices
TSAI / KVM Added 8 kHz ref clock to p. 1 Features
Moved Functional Description to p. 1, replacing Benefits section
Removed Selector Guide table
Added units (MHz) to ICLK column of Table 2
Standardized parameter name capitalization in AC Electrical table
Changed timing parameter name t6 to tP_LOCK
Added footnote for tP_LOCK and tFS_LOCK
Remove part numbers CY26049ZC-36, CY26049ZC-36T, CY26049ZI-36 and
CY26049ZI-36T
Updated to new template.
Post to external web.
Posting to external web.
Page 11 of 12
CY26049-36
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/arm
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cypress.com/memory
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cypress.com/support
cypress.com/psoc
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cypress.com/wireless
© Cypress Semiconductor Corporation, 2002-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-07415 Rev. *I
FailSafe™ is a trademark of Cypress Semiconductor Corporation.
Revised May 23, 2016
Page 12 of 12