ComLink™ Series CY2LL842 Two-channel LVDS Repeater/Mux Features • • • • • • • • • • Description ANSI TIA/EIA-644-1995-compliant Does not exceed Belcore 802.3 standards Operation at => 350 MHz–700 Mbps Single 2 × 2 Low-voltage differential signaling (LVDS) with output voltages of ± 350 mV into 100-ohm load version (Std) Single 3.3V supply Accepts ± 350 mV differential inputs Output drivers are high-impedance when disabled or when VDD ≤ 1.5V 16-pin SOIC/TSSOP packages Industrial version available The CYPRESS CY2LL842 are differential line drivers and receivers that utilize LVDS to achieve signaling rates of 650 Mbs. The receiver outputs can be switched to either or both drivers thru the multiplexer control signals S0/S1. This provides flexibility in application for either a splitter or router configuration with a single device. The CYPRESS CY2LL842 is configured as a single two-channel repeater/Mux. The LVDS standard provides a minimum differential output voltage of 247 mV into a 100-ohm load and receipt of as little as 100-mV signals with up to 1V of DC offset between transmitter and receiver. A doubly terminated bus LVDS line enables multipoint configurations. Designed for both point to point based-band multi-point data transmission over controlled impedance lines. Block Diagram Pin Configuration 1DE 1A S0 1A 1B 1Y 1Z 1DE 2A 2Y 2Z 2A S1 2B 2B GND GND 2DE S0 S1 Cypress Semiconductor Corporation Document #: 38-07063 Rev. *A 1 2 3 4 5 6 7 8 CY2LL842 1B VDD 16 15 14 13 12 11 10 9 VDD VDD 1Y 1Z 2DE 2Z 2Y GND 16 pin SOIC/TSSOP • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 15, 2002 ComLink™ Series CY2LL842 Pin Description Pin Number Pin Name 1,2 1B, 1A 3 S0 4 1DE 5 S1 6,7 2A, 2B 8,9 GND 10,11 2Y, 2Z 12 2DE 14,13 IY, 1Z 15,16 VDD Pin Description Differential Input Channel 1 Function Select 0 Data Enable Channel 1 Function Select 1 Differential Input Channel 2 Ground Differential Output Channel 2 Data Enable Channel 2 Differential Output Channel 1 Supply Voltage Table 1. Mux Function Table Output[1] Input S0 0 1 0 1 S1 0 0 1 1 1Y/1Z 1A/1B 2A/2B 1A/1B 2A/2B Function 2Y/2Z 1A/1B 2A/2B 2A/2B 1A/1B Splitter A Splitter B Pass Thru Router Cross Point Router Table 2. Absolute Maximum Rating Over Operating Free-air Temperature[2] Supply Voltage Range, VDD(1) –0.5V to 4V Voltage Range (DE,S0,S1) –0.5V to 6.0V Input Voltage Range, VIN (A or B) –0.5V to VDD+0.5V ESD (All pins) Class 3, A: 2KV, B: 500V Storage Temperature Range –65°C to 150°C [3] Table 3. Recommended Operating Conditions Parameter VDD VIH VIL VID VIC TA Description Min. Supply Voltage 3 High-level Input Voltage (S0,S1,1DE,2DE) 2 Low-level Input Voltage (S0,S1,1DE,2DE) Magnitude of Differential Input Voltage 0.1 Common Mode Input Voltage ( see Figure 6,Figure 7, and Figure 8) VID/2 Operating Free Air Temperature –40 Typ. 3.3 Max. 3.6 Unit V 0.8 0.6 2.4–(VID/2) 85 °C Table 4. Receiver Electrical Characteristics Over Recommended Operating Conditions Parameter VITH+ VITHII Description Positive-going Differential Input Voltage Threshold Negative-going Differential Input Voltage Threshold Input Current ( A Inputs) II Input Current (B Inputs) II (Off) Power-off Current (A or B Inputs) Test Conditilons VCM = 1.2V VCM = 1.2V VI = 0V VI = 2.4V VI = 0.8V VI = 2.4V VDD = 0V Min. Typ. –100 –0.5 0.5 0.1 Max. 100 –10 –10 10 10 10 Unit mV mV uA uA uA uA uA Notes: 1. See Figure 1. 2. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07063 Rev. *A Page 2 of 14 ComLink™ Series CY2LL842 Table 5. Receiver Electrical Characteristics Over Recommended Operating Conditions Parameter Description VOD Differential Output Voltage Swing ~VOD Change in differential Output Voltage Swing between logic states VOC(SS) Steady State Common-mode output voltage ~VOC(SS) Change in Steady State Common-mode output between logic states VOC(PP) Peak to Peak Common-mode output voltage ICC Supply Current Test Conditions RL = 100 Ohm Min. Typ. Max. Unit See Figure 9 247 340 –50 See Figure 10 1.125 –50 3 454 mV 50 mV 1.375 V 50 mV 150 mV No load f = 100 MHz 25 mA RL = 100 ohm f = 100 MHz 25 mA 20 mA Both Channels Disabled f = 100 MHz IH High-level Input Current S0,S1,DE VIH = 5V 20 IIL Low-level Input Current S0,S1,DE IOS Short-circuit Current VIL = 0.8V 5 IOZ High-impedance Output Current VOD = 60mV 0.1 1 VO= 0V or VDD 0.1 1 Cin Input Capacitance 1A, 1B, 2A, 2B 3 pF Control Input Capacitance S0, S1, 1DE, 2DE 8 pF VOY or V0Z = 0V uA uA 20 VOD = 0V mA 20 uA Table 6. Differential Receiver to Driver Switching Characteristics Over Recommended Operating Conditions[5] Parameter Description Test Conditions CL = 10 pF (see Figure 11) Min. Typ.[4] Max. Unit 4 6 nS 4 6 nS TPLH Differential Propagation delay, low to high TPHL Differential Propagation delay, high to low Tsk(p) Pulse Skew ( TPHL–TPLH) Tr Transition Low to High 800 1500 pS Tf Transition High to Low 800 1500 pS 0.2 (see Figure 12) nS TPHZ Propagation delay, high-level to high-impedance output 4 10 nS TPLZ Propagation delay, low-level to high-impedance output 4.3 10 nS TPZH Propagation delay, high-impedance to high-level output 3 10 nS TPZL Propagation delay, high-impedance to low-level output 2 10 nS TPHL_skR1_Dx Channel to Channel skew-receiver 1 to Any mux related drivers 95 pS TPLH_skR1_Dx Channel to Channel skew-receiver 1 to Any mux related drivers 95 pS TPPHL_skR2_Dx Channel to Channel skew-receiver 2 to Any mux related drivers 95 pS TPLH_skR2_Dx Channel to Channel skew-receiver 2 to Any mux related drivers 95 pS DJ(P-P) Deterministic Jitter (100 MHz 25C VID = 0.4 So,S1=00) 95 pS PRBS Differential Notes: 4. All typical values are measured at 25°C with a 3.3V supply. 5. These parameters are measured over supply voltage and temperature ranges recommended for the device. Document #: 38-07063 Rev. *A Page 3 of 14 ComLink™ Series CY2LL842 High-frequency Parametrics Parameter Fmax Description Test Conditions Min. Maximum frequency VDD = 3.3V 50% duty cycle tW(50–50) Standard Load Circuit. Max. Unit 400 MHz Splitter O ptions Router Options S 0/S 1 1A /1B Typ. S 0/S1 1Y/1Z Cross Point Router 1A/1B 1Y/1Z Splitter A 2A/2B 2Y /2Z 1Y/1Z 1A/1B 1Y/1Z 2Y/2Z 2A /2B 2A/2B 2Y/2Z 1A /1B 2A/2B Pass Thru Router Splitter B S 0/S 1 2Y /2Z S 0/S1 Figure 1. 2 Channel Cross Point Switch/Mux Document #: 38-07063 Rev. *A Page 4 of 14 ComLink™ Series CY2LL842 Dynamic IDD CY2LL842C VID=0.4, VIC=1.2V S0, S1=01 Temp = 25°C 45.00 45.00 40.00 40.00 35.00 35.00 Idd (mA) Idd (mA) Dynamic IDD CY2LL842C VID=0.4, VIC=1.2V S0, S1=00 Temp = 25°C 30.00 25.00 30.00 25.00 Vdd=3.00V Vdd=3.00V Vdd=3.30V 20.00 20.00 Vdd=3.30V Vdd=3.60V Vdd=3.60V 15.00 15.00 50 100 150 200 250 300 350 50 400 100 150 Fin (MHz) 250 300 350 400 Fin (MHz) Dynamic IDD CY2LL842C VID=0.4, VIC=1.2V S0, S1=00 Temp = 85°C Dynamic IDD CY2LL842C VID=0.4, VIC=1.2V S0, S1=01 Temp = 85°C 45.00 45.00 40.00 40.00 35.00 35.00 Idd (mA) Idd (mA) 200 30.00 25.00 Vdd=3.00V 30.00 25.00 Vdd=3.30V 20.00 Vdd=3.60V Vdd=3.00V 20.00 Vdd=3.30V Vdd=3.60V 15.00 15.00 50 100 150 200 250 300 350 400 50 100 150 200 250 300 350 400 Fin (MHz) Fin (MHz) Figure 2. IDD vs. Frequency Document #: 38-07063 Rev. *A Page 5 of 14 ComLink™ Series CY2LL842 20 70 120 170 220 1Y/1Z 1. 21 1. 4 21 4 1. 1.215 21 1. 5 21 5 1. 21 5 1. 21 5 1. 21 6 1 1..21 1.2177 21 6 V OC(ss) [V] 1.300 1.250 1.200 1.150 1.100 1. 21 4 1. 21 4 VDD = 3V, Temp = 25°C 270 2Y/2Z 320 Freq (M Hz) 20 70 120 170 220 270 1. 2 1. 17 21 7 1. 21 7 1. 21 7 1. 2 1. 18 21 1. 8 21 8 1. 21 7 1. 21 8 1. 1.2 1.21199 21 9 V OC(ss) [V] 1.300 1.250 1.200 1.150 1.100 1. 21 9 VDD = 3V, Temp = 85°C 1Y/1Z 2Y/2Z 320 Freq (MHz) Figure 3. VOC(ss) of PRBS at Network Frequencies VDD=3V , Temp = 25°C 0.500 1Y Vod (V) 0.400 1Z 0.300 2Y 0.200 2Z 0.100 20 70 120 170 220 270 320 Freq (MHz) VDD = 3V, Temp = 85°C Vod (V) 0.500 1Y 0.400 1Z 0.300 2Y 0.200 2Z 0.100 20 70 120 170 220 270 320 Freq (MHz) Figure 4. VOD of PRBS at Network Frequencies Document #: 38-07063 Rev. *A Page 6 of 14 ComLink™ Series CY2LL842 1Y 120 220 320 2Y 3. 2 3. 0 4. 0 5. 7 6. 7.4 7 5. 6 7. 3 15 .2 20 1Z 8. 0 80.0 60.0 40.0 20.0 0.0 4 50 30 0.0 .1 .3 PW(Min) [nS] VDD = 3.0V, Temp = 25°C 2Z Freq (MHz) 1Y 1Z 20 120 220 2Z 4. 0 3. 7 6 6..4 5. 0 6 5. 0 0 8. 15 .2 2Y 3. 2 3. 0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 4 50 30 0.0 .0 .3 PW(Min) [nS] VDD = 3.0V, Temp = 85°C 320 Freq (MHz) Figure 5. PRBS Waveform Minimum Pulse DJ Deterministic Jitter, Temp = 25°C ps - Peak to Peak 300 250 200 150 100 50 0 20 70 120 170 220 270 320 Freq (MHz) Figure 5. Determinate Jitter Document #: 38-07063 Rev. *A Page 7 of 14 ComLink™ Series CY2LL842 VDD = 3.3V, Tem p = 25°C 6.000 TPLH [nS] 5.500 V ID 0.100 5.000 0.400 4.500 0.600 4.000 3.500 0 0.5 1 1.5 2 2.5 V IC Figure 6. TPLH vs VIC 3.3V, 50 MHz VDD = 3.3V, Temp = 25°C 6.500 TPHL[nS] 6.000 VID 5.500 0.100 5.000 0.400 0.600 4.500 4.000 3.500 0 0.5 1 1.5 2 2.5 VIC Figure 7. TPHL vs. VIC 3.3V, 50 MHz Document #: 38-07063 Rev. *A Page 8 of 14 ComLink™ Series CY2LL842 VDD = 3.3V, Tem p = 25°C 400 300 VID 0.100 TPLH-TPHL (pS) 200 0.200 100 0.300 0 -100 0 0.5 1 1.5 2 2.5 0.400 0.500 0.600 -200 -300 -400 VIC (V) Figure 8. TPLH-TPHL vs VIC 3.3V 50 MHz A Pulse Generator B Y R D RL Z DE CL = 10pF 10 pF VI(A) 1.4V VI(B) 1.0V 100% 80% 0.0V 20% 0% tF tR Figure 9. Test Circuit and Voltage Definitions for the Differential Output Signal[6,7,8] Document #: 38-07063 Rev. *A Page 9 of 14 ComLink™ Series CY2LL842 A Y Pulse B Generator R D RL Z DE CL = 10pF 10 pF VI(A) 1.4V VI(B) 1.0V Voc (pp) VDD Voc (ss) Figure 10. Test Circuit & Voltage Definitions for the Driver Common-Mode Output Voltage[6,7,8,9] A P u lse G e n e ra to r B R D Y Z RL & RC DE 10 pF 10 pF V IA 1 .4 V 0 V D i f f e r e n t ia l 1 .2 V C M 1 .0 V V IB 1 .4 V V0Y 0 V D if f e r e n t ia l 1 .2 V C M V0Z 1 .0 V TPHL T P LH 80% 0 V D iffe re n tia l 20% V0Y - V0Z tR tF Figure 11. Test Circuit & Voltage Definitions for the Driver Common-Mode Output Voltage[6,10] Notes: 6. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF £ 1 nS; pulse rep rate = 50 MppS; pulse width = 10 ± 0.2 nS. 7. RL = 100 Ohm. 8. CL includes instrumentation and fixture capacitance within 6 mm of the DUT. 9. VOC measurement requires equipment with a 3-dB bandwith of at least 300 MHz. 10. RL = 100 Ohm ± 1%. Document #: 38-07063 Rev. *A Page 10 of 14 ComLink™ Series CY2LL842 RL/2 (See Note B) A 1.0 V or 1 .2V B Y R D 1 .2V 1.2V Z (See Note A) DE CL =10 pF 2 .0 V 1 .4V DE 0 .8 V 1 .4 V T PZH 1 .25V T PZH V0Y or V0Z V0Y or V0Z 1 .2 V 1 .2 V T P LZ 1 .15V 1 .0 V Figure 12. Differential Receiver to Driver Propagation Delay and Driver Transition Time[6,10,11] Application Engineering Typical Characteristics (@ VDD = 3.3V/TA = 25C) CY2LL842 Z O =50 RL=100 ohm Pulse Generator Z O =50 CL = 10pF 2 locations Current (ma) 5 0 Voh - Ioh -5 -10 -15 0 Figure 13. Termination Scheme for 100-Ohm External Termination 1 2 3 4 Voltage ZO=50 100 ohm R e c e iv e r c h ip w ith 1 0 0 O h m o n c h ip te rm in a tio n Figure 15. VOH vs IOH ZO=50 CY2LL842 CL CL Figure 14. Termination Scheme for 100-Ohm Self-termination Interface Chip Current (ma) 4 3 2 Vol - Iol 1 0 -1 0 1 2 3 4 Voltage Figure 16. VOL vs IOL Note: 11. Point to Point: RL = 100 Ohm ± 1% CL 3 pF. Document #: 38-07063 Rev. *A Page 11 of 14 ComLink™ Series CY2LL842 Table 7. Technical Notes on STD Drive (LL842, A and D) vs. High Drive (LL843, B and C)[12] A B C D Unit VOX 1.2 1.2 1.2 1.2 V DC Offset 1.0 1.0 1.0 1.0 V VOD Min 0.25 0.5 0.25 0.125 V VOD Max 0.45 0.9 0.45 0.225 V T/Rise 1.4 1.4 0.6 0.6 ns T/Fall 1.4 1.4 0.6 0.6 ns Standard Drive Current drive of 1i A +/i D +/i 100 ohm 50 ohm Hi Drive Current drive of 2i 100 ohm B +/2i 25 ohm +/2i 50 ohm C 25 ohm Figure 17. Comparison Standard Drive ‘842 vs. High Drive ‘843 Ordering Information Part Number Package Type Product Flow CY2LL842SI 16-lead SOIC Industrial, –40° to 85°C CY2LL842SIT 16-lead SOIC–Tape and Reel Industrial, –40°C to 85°C CY2LL842ZI 16-lead TSSOP Industrial, –40° to 85°C CY2LL842ZIT 16-lead TSSOP–Tape and Reel Industrial, –40°C to 85°C CY2LL842SC 16-lead SOIC Commercial, 0°C to 70°C CY2LL842SCT 16-lead SOIC–Tape and Reel Commercial, 0°C to 70°C CY2LL842ZC 16-lead TSSOP Commercial, 0°C to 70°C CY2LL842ZCT 16-lead TSSOP–Tape and Reel Commercial, 0°C to 70°C Package Drawings 16-lead (150-mil) Molded SOIC S16 51-85068-A Note: 12. See Figure 17. Document #: 38-07063 Rev. *A Page 12 of 14 ComLink™ Series CY2LL842 16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07063 Rev. *A Page 13 of 14 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. ComLink™ Series CY2LL842 Document Title: ComLink™ Series CY2LL842 Two-channel LVDS Repeater/Mux Document Number: 38-07063 ECN No. Issue Date Orig. of Change ** 116746 08/01/02 HWT *A 122749 12/15/02 RBI REV. Document #: 38-07063 Rev. *A Description of Change New Data Sheet Added power-up requirements to operating conditions information. Page 14 of 14