ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ 8-Mb (512K x 16) Pseudo Static RAM Features • Wide voltage range: 2.70V–3.30V • Access Time: 70 ns • Ultra-low active power — Typical active current: 2.0 mA @ f = 1 MHz — Typical active current: 11 mA @ f = fmax • Ultra low standby power • Easy memory expansion with CE, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Offered in a 48-ball BGA Package Functional Description[1] The CYK512K16SCCAU is a high-performance CMOS pseudo static RAM organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active Logic Block Diagram 512K x 16 RAM Array 1T SENSE AMPS DATA IN DRIVERS ROW DECODER A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption by more than 99% when deselected using CE LOW, CE2 HIGH or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH, CE2 LOW OE is deasserted HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling even when the chip is selected (Chip Enable CE LOW, CE2 HIGH and both BHE and BLE are LOW). Reading from the device is accomplished by asserting the Chip Enables (CE LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes. I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 BHE WE OE BLE CE2 CE Power -Down Circuit Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05425 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 8, 2004 ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ Pin Configuration[2, 3, 4] FBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 GND A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F A12 A13 WE I/O7 G A9 A10 A11 NC/ I/O15 A18 NC/ A8 H Note: 2. DNU pins have to be left floating or tied to Vss. 3. Ball G2, H6 are expansion pins to 16-Mbit and 32-Mbit densities, respectively. 4. NC “no connect” - not connected internally to the die. Document #: 38-05425 Rev. ** Page 2 of 10 ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ Maximum Ratings DC Voltage Applied to Outputs in High Z State[5, 6, 7] ........................................–0.2V to 3.3V (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage[5, 6, 7] .................................... –0.2V to 3.3V Storage Temperature ................................–65°C to + 150°C Ambient Temperature with Power Applied ...........................................–55°C to + 125°C Supply Voltage to Ground Potential ................ –0.4V to 4.6V Output Current into Outputs (LOW)............................ 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC CYK512K16SCCAU Industrial –25°C to +85°C 2.70V to 3.30V Product Portfolio Power Dissipation Product CYK512K16SCCAU-70BAI Speed (ns) VCC Range (V) Min. Typ.[8] Max. 2.70 3.0 3.30 70 Operating ICC(mA) f = 1MHz Typ.[8] 2 f = fmax Standby ISB2(µA) Max. Typ.[8] Max. Typ.[8] Max. 3.5 11 17 55 80 Electrical Characteristics Over the Operating Range CYK512K16SCCAU-70 Parameter Description Test Conditions Min. VCC Supply Voltage 2.7 VOH 2.4 VOL Output HIGH Voltage IOH = –1.0 mA Output LOW Voltage IOL = 2.0 mA VIH Input HIGH Voltage VCC= 2.7V to 3.3V VIL Input LOW Voltage VCC= 2.7V to 3.3V (F = 0) IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels Typ.[8] Max. 3.3 Unit V V 0.4 V 0.8*Vcc VCC + 0.3V V –0.3 0.4 V –1 +1 µA –1 +1 µA 11 17 mA 2.0 3.5 mA 400 µA ISB1 Automatic CE Power-down Current — CMOS Inputs CE > VCC−0.2V or CE2< 0.2V VIN>VCC–0.2V, VIN<0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC=3.30V Vcc = 3.3V ISB2 Automatic CE Power-down Current — CMOS Inputs CE > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.30V Vcc = 3.3V 55 80 µA Vcc = 3.0V 50 70 µA Vcc = 2.8V 45 60 µA Notes: 5. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 6. VIL(MIN) = –0.5V for pulse durations less than 20 ns. 7. Overshoot and undershoot specifications are characterized and are not 100% tested. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25C. 9. Vcc and Vcc must be at minimal operational levels before inputs are turned ON. Document #: 38-05425 Rev. ** Page 3 of 10 ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ Capacitance[10] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance[10] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions BGA Unit 55 °C/W 16 °C/W Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board AC Test Loads and Waveforms R1 VCC OUTPUT VCC 50 pF 10% GND Rise Time = 1 V/ns R2 INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 3.0V VCC Unit R1 1179 Ω R2 1941 Ω RTH 733 Ω VTH 1.87 V Switching Characteristics Over the Operating Range [11] 70 ns Parameter Description Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid 70 tOHA Data Hold from Address Change tACE CE LOW and CE2 HIGH to Data Valid ns 70 tDOE OE LOW to Data Valid tLZOE OE LOW to LOW Z[12, 13] Z[12, 13] 10 ns ns 70 ns 35 ns 5 ns tHZOE OE HIGH to High tLZCE CE LOW and CE2 HIGH to Low Z[12, 13] tHZCE CE HIGH and CE2 LOW to High Z[12, 13] 25 ns tDBE BLE / BHE LOW to Data Valid 70 ns Z[12, 13] tLZBE BLE / BHE LOW to Low tHZBE BLE / BHE HIGH to HIGH Z[12, 13] 25 5 ns ns 5 ns 25 ns Notes: 10. Tested initially and after any design or process changes that may affect these parameters. 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state—100 mV from the steady state. 13. High-Z and Low-Z parameters are characterized and are not 100% tested. Document #: 38-05425 Rev. ** Page 4 of 10 ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ Switching Characteristics Over the Operating Range (continued)[11] 70 ns Parameter tSK Description Min. Address Skew Max. Unit 10 ns Write Cycle[14] tWC Write Cycle Time 70 ns tSCE CE LOW and CE2 HIGH to Write End 60 ns tAW Address Set-up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 45 ns tBW BLE / BHE LOW to Write End 60 ns tSD Data Set-up to Write End 45 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High-Z[12, 13] tLZWE WE HIGH to Low-Z[12, 13] ns 25 5 ns ns Switching Waveforms Read Cycle 1 (Address Transition Controlled)[15] tRC ADDRESS tSK DATA OUT tOHA PREVIOUS DATA VALID tAA DATA VALID Notes: 14. Internal memory write time is defined by overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to edge of signal that terminates the write. 15. WE is HIGH for read cycle. Document #: 38-05425 Rev. ** Page 5 of 10 ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ Switching Waveforms (continued) Read Cycle 2 (OE Controlled)[15] ADDRESS CE tRC tSK tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE DATA OUT tHZOE tDOE tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPU VCC 50% SUPPLY Write Cycle 1 (WE Controlled) [14, 13, 16, 17, 18] 50% ICC tWC ADDRESS tSCE CE CE2 tAW tSA tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA Don’t Care tHZOE Notes: 16. Data I/O is high impedance if OE = VIH. 17. If Chip Enable goes INACTIVE and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. 19. H = VIH, L = VIL, X = Don’t Care. Document #: 38-05425 Rev. ** Page 6 of 10 ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ Switching Waveforms (continued) Write Cycle 2 (CE or CE2 Controlled) [14, 13, 16, 17, 18] tWC ADDRESS tSCE CE CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA Don’t Care [18] tHZOE Write Cycle 3 (WE Controlled, OE LOW) [17, 18] tWC ADDRESS tSCE CE CE2 tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATAI/O Don’t Care VALID DATA tHZWE Document #: 38-05425 Rev. ** tHD tLZWE Page 7 of 10 ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ Switching Waveforms (continued) Write Cycle 4 (BHE/BLE Controlled, OE LOW)[17, 18] tWC ADDRESS CE CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD Don’t Care DATA I/O tHD VALID DATA Truth Table[19] CE CE2 WE OE BHE BLE H X X X X X Inputs/Outputs High Z Mode Power Deselect/Power-down Standby (ISB) X L X X X X High Z Deselect/Power-down Standby (ISB) X X X X H H High Z Deselect/Power-down Standby (ISB) L H H L L L Data Out (I/O0 – I/O15) Read Active (ICC) L H H L H L Data Out (I/O0 – I/O7); High Z (I/O8 – I/O15) Read Active (ICC) L H H L L H High Z (I/O0 – I/O7); Data Out (I/O8 – I/O15) Read Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H L X L L Data In (I/O0 – I/O15) Write Active (ICC) L H L X H L Data In (I/O0 – I/O7); High Z (I/O8 – I/O15) Write Active (ICC) L H L X L H High Z (I/O0 – I/O7); Data In (I/O8 – I/O15) Write Active (ICC) Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 70 CYK512K16SCCAU-70BAI BA48K 48-ball Fine Pitch BGA (6 mm × 8mm × 1.2 mm) Industrial Document #: 38-05425 Rev. ** Page 8 of 10 ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ Package Diagram 48-Ball (6 mm x 8 mm x 1.2 mm) FBGA BA48K TOP VIEW BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) A1 CORNER 1 2 3 4 5 6 6 5 4 3 2 A A C E F D E F 2.625 8.00±0.10 8.00±0.10 D 0.75 B C 5.25 B G G H H A 1.875 A 0.75 6.00±0.10 B 3.75 B 0.15 C 0.21±0.05 0.53±0.05 0.25 C 1 6.00±0.10 0.15(4X) REFERENCE JEDEC MO-207 C 1.20 MAX 0.36 SEATING PLANE 51-85193-*A MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-05425 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. ADVANCE INFORMATION CYK512K16SCCAU MoBL3™ Document History Page Document Title: CYK512K16SCCAU 8-Mb (512K x 16) Pseudo Static RAM Document Number: 38-05425 REV. ** ECN NO. Issue Date 130538 01/27/2004 Document #: 38-05425 Rev. ** Orig. of Change AWK Description of Change New Data Sheet Page 10 of 10