CYK256K16SCCB 4-Mbit (256K x 16) Pseudo Static RAM Features in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption dramatically when deselected (CE1 LOW, CE2 HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1 HIGH, CE2 LOW, OE is deasserted HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). • Advanced low-power MoBL® architecture • High speed: 55 ns, 60 ns and 70 ns • Wide voltage range: 2.7V to 3.3V • Typical active current: 1 mA @ f = 1 MHz • Low standby power • Automatic power-down when deselected Functional Description[1] The CYK256K16SCCB is a high-performance CMOS pseudo static RAM (PSRAM) organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) Logic Block Diagram 256K x 16 RAM Array SENSE AMPS DATA IN DRIVERS ROW DECODER A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Reading from the device is accomplished by asserting the Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins A0 through A17 will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes. I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 BHE WE CE2 CE1 OE BLE Power -Down Circuit BHE BLE CE2 CE1 Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05526 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 18, 2006 [+] Feedback CYK256K16SCCB Pin Configuration[3, 4, 5] 48-ball VFBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 DNU A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Product Portfolio Power Dissipation Operating, ICC (mA) VCC Range (V) Product Min. Typ. Max. CYK256K16SCCB 2.7 3.0 3.3 f = 1 MHz f = fMAX Standby, ISB2 (µA) Speed (ns) Typ.[2] Max. Typ.[2] Max. Typ.[2] Max. 55 1 5 14 22 17 40 8 15 60 70 Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C. 3. Ball H1, G2, H6 are the address expansion pins for the 8-Mb, 16-Mb, and 32-Mb densities, respectively. 4. NC “no connect”—not connected internally to the die. 5. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper application. Document #: 38-05526 Rev. *H Page 2 of 10 [+] Feedback CYK256K16SCCB DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V Maximum Ratings Output Current into Outputs (LOW) ............................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current .................................................... > 200 mA Ambient Temperature with Power Applied .............................................. –40°C to +85°C Operating Range Supply Voltage to Ground Potential ................ −0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State[6, 7, 8] ....................................... −0.4V to 3.7V Range Ambient Temperature (TA) VCC Industrial −25°C to +85°C 2.7V to 3.3V DC Electrical Characteristics (Over the Operating Range) CYK256K16SCCB -55, 60, 70 Parameter Description Test Conditions VCC Supply Voltage VOH Output HIGH Voltage IOH = −0.1 mA VOL Output LOW Voltage IOL = 0.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage F=0 IIX Input Leakage Current IOZ ICC Min. Typ.[2] Max. Unit 2.7 3.0 3.3 V VCC – 0.4 V 0.4 V 0.8 * VCC VCC + 0.4 V −0.4 0.62 V GND < VIN < Vcc −1 +1 µA Output Leakage Current GND < VOUT < Vcc, Output Disabled −1 +1 µA VCC Operating Supply Current f = fMAX = 1/tRC VCC = 3.3V, IOUT = 0 mA, CMOS level 22 for –55 22 for –60 15 for –70 mA 14 for –55 14 for –60 8 for –70 f = 1 MHz 1 for all speeds 5 for all speeds ISB1 CE > VCC − 0.2V, CE2 < 0.2V Automatic CE1 Power-down Current VIN > VCC − 0.2V, VIN < 0.2V, —CMOS Inputs f = fMAX(Address and Data Only), f = 0 (OE, WE, BHE and BLE) 150 250 µA ISB2 Automatic CE1 CE > VCC − 0.2V, CE2 < 0.2V Power-down Current VIN > VCC − 0.2V or VIN < 0.2V, —CMOS Inputs f = 0, VCC = 3.3V 17 40 µA Capacitance[9] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. Unit 8 pF 8 pF Thermal Resistance[9] Parameter Description θJA Thermal Resistance (Junction to Ambient) θJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. VFBGA Unit 55 °C/W 17 °C/W Notes: 6. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 7. VIL(MIN) = –0.5V for pulse durations less than 20 ns. 8. Overshoot and undershoot specifications are characterized and are not 100% tested. 9. Tested initially and after design or process changes that may affect these parameters. Document #: 38-05526 Rev. *H Page 3 of 10 [+] Feedback CYK256K16SCCB AC Test Loads and Waveforms R1 VCC OUTPUT VCC 10% GND R2 30 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH Parameters 3.0V VCC Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 V Switching Characteristics (Over the Operating Range)[10] –55 Parameter Description Min. –60 Max. Min. –70 Max. Min. Max. Unit Read Cycle 55[14] tRC Read Cycle Time tAA Address to Data Valid 60 tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[11, 12] tHZOE OE HIGH to High Z[11, 12] tLZCE CE1 LOW and CE2 HIGH to Low Z[11, 12] tHZCE CE1 HIGH and CE2 LOW to High Z[11, 12] 25 25 25 ns tDBE BLE/BHE LOW to Data Valid 55 60 70 ns 55 5 8 55 5 10 5 5 5 35 5 25 ns ns ns 25 5 5 ns ns 70 25 5 25 ns 70 60 25 Z[11, 12] 70 60 ns ns tLZBE BLE/BHE LOW to Low tHZBE BLE/BHE HIGH to High-Z[11, 12] 10 10 5 25 ns ns tSK[14] Address Skew 0 5 10 ns [13] Write Cycle tWC Write Cycle Time 55 60 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 45 45 60 ns tAW Address Set-up to Write End 45 45 55 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns Notes: 10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance 11. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. Document #: 38-05526 Rev. *H Page 4 of 10 [+] Feedback CYK256K16SCCB Switching Characteristics (Over the Operating Range)[10] (continued) –55 Parameter Description Min. –60 Max. Min. –70 Max. Min. Max. Unit tPWE WE Pulse Width 40 40 45 ns tBW BLE/BHE LOW to Write End 50 50 55 ns tSD Data Set-up to Write End 25 25 25 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[11, 12] tLZWE WE HIGH to Low Z[11, 12] 0 25 5 0 25 ns 25 5 5 ns ns Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15, 16] tRC ADDRESS tSK DATA OUT tOHA tAA PREVIOUS DATA VALID DATA VALID Read Cycle 2 (OE Controlled)[14, 16] ADDRESS CE1 tRC tSK tHZCE CE2 tACE BHE/BLE tLZBE tDBE tHZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE DATA VALID HIGH IMPEDANCE tLZCE t VCC PU Notes: 15. Device is continuously selected. OE, CE = VIL. 16. WE is HIGH for Read Cycle. Document #: 38-05526 Rev. *H ICC Page 5 of 10 [+] Feedback CYK256K16SCCB Switching Waveforms (continued) Write Cycle No. 1(WE Controlled)[12, 13, 17, 18, 19] tWC ADDRESS tSCE CE1 CE22 CE tAW tSA tHA tPWE WE tBW BHE/ BLE OE t SD DATA I/O tHD VALID DATA DO N’T CARE tHZOE Notes: 17. Data I/O is high impedance if OE > VIH. 18. If Chip Enable goes INACTIVE simultaneously with WE =HIGH, the output remains in a high-impedance state. 19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05526 Rev. *H Page 6 of 10 [+] Feedback CYK256K16SCCB Switching Waveforms (continued) Write Cycle 2 (CE1 or CE2 Controlled)[12, 13, 17, 18, 19] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA DON’T CARE tHZOE Write Cycle 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATAI/O DON’T CARE VALID DATA tHZWE Document #: 38-05526 Rev. *H t HD tLZWE Page 7 of 10 [+] Feedback CYK256K16SCCB Switching Waveforms (continued) Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18, 19] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE t HD tSD DON’T CARE DATA I/O t HD VALID DATA Truth Table[20] CE1 CE2 WE OE BHE BLE Inputs/Outputs H X X X X X X L X X X X High Z Deselect/Power-down Standby (ISB) X X X X H H High Z Deselect/Power-down Standby (ISB) L H H L L L Data Out (I/O0–I/O15) Read (Upper Byte and Lower Byte) Active (ICC) L H H L H L Data Out (I/O0–I/O7); I/O8–I/O15 in High Z Read (Upper Byte only) Active (ICC) L H H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read (Lower Byte only) Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower Byte) Active (ICC) L H L X H L Data In (I/O0–I/O7); I/O8–I/O15 in High Z Write (Lower Byte Only) Active (ICC) L H L X L H Data In (I/O8–I/O15); I/O0 –I/O7 in High Z Write (Upper Byte Only) Active (ICC) High Z Mode Deselect/Power-down Power Standby (ISB) Note: 20. H = Logic HIGH, L = Logic LOW, X = Don’t Care. Document #: 38-05526 Rev. *H Page 8 of 10 [+] Feedback CYK256K16SCCB Ordering Information Speed (ns) Ordering Code 55 CYK256K16SCCBU-55BVI Package Diagram Operating Range Package Type 51-85150 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) CYK256K16SCBU-55BVXI Industrial 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 60 CYK256K16SCCBU-60BVI 51-85150 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) Industrial 70 CYK256K16SCCBU-70BVI 51-85150 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) Industrial CYK256K16SCBU-70BVXI 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Package Diagram 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 6.00±0.10 0.15(4X) 0.10 C 0.21±0.05 0.25 C 0.55 MAX. B 51-85150-*D C 1.00 MAX 0.26 MAX. SEATING PLANE MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05526 Rev. *H Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CYK256K16SCCB Document History Page Document Title: CYK256K16SCCB 4-Mbit (256K x 16) Pseudo Static RAM Document Number: 38-05526 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 215621 See ECN REF New data sheet *A 218183 See ECN REF Changed ball E3 on package pinout from DNU to NC *B 230855 See ECN AJU Changed from Advance Information to Preliminary Modified MAX limit on DC Input voltage in ‘Maximum Ratings’ section Fixed package name typo in ‘Thermal Resistance’ table Changed ordering code from CYK256K16SCCB to CYK256K16SCCBU in ‘Ordering Information’ section *C 234474 See ECN SYT Changed ball E3 on package pinout from NC to DNU. *D 260330 See ECN PCI Changed from Preliminary to Final *E 298651 See ECN PCI Added 60-ns speed bin *F 314013 See ECN RKF Added Pb-Free parts to the Ordering information *G 522566 See ECN NXR Changed VIL Max spec from 0.4 V to 0.6 V in DC Electrical Characteristics table *H 562386 See ECN NXR Changed VIL Max spec from 0.6 V to 0.62 V in DC Electrical Characteristics table Document #: 38-05526 Rev. *H Page 10 of 10 [+] Feedback