ETC PI74ALVCH16269

PI74ALVCH16269
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12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
Product Features
Product Description
• PI74ALVCH16269 is designed for low voltage operation
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
The PI7ALVCH16269 is used in applications in which two separate
ports must be multiplexed onto, or demultiplexed from, a single port.
It is particularly suitable as an interface between synchronous DRAM’s
and high-speed microprocessors.
Data is stored on the internal B-port registers on the low-to-high
transition of the clock (CLK) input when the appropriate clock-enable
(CLKENA) inputs are low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit word on the B-port.
For data transfer in the B-to-A direction, a single storage register is
provided. The select (SEL) line selects 1B or 2B data for the A outputs.
The register on the A output permits the fastest possible data transfer,
thus extending the period during which the data is valid on the bus. The
control terminals are registered so that all transactions are synchronous
with CLK. Data flow is controlled by the active-low output enables
(OEA, OEB1, and OEB2).
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to VCC through a pullup resistor; the minimum value
of the resistor is determined by the current-sinking capability of the
driver. Because OE is being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the
first clock pulse.
Logic Block Diagram
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
1
PS8379
04/16/99
PI74ALVCH16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
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Truth Tables(1)
Product Pin Description
Pin Name
OE
CLK
SEL
CLKEN
A,1B,2B
GND
VCC
Inputs
Description
Output Enable Input (Active LOW)
Clock
Select (Active Low)
Clock Enable (Active Low)
3-State Outputs
Ground
Power
Outputs
CLK
OEA
OEB
A
1B,2B
↑
H
H
Z
Z
↑
H
L
Z
Active
↑
L
H
Active
Z
↑
L
L
Active
Active
A to B STORAGE (OEB = L)
Product Pin Configuration
INPUTS
OEA
OEB1
1
2
56
55
OEB2
CLKENA2
2B3
3
4
5
54
53
52
2B4
H
H
GND
L
6
7
8
51
50
49
2B6
VCC
2B7
9
10
48
47
2B8
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
11
46
12 56-PIN 45
13 A56
44
A7
14
15
A8
16
A9
17
GND
18
A10
A11
19
V56
43
42
41
2B5
2B9
2B10
1B
2B
X
X
1B0(2)
2B0(2)
X
↑
L
L
X
L
X
↑
H
H
X
X
L
↑
L
X
L
X
L
↑
H
X
H
B to A STORAGE (OEA = L)
Inputs
1B12
1B11
20
21
38
37
36
1B9
1B8
35
34
33
VCC
1B6
1B2
22
23
24
GND
1B3
25
26
32
31
GND
1B4
NC
27
28
30
29
CLKENA1
SEL
A
2B11
2B12
1B10
VCC
1B1
CLK
GND
40
39
A12
CLKENA1 CLKENA2
OUTPUTS
GND
1B7
1B5
CLK
SEL
1B
2B
Outputs
A
X
H
X
X
A0(2)
X
L
X
X
A0(2)
↑
H
L
X
L
↑
H
Η
X
H
↑
L
X
L
L
↑
L
X
H
H
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
↑ = Transition, Low to High
2. Output level before indicated steady
state input conditions established.
CLK
2
PS8379
04/16/99
PI74ALVCH16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Storage Temperature ................................................ –65°C to +150°C
Stresses greater than those listed under MAXIMUM
Supply Voltage Range, VCC ................................................. –0.5V to 4.6V
RATINGS may cause permanent damage to the device.
Input Voltage Range,VI: Except
This is a stress rating only and functional operation of the
I/O ports(1) ................................................................................ –0.5V to 4.6V
device at these or any other conditions above those
indicated in the operational sections of this specification
I/O ports(1,2) ............................................................... –0.5V to VCC + 0.5V
(1,2)
is not implied. Exposure to absolute maximum rating
Output Voltage Range, VO
.............................. –0.5V to VCC + 0.5V
conditions for extended periods may affect reliability.
Input Clamp current, IIK (VI < 0) ............................................ –50mA
Output Clamp current, IOK (VO < 0) ....................................... –50mA
Continous Output Current, IO .................................................. ±50mA
Continous Current through each VCC or GND ...................... ±100mA
Maximum Power Dissipation:
A package ........................................................................................ 1W
V package ..................................................................................... 1.4W
Notes:
1. The input and output negative-voltage ratings maybe exceeded if the input
and outputclamp-current ratings are observed.
2. This value is limited to 4.6V maximum.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%)
Parame te rs
De s cription
Te s t Conditions
M in.
Typ.
VCC
Supply Voltage
VIH(1)
Input HIGH Voltage
VIL(1)
Input LOW Voltage
VIN(1)
Input Voltage
0
VCC
VOUT(1)
Output Voltage
0
VCC
IOH(1)
HIGH- level
Output Current
IOL(1)
LOW- level
Output Current
2.3
M ax.
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2.0
3.6
VCC = 2.3V to 2.7V
0.7
VCC = 2.7V to 3.6V
0.8
VCC = 2.3V
- 12
VCC = 2.7V
- 12
VCC = 3.0V
- 24
VCC = 2.3V
12
VCC = 2.7V
12
VCC = 3.0V
24
TA
Operating Free- Air Temperature
At/∆V
Input Transition Rise or Fall Rate
- 40
Units
V
mA
85
ºC
10
ns/V
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3
PS8379
04/16/99
PI74ALVCH16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
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DC Electrical Characteristics-Continued (Over the Operating Range, TA = -40ºC to +85ºC, VCC = 3.3V ±10%
Parame te rs
VCC(1)
M in.
Min. to Max.
VCC - 0.2
2.3V
2.0
2.3V
1.7
2.7V
2.2
3.0V
2.4
IOH = - 24mΑ
3.0V
2.0
IOL= 100µΑ
Min. to Max.
0.2
IOL = 6mΑ
2.3V
0.4
2.3V
0.7
2.7V
0.4
IOL = 24mΑ
3.0V
0.55
VI = VCC or GND
3.6V
±5
Te s t Conditions
IOH = - 100µΑ
IOH = - 6mΑ
VOH
VOL
II
IOH = - 12mΑ
IOL = 12mΑ
VI = 0.7V
VI = 1.7V
II (Hold)(3)
VI = 0.8V
VI = 2.0V
IOZ(4)
ICC
∆ΙCC
Typ.(2)
M ax.
V
45
2.3V
- 45
3.0V
75
- 75
VI = 0 to 3.6V
3.6V
±500
VO = VCC or GND
3.6V
±10
VI = VCC or GND, IO = 0
3.6V
40
3V to 3.6V
750
O ne input at VCC - 0.6V,
O ther inputs at VCC or GND
Units
CI Control Inputs
VI = VCC or GND
3.3V
3.5
CIO A or B Ports
VO = VCC or GND
3.3V
8.5
µΑ
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25ºC ambient and maximum loading.
3. Bus hold maximum dynamic current required to switch the input from one state to another
4. For I/O ports, the IOZ includes the input leakage current.
4
PS8379
04/16/99
PI74ALVCH16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
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Timing Requirements over Operating Range
Parame te rs
fCLOCK
tW
tSU
tH
D e s cription
VCC = 2.5V ±
0.2V
VCC = 2.7V
VCC = 3.3V ±
0.3V
M in.
M in.
M in.
M ax.
Clock frequency
135
Pulse duration, CLK
High or Low
Setup time
Hold time
M ax.
135
3.3
3.3
3.3
A data before CLK↑
2.0
2.0
1.7
B data before CLK↑
2.2
2.1
1.8
SEL before CLK↑
1.6
1.6
1.3
CLK ENA1 or CLK ENA2
before CLK ↑
1.0
1.2
0.9
O E data before CLK ↑
1.5
1.6
1.3
A data after CLK↑
0.7
0.6
0.6
B data after CLK↑
0.7
0.6
1.6
SEL after CLK↑
1.1
0.7
0.7
CLK ENA1 or CLK ENA2
after CLK ↑
1.0
0.8
1.1
O E after CLK↑
0.8
0.8
0.8
M ax.
Units
135
MHz
ns
Switching Characteristics over Operating Range(1)
Parame te rs
From
(INPUT)
To
(OUTPUT)
M in.(2)
M ax.
135
fMAX
tPD
tEN
VCC = 2.5V ± 0.2V
CLK
tDIS
VCC = 2.7V
M in.(2)
M ax.
VCC = 3.3V ± 0.3V
M in.(2)
135
Units
M ax.
135
B
1.0
8.2
7.3
1.0
6.2
A
1.0
6.4
5.8
1.0
5.0
B
1.0
7.9
6.7
1.0
6.1
A
1.0
7.6
6.2
1.0
5.9
B
1.0
8.1
6.9
1.0
6.1
A
1.0
7.5
6.8
1.0
5.6
ns
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA = 25°C
Parame te r
CPD Power Dissipation
Capacitance per
Exchanger
Outputs Enabled
Outputs Disabled
Te s t
Conditions
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Typical
CL= 0pF,
F = 10 MHz
Units
87
120
80.5
118
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8379
04/16/99