PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74ALVCH162260 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-STATE Outputs Product Features Product Description • PI74ALVCH162260 is designed for low voltage operation Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. • VCC = 2.3V to 3.6V • Hysteresis on all inputs • Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C • Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C • Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors • Industrial operation at 40°C to +85°C • Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V) The PI74ALVCH162260 is a 12-bit to 24-bit multiplexed D-type latch designed for 2.3V to 3.6 VCC operation. It is used in applications where two separate datapaths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device is also useful in memory-interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is HIGH, the latch is transparent. When the latch-enable input goes LOW, the data present at the inputs is latched and remains latched until the latch-enable input is returned HIGH. Logic Block Diagram LE1B LE2B LEA1B LEA2B OE2B 2 27 30 55 56 To reduce overshoot and undershoot, the B-port outputs include 26Ω series resistors. 29 OE1B OEA SEL 28 G1 A1 To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pullup resistor, the minimum value of the resistor is determined by the currentsinking capability of the driver. 1 8 C1 23 1 1 1D 1B1 Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. C1 6 1D 2B1 C1 1D C1 1D TO 11 OTHER CHANNELS 1 PS8127 03/17/98 PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Name OE SEL LE A,1B,2B A,1B,2B GND VCC Truth Tables(1) Description Output Enable Input (Active LOW) Select Latch Enable Data Inputs 3-State Outputs Ground Power B to A (OEB = H) Inputs Product Pin Configuration OEA LE1B 1 2 56 55 OE2B 2B3 2B2 5 54 53 52 2B4 GND 3 4 2B1 6 VCC A1 7 8 56-PIN V56 51 A56 50 49 LEA2B 1B 2B SEL LE1B LE2B OEA H X H H X L H L X H H X L L X X H L X L A0 X H L X H L H X L L X H L L X X L X L L A0 X X X X X H Z GND 2B5 A to B (OEA = H) 2B6 VCC INPUTS 2B7 A OUTPUTS LEA1B LEA2B O E1B O E2B 1B 2B L L H H H L L L L H L L L H 2B0 48 47 2B8 A3 9 10 2B9 H H H GND 11 A4 12 13 46 45 GND 2B10 L H H A2 Output A 44 2B11 14 15 16 43 42 2B12 1B12 L H L L L L 2B0 41 1B11 17 18 40 39 1B10 GND H L H L L 1B0 H L L H L L 1B0 L 19 20 21 38 37 36 1B9 X L L L L 1B0 2B0 X X H H Z Z X X X L H Active Z 1B2 35 34 33 VCC 1B6 1B5 X 22 23 24 GND 1B3 25 26 32 31 GND X X X H L Z Active X X X L L Active Active LE2B 27 28 30 29 LEA1B A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 SEL 1B8 1B7 1B4 Note: 1. H = L = X = Z = OE1B 2 High Signal Level Low Signal Level Irrelevant High Impedance PS8127 03/17/98 PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........................................................... 65°C to +150°C Ambient Temperature with Power Applied ........................ 40°C to +85°C Input Voltage Range, VIN ...................................................... 0.5V to VCC +0.5V Output Voltage Range, VOUT ............................................... 0.5V to VCC +0.5V DC Input Voltage .................................................................... 0.5V to +5.0V DC Output Current ............................................................................ 100 mA Power Dissipation .................................................................................. 1.0W Parame te rs De s cription Te s t Conditions M in. Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Typ. M ax. VCC Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage VIN Input Voltage 0 VCC VOUT Output Voltage 0 VCC IOH IOL IOH IOL TA High- level output current (A Port) Low- level output current (A Port) High- level output current (B Port) Low- level output current (B Port) 2.3 VCC = 2.7V to 3.6V 2.0 VCC = 2.3V to 2.7V 1.7 3.6 VCC = 2.7V to 3.6V 0.8 VCC = 2.3V to 2.7V 0.7 VCC = 2.3V - 12 VCC = 2.7V - 12 VCC = 3.0V - 24 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 VCC = 2.3V -6 VCC = 2.7V -8 VCCC = 3.0V - 12 VCC = 2.3V 6 VCC = 2.7V 8 VCC = 3.0V 12 Operating free- air temperature - 40 Units 85 V mA °C Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 PS8127 03/17/98 PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%) Parame te rs VCC(1) M in. Min. to Max. VCC - 0.2 VIH = 1.7V 2.3 V 2.0 VIH = 1.7V 2.3 V 1.7 Te s t Conditions IOH = - 100mA IOH = - 6mA VOH (A PORT) IOH = - 12mA IOH = - 24mA VIH = 2.0V 2.7 V 2.2 VIH = 2.0V 3.0 V 2.4 VIH = 2.0V 3.0 V 2.0 Min. to Max. VCC - 0.2 VIH = 1.7V 2.3 V 1.9 VIH = 1.7V 2.3 V 1.7 VIH = 2.0V 3.0 V 2.4 IOH = - 100mA IOH = - 4mA VOH (B PORT) IOH = - 6mA IOH = - 8mA VIH = 2.0V 2.7 V 2.0 IOH = - 12mA VIH = 2.0V 3.0 V 2.0 IOL = 100mA IOL = 6mA VOL (A PORT) IOL = 12mA IOL = 24mA VIL = 0.7V 2.3V 0.4 VIL = 0.7V 2.3V 0.7 VIL = 0.8V 2.7V 0.4 VIL = 0.8V 3.0V 0.55 Min. to Max. 0.2 2.3V 0.4 VIL = 0.7V 2.3V 0.55 VIL = 0.8V 3.0V 0.55 IOL = 8mA VIL = 0.8V 2.7V 0.6 IOL = 12mA VIL = 0.8V 3.0V 0.8 3.6V ±5 VOL (B PORT) IOL = 6mA VI = VCC or GND VIN = 0.7V 2.3V VIN = 1.7V VIN = 0.8V 3.0V VIN = 2.0V IOZ(3) ICC DICC 45 - 45 75 - 75 mA VIN = 0 to 3.6V 3.6V ±500 VO = VCC or GND VI = VCC or GND 3.6V ±10 3.6V 40 3.3V to 3.6V 750 One input at VCC = 0.6V. Other inputs at VCC or GND Units V 0.2 VIL = 0.7V IOL = 4mA II (Hold) M ax. Min. to Max. IOL = - 100mA II Typ.(2) CI Control Inputs VIN = VCC or GND 3.3V 3.5 CIO A or B ports VO = VCC or GND 3.3V 4.5 pF Notes: 1. For Max. or Min. conditions use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading. 3. This is the bus-hold maximum dynamic current required to swtich the input from one state to another. 4 PS8127 03/17/98 PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements over Operating Range Parame te rs fCLOCK VCC = 2.5V ± 0.2V De s cription M in. Clock Frequency M ax. VCC = 2.7V M in. VCC = 3.3V ± 0.3V M ax. 150 M in. M ax. 150 150 tW Pulse duration, LE1B, LE2B, LEA1B, or LEA2B High 3.3 3.3 3.3 tSU Setup time, data before LE1B, LE2B, LEA1B, or LEA2B 1.4 1.1 1.1 tH Hold time, data after LE1B, LE2B, LEA1B or LEA2B 1.6 1.9 1.5 Dt/D(1) Input Transition Rise or Fall Units MHz ns 0 10 ns/V Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. Switching Characteristics over Operating Range(1) Parame te rs From To (INPUT) (OUTPUT) fMAX tPD tEN tDIS VCC = 2.5V ± 0.2V M in.(2) M ax. VCC = 2.7V M in.(2) 150 VCC = 3.3V ± 0.3V M ax. 150 M in.(2) M ax.(2) 150 Units MHz A B 1.2 6.5 5.8 1.2 4.9 B A 1.2 6.0 5.1 1.2 4.3 LE A 1.0 6.2 5.2 1.0 4.4 LE B 1.0 6.7 5.9 1.0 5.0 SEL A 1.2 7.5 6.6 1.1 5.6 OE A 1.0 7.2 6.4 1.0 5.4 OE B 1.0 7.7 7.1 1.0 6.0 OE A 1.7 5.9 5.0 1.3 4.6 OE B 1.7 6.4 5.5 1.3 5.1 ns Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Operating Characteristics, TA = 25ºC Parame te r CPD Power Dissipation Capacitance O utputs Enabled O utputs Disabled VCC = 2.5V ± 0.2V Te s t Conditions VCC = 3.3V ± 0.3V Typical CL = 50pF, f = 10 MHz 62 46 29 24 Units pF Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS8127 03/17/98