STD35NF3LL STD35NF3LL-1 N-CHANNEL 30V - 0.014 Ω - 35A IPAK/DPAK STripFET II POWER MOSFET TYPE STD35NF3LL STD35NF3LL-1 ■ ■ ■ ■ ■ ■ ■ VDSS R DS(on) ID 30 V 30 V < 0.0195 Ω < 0.0195 Ω 35 A 35 A TYPICAL RDS(on) = 0.016 Ω @ 4.5V OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DRIVE THROUGH-HOLE IPAK (TO-251) POWER PACKAGE IN TUBE (SUFFIX “-1”) SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX “T4”) DESCRIPTION 3 3 1 2 1 IPAK TO-251 (Suffix “-1”) DPAK TO-252 (Suffix “T4”) INTERNAL SCHEMATIC DIAGRAM This application specific Power MOSFET is the third genaration of STMicroelectronis unique ”Single Feature Size ” strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR VGS Parameter Unit Drain-source Voltage (VGS = 0) 30 V Drain-gate Voltage (RGS = 20 kΩ) 30 V ± 16 V Gate- source Voltage ID Drain Current (continuos) at TC = 25°C 35 A ID Drain Current (continuos) at TC = 100°C 25 A Drain Current (pulsed) 140 A Total Dissipation at TC = 25°C Derating Factor 50 W 0.33 W/°C Single Pulse Avalanche Energy 300 mJ -55 to 175 °C IDM(•) Ptot E AS (1) Tstg Tj Storage Temperature Max. Operating Junction Temperature (•) Pulse width limit ed by safe operating area. February 2002 . Value (1) Starting Tj = 25 oC, ID = 17.5 A, VDD= 24 V 1/10 STD35NF3LL/STD35NF3LL-1 THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max Typ °C/W °C/W °C 3 100 300 ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (V GS = 0) VDS = Max Rating VDS = Max Rating TC = 100°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 16 V V(BR)DSS Min. Typ. Max. 30 Unit V 1 10 µA µA ±100 nA Max. Unit ON (*) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS I D = 250 µA R DS(on) Static Drain-source On Resistance VGS = 10 V VGS = 4.5 V I D = 17.5 A I D = 17.5 A Min. Typ. 1 V 0.014 0.016 0.0195 0.0215 Ω Ω Typ. Max. Unit DYNAMIC Symbol 2/10 Parameter Test Conditions gfs (*) Forward Transconductance VDS =15 V C iss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 ID = 17.5 A Min. 19 S 800 250 60 pF pF pF STD35NF3LL/STD35NF3LL-1 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 15 V ID = 17.5 A VGS = 4.5 V RG = 4.7 Ω (Resistive Load, Figure 3) 17 100 Qg Qgs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 24 V ID = 35 A VGS= 5V 12.5 4.2 5.2 17 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions Min. VDD = 15 V ID = 17.5 A VGS = 4.5 V RG = 4.7 Ω (Resistive Load, Figure 3) 20 21 ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 35 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 35 A di/dt = 100A/µs Tj = 150°C VDD = 15 V (see test circuit, Figure 5) trr Qrr IRRM Test Conditions Min. Typ. V GS = 0 35 44 2.5 Max. Unit 35 140 A A 1.3 V ns nC A (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/10 STD35NF3LL/STD35NF3LL-1 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/10 STD35NF3LL/STD35NF3LL-1 Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature. . . 5/10 STD35NF3LL/STD35NF3LL-1 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/10 STD35NF3LL/STD35NF3LL-1 TO-251 (IPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 B5 0.033 0.3 0.012 B6 0.95 0.037 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 A1 C2 A3 A C H B B3 = 1 = 2 G = = = E B2 = 3 B5 L D B6 L2 L1 0068771-E 7/10 STD35NF3LL/STD35NF3LL-1 TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.031 0.6 1 0.023 0.039 A1 C2 A H A2 C DETAIL ”A” L2 D = 1 = G 2 = = = E = B2 3 B DETAIL ”A” L4 0068772-B 8/10