STMICROELECTRONICS STD12NF06

STD12NF06
N-CHANNEL 60V - 0.08 Ω - 12A IPAK/DPAK
STripFET™ II POWER MOSFET
■
■
■
■
■
TYPE
VDSS
RDS(on)
ID
STD12NF06
60 V
<0.1 Ω
12 A
TYPICAL RDS(on) = 0.08Ω
EXCEPTIONAL dv/dt CAPABILITY
LOW GATE CHARGE
THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX “-1")
SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX “T4")
3
3
1
2
1
IPAK
TO-251
(Suffix “-1”)
DPAK
TO-252
(Suffix “T4”)
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronis unique "Single Feature Size™" stripbased process. The resulting transistor shows extremely
high packing density for low on-resistance, rugged
avalanche characteristics and less critical alignment
steps
therefore
a
remarkable
manufacturing
reproducibility.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGH CURRENT, HIGH SWITCHING SPEED
■ MOTOR CONTROL , AUDIO AMPLIFIERS
■ SOLENOID AND RELAY DRIVERS
■ DC-DC & DC-AC CONVERTERS
■ AUTOMOTIVE ENVIRONMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
VDS
VDGR
VGS
Parameter
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage
Unit
60
V
60
V
± 20
V
ID
Drain Current (continuos) at TC = 25°C
12
A
ID
Drain Current (continuos) at TC = 100°C
8.5
A
IDM(•)
Ptot
dv/dt
(1)
EAS (2)
Tstg
Tj
Drain Current (pulsed)
48
A
Total Dissipation at TC = 25°C
30
W
Derating Factor
0.2
W/°C
Peak Diode Recovery voltage slope
15
V/ns
Single Pulse Avalanche Energy
140
mJ
-55 to 175
°C
Storage Temperature
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area.
December 2001
.
Value
(1) ISD ≤12A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
(2) Starting T j = 25 oC, ID = 6A, VDD = 30V
1/10
STD12NF06
THERMAL DATA
Rthj-case
Rthj-amb
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
Typ
5
100
275
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified)
OFF
Symbol
Parameter
Test Conditions
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating TC = 100°C
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20 V
V(BR)DSS
Min.
Typ.
Max.
60
Unit
V
1
10
µA
µA
±100
nA
ON (*)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS
ID = 250 µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10 V
ID = 6 A
Min.
Typ.
Max.
Unit
2
3
4
V
0.08
0.1
Ω
Typ.
Max.
Unit
DYNAMIC
Symbol
2/10
Parameter
Test Conditions
gfs (*)
Forward Transconductance
VDS = 15 V
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25V, f = 1 MHz, VGS = 0
ID = 6 A
Min.
5
S
315
70
30
pF
pF
pF
STD12NF06
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
td(on)
tr
Turn-on Delay Time
Rise Time
ID = 6 A
VDD = 30 V
RG = 4.7 Ω
VGS = 10 V
(Resistive Load, Figure 3)
7
18
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 48V ID = 12A VGS= 10V
10
3.0
3.5
12
nC
nC
nC
Typ.
Max.
Unit
ns
ns
SWITCHING OFF
Symbol
td(off)
tf
Parameter
Turn-off Delay Time
Fall Time
Test Conditions
Min.
ID = 6 A
VDD = 30 V
RG = 4.7Ω,
VGS = 10 V
(Resistive Load, Figure 3)
17
6
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
ISD
ISDM (•)
Source-drain Current
Source-drain Current (pulsed)
VSD (*)
Forward On Voltage
ISD = 12 A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
di/dt = 100A/µs
ISD = 12 A
VDD = 30 V
Tj = 150°C
(see test circuit, Figure 5)
trr
Qrr
IRRM
Test Conditions
Min.
Typ.
VGS = 0
50
65
3.5
Max.
Unit
12
48
A
A
1.3
V
ns
µC
A
(*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(•)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
3/10
STD12NF06
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/10
STD12NF06
Normalized Gate Threshold Voltage vs Temperature
Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature
.
.
5/10
STD12NF06
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/10
STD12NF06
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
1
0.031
0.039
A1
C2
A3
A
C
H
B
B3
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B6
L2
L1
0068771-E
7/10
STD12NF06
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
1
0.023
0.039
A1
C2
A
H
A2
C
DETAIL "A"
L2
D
=
1
=
G
2
=
=
=
E
=
B2
3
B
DETAIL "A"
L4
0068772-B
8/10
STD12NF06
*on sales type
9/10
STD12NF06
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 2001 STMicroelectronics - All Rights Reserved
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